Current type driving circuit

Abstract

The present disclosure relates to a current-mode driving circuit, comprising: an output module (10) comprising a first MOS transistor (M1); a sampling module (20) comprising a second MOS tube (M2) configured to sample the current flowing through the first MOS tube (M1); the loop control module (30) comprises a third MOS transistor (M3) and a comparison module (32), and the comparison module is configured to compare the current sampled by the second MOS transistor (M2) with the reference current (Iref1) and output the compared difference value to the grid electrode of the third MOS transistor (M3), so that the first MOS transistor (M1) adjusts the output current at the output end (OUT) based on the compared difference value.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to drive circuits, and more particularly to current-mode drive circuits. Background Art

[0002] The driving of some electronic devices requires not only high voltage but also high frequency. In the field of traditional current-type high-voltage driving, it is difficult to meet the requirements of speed, accuracy and high current at the same time. This is because the output drive current accuracy and speed are often incompatible. In terms of frequency, traditional technology usually uses current mirror mirror current to control the output drive current, but the speed of this drive is relatively slow and there will be large errors in high-voltage and high-current applications. Although the drive output current can be adjusted by setting a loop, the high-voltage power tube will bring a large parasitic capacitance, which poses a great challenge to the stability of the loop. Therefore, the loop bandwidth is usually set to a low frequency, which will cause the loop response speed to be very slow. It is expected that the traditional current-type drive circuit can be improved. Summary of the invention

[0003] Embodiments of the present disclosure provide a current-mode driving circuit, aiming to solve one or more of the above problems and other potential problems.

[0004] According to the first aspect of the present disclosure, a current-type drive circuit is provided. The current-type drive circuit includes: an output module, including a first MOS tube and an output end, the drain of the first MOS tube is connected to a power supply node, and the source of the first MOS tube is connected to the output end; a sampling module, including a second MOS tube configured to sample the current flowing through the first MOS tube, the source of the second MOS tube is connected to the output end, and the gate of the second MOS tube is connected to the gate of the first MOS tube; and a loop control module, including: a third MOS tube, the first end of the third MOS tube is connected to the gate of the second MOS tube and the gate of the first MOS tube; and a comparison module, configured to compare the current sampled by the second MOS tube with a reference current, and output the compared difference to the gate of the third MOS tube, so that the first MOS tube adjusts the output current at the output end based on the compared difference.

[0005] In some embodiments, the driving circuit further includes a first voltage clamping module configured to clamp the drain voltage of the third MOS tube; the first voltage clamping module includes a first clamping MOS tube and a second clamping MOS tube; the source of the first clamping MOS tube is connected to the first end of the third MOS tube, and the drain of the first clamping MOS tube is connected to the gate of the second MOS tube and the gate of the first MOS tube; the gate of the first clamping MOS tube is connected to the gate of the second clamping MOS tube, and the source of the second clamping MOS tube is applied with a first bias current; the first clamping MOS tube and the second clamping MOS tube are configured to withstand a first voltage, and the third MOS tube is configured to withstand a second voltage lower than the first voltage; wherein the first clamping MOS tube and the second clamping MOS tube are configured to operate in a switching mode, and the first MOS tube, the second MOS tube and the third MOS tube are configured to operate in a proportional mode.

[0006] In some embodiments, the gate of the first clamping MOS transistor and the gate of the second clamping MOS transistor are connected to a first control node to turn on or off the first clamping MOS transistor and the second clamping MOS transistor based on the potential of the first control node.

[0007] In some embodiments, the driving circuit further includes an impedance attenuation circuit, and the impedance attenuation circuit is configured to reduce the impedance between the gate of the first MOS transistor and the source of the first MOS transistor.

[0008] In some embodiments, the impedance attenuation circuit includes: a first impedance attenuation MOS transistor, the drain of the first impedance attenuation MOS transistor is connected to the gate of the first MOS transistor, and the source of the first impedance attenuation MOS transistor is connected to the output end; a second impedance attenuation MOS transistor, the gate of the second impedance attenuation MOS transistor is connected to the gate of the first impedance attenuation MOS transistor, the source of the second impedance attenuation MOS transistor is connected to the output end, and the drain of the second impedance attenuation MOS transistor is connected to the drain of the second clamping MOS transistor; and a resistor, one end of the resistor is connected to the drain of the first impedance attenuation MOS transistor, and the other end of the resistor is connected to a first connection node where the gate of the second impedance attenuation MOS transistor and the drain of the second impedance attenuation MOS transistor are connected.

[0009] In some embodiments, the first MOS transistor and the second MOS transistor are lateral diffused metal oxide semiconductor (LDMOS).

[0010] In some embodiments, the driving circuit further includes a second voltage clamping module configured to clamp the drain voltage of the first MOS tube and the drain voltage of the second MOS tube, the second voltage clamping module includes a third clamping MOS tube, a fourth clamping MOS tube, and a fifth clamping MOS tube, the source of the third clamping MOS tube is connected to the drain of the second MOS tube, the source of the fourth clamping MOS tube is connected to the drain of the first MOS tube, the gate of the third clamping MOS tube is connected to the gate of the fourth clamping MOS tube, and the drain of the fifth clamping MOS tube is connected to the third clamping MOS tube. A second bias current is applied to the gate of the OS tube and the gate of the fourth clamping MOS tube, and the source of the fifth clamping MOS tube; the third clamping MOS tube, the fourth clamping MOS tube and the fifth clamping MOS tube withstand a first voltage, and the first MOS tube and the second MOS tube are configured to withstand a second voltage lower than the first voltage; wherein the third clamping MOS tube, the fourth clamping MOS tube and the fifth clamping MOS tube are configured to operate in a switching mode, and the first MOS tube, the second MOS tube and the third MOS tube are configured to operate in a proportional mode.

[0011] In some embodiments, the driving circuit further includes a current limiting module, and the current limiting module is configured to clamp the gate voltage of the third clamping MOS tube and the gate voltage of the fourth clamping MOS tube.

[0012] In some embodiments, the current limiting module includes a Zener diode.

[0013] In some embodiments, the comparison module includes a first current mirror, the first current mirror includes a first current mirror MOS tube and a second current mirror MOS tube, the first current mirror MOS tube is configured to convert the sampled current into a first sampling current, the drain of the first current mirror MOS tube is connected to the drain of the second MOS tube, the source of the first current mirror MOS tube is connected to the source of the second current mirror MOS tube, and the gate of the first current mirror MOS tube is connected to the gate of the second current mirror MOS tube.

[0014] In some embodiments, the driving circuit also includes a capacitor, one end of which is connected to a second connection node where the drain of the second current mirror MOS tube and the gate of the third MOS tube are interconnected, and the other end of the capacitor is connected to a third connection node where the source of the first current mirror MOS tube and the source of the first current mirror MOS tube are interconnected, and the third connection node is connected to a power supply node.

[0015] In some embodiments, the first current mirror further includes a first control MOS tube, a source of the first control MOS tube being connected to the third connection node, a drain of the first control MOS tube being connected to the drain of the second MOS tube, and a gate of the first control MOS tube being connected to a second control node so as to turn on or off the first control MOS tube based on the potential of the second control node.

[0016] In some embodiments, the comparison module also includes a second current mirror that converts a first reference current (Iref2) into the reference current, the second current mirror includes a third current mirror MOS tube and a fourth current mirror MOS tube, the gate of the third current mirror MOS tube is connected to the gate of the fourth current mirror MOS tube, the source of the third current mirror MOS tube is connected to the source of the fourth current mirror MOS tube, the drain of the third current mirror MOS tube is connected to the second connection node, and the drain of the fourth current mirror MOS tube is configured to receive the first reference current.

[0017] In some embodiments, the second current mirror further includes a second control MOS tube, the gate of the second control MOS tube is connected to a third control node, and the drain of the second control MOS tube is connected to the gate of the fourth current mirror MOS tube and the gate of the third current mirror MOS tube, so as to turn on or off the second control MOS tube based on the potential of the third control node.

[0018] The loop design according to the present disclosure can achieve accurate sampling and fast response performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the embodiments of the present disclosure will become readily understood by referring to the accompanying drawings and reading the following detailed description. In the accompanying drawings, several embodiments of the present disclosure are shown by way of example and not limitation.

[0020] Figure 1 A schematic circuit diagram of a current-type driving circuit according to a first embodiment of the present disclosure is shown.

[0021] Figure 2 A schematic circuit diagram of a current-type driving circuit according to a second embodiment of the present disclosure is shown.

[0022] Figure 3 A schematic circuit diagram of a current-type driving circuit according to a third embodiment of the present disclosure is shown.

[0023] In the various drawings, the same or corresponding reference numerals represent the same or corresponding parts. DETAILED DESCRIPTION

[0024] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0025] In many electronic devices, in addition to the need to accurately control the driving current, high-frequency driving is also required. As an application example, in the driving applications of light-emitting diodes, the switching frequency of the equipment is getting higher and higher. In addition, these applications are often accompanied by high voltage and high current.

[0026] In the field of traditional current-type high-voltage drive, it is difficult to meet the requirements of speed, accuracy and high current at the same time. In contrast, voltage-type drive can be quickly turned on and off through a logic chain, while current-type drive is very difficult. As described in the background technology section, although the accuracy of the output current used for driving can be controlled through the loop, when driven at high frequency, the high-voltage power tube will bring a large parasitic capacitance, which will affect the stability of the loop. Once the bandwidth of the loop is set to a lower frequency, this will cause the loop response speed to be very slow, which is not suitable for high-frequency applications.

[0027] According to the present disclosure, a current-type drive circuit is proposed, especially a large drive current, which can solve one or more of the above technical problems. The specific implementation structure of the current-type drive circuit according to the embodiment of the present disclosure is described in detail below in conjunction with the accompanying drawings.

[0028] Figure 1 FIG. 1 is a schematic circuit diagram of a current-type driving circuit 100 according to a first embodiment of the present disclosure. Figure 1 As shown, the driving circuit 100 includes an output module 10, a sampling module 20 and a loop control module 30. The output module 10 includes a first MOS tube M1 and an output terminal OUT. The first MOS tube M1 is a main power tube, and the source of the first MOS tube M1 is connected to the output terminal OUT. The drain of the first MOS tube M1 is connected to the power node VM, and the power node VM is configured to provide a high voltage, such as tens of volts. In some embodiments, the voltage is, for example, 10V to 100V. The sampling module 20 includes a second MOS tube M2, which is a sampling MOS tube and is configured to sample the current flowing through the first MOS tube M1. The source of the second MOS tube M2 is connected to the output terminal OUT, and the gate of the second MOS tube M2 is connected to the gate of the first MOS tube M1 (represented as HS_Gate in the figure). In the illustrated embodiment, M1 and M2 are high-voltage N-type LDMOS. It should be understood that M1 and M2 can also be P-type LDMOS.

[0029] The loop control module 30 includes a third MOS tube M3 and a comparison module 32. The first end of the third MOS tube M3 is connected to the gate of the second MOS tube M2 and the gate of the first MOS tube M1. In the illustrated embodiment, M3 is a PMOS tube, and the first end corresponds to the drain of the PMOS tube. It should be understood that this is merely exemplary, and M3 may also be an NMOS tube, and the first end corresponds to the source of the NMOS tube. The comparison module 32 may be a differential comparator, and the comparison module 32 is configured to compare the current sampled by the second MOS tube M2 with the reference current Iref1, and the difference generated by the comparison is output to the gate of the third MOS tube M3, and after being amplified by the third MOS tube M3, it is output to the gate of the first MOS tube M1 and the gate of the second MOS tube M2. Thus, the first MOS tube M1 adjusts the output current at the output terminal OUT based on the current from the third MOS tube M3.

[0030] According to the present disclosure, the first MOS transistor M1, the second MOS transistor M2 and the third MOS transistor M3 all work in a proportional mode, that is, work in an analog region, and the output current at the output terminal OUT can be accurately adjusted based on the reference current Iref1 by the loop control module 30. During operation, the comparison module 32 can compare the current sampled by the second MOS transistor M2 with the reference current Iref1, and output the difference generated by the comparison to the gate of the third MOS transistor M3 for amplification, and the amplified current is further output to the gate of the first MOS transistor M1 and the gate of the second MOS transistor M2, thereby accurately controlling the output current at the output terminal OUT.

[0031] In some embodiments, Figure 1 As shown, the first MOS transistor and the second MOS transistor can be MOS transistors that withstand high voltage, for example, they can be lateral diffused metal oxide semiconductor LDMOS, and the third MOS transistor M3 can be a common MOS transistor (for example, a traditional NMOS transistor or PMOS transistor), and withstand a low voltage lower than the high voltage borne by the first MOS transistor and the second MOS transistor. This is particularly suitable for application scenarios when the power node VM is a high voltage (for example, tens of volts).

[0032] In some embodiments, Figure 1 As shown, the driving circuit 100 may further include a first voltage clamping module 40 configured to clamp the drain voltage of the third MOS transistor M3. By clamping the drain voltage of the third MOS transistor M3, the third MOS transistor M3 can be used in high voltage applications.

[0033] In some embodiments, Figure 1As shown, the first voltage clamping module 40 may include a first clamping MOS tube QM1 and a second clamping MOS tube QM2. The first clamping MOS tube QM1 and the second clamping MOS tube QM2 operate in a switch mode. The first clamping MOS tube QM1 may be connected in series between the drain of the third MOS tube M3 and the gate of the first MOS tube M1, the gate of the first clamping MOS tube QM1 may be connected to the gate of the second clamping MOS tube QM2, and the source of the second clamping MOS tube QM2 may be applied with a first bias current Ib. The drain of the second clamping MOS tube QM2 may be connected to the drain of the second impedance attenuation MOS tube ZM2. In some embodiments, the gate of the first clamping MOS tube QM1 and the gate of the second clamping MOS tube QM2 may also be connected to a control node, and the conduction and closing of the first clamping MOS tube QM1 and the second clamping MOS tube QM2 may be controlled based on the voltage at the control node. In the illustrated embodiment, QM1 and QM2 use P-type LDMOS. It should be understood that the illustrated embodiment is merely exemplary, and QM1 and QM2 may also be N-type LDMOS.

[0034] According to the loop design disclosed in the present invention, accurate sampling and fast response performance can be achieved. The output current used for driving mainly comes from the power tube M1. In some embodiments, the sampling tube M1 will have a mA-level detection current, M3 will also have a mA-level adjustment current, and the remaining MOS tubes will all have uA-level currents. The mA-level current on M2 will all flow to the drive output current, which will reduce the size of the power tube to a certain extent; on the other hand, the current on the power supply voltage VM will flow into the drive output as much as possible, rather than being consumed by the internal circuit, to reduce energy loss.

[0035] In some embodiments, M3 may adopt an NMOS structure, because at the same current capability, the size of NMOS is smaller than that of PMOS, so the use of NMOS architecture will reduce the chip area. It should be understood that this is only exemplary, and M3 may also adopt a PMOS structure. In the present disclosure, by using MOS tube M3 to replace the charge pump, the chip area can be further reduced.

[0036] In addition, in some embodiments, it is also desirable to increase the headroom of M1 and M2 as much as possible. When M2 is a P-type LDMOS, the gate-source voltage Vgs of M2 is fully open, and its drain-source voltage Vds is very small, which is equivalent to outputting the drain end of M3 to the gates of M1 and M2. When OUT is close to VM, the headroom of M1 and M2 depends on the sum of the gate-source voltage Vgs of M1 and M2 and the drain-source voltage of M3. As an example, the drain-source voltage of M3 can be set to several hundred mV. In this case, the minimum headroom between OUT and VM can be between 1-2V. For many applications, the above circuit design meets the requirements.

[0037] According to the present disclosure, a fast response loop can be realized by current comparison, and the drive output current can be accurately adjusted; however, the power tube in the drive circuit (for example, for M1 and M2) will have a large parasitic capacitance, which may affect the stability of the loop. When the loop control module 30 operates in the high frequency region, the impact caused by this parasitic capacitance is greater. In some embodiments, the drive circuit 100 is also provided with an impedance attenuation circuit 50 to increase the bandwidth of the loop.

[0038] like Figure 1 As shown, the driving circuit 100 may further include an impedance attenuation circuit 50. The impedance attenuation circuit 50 is configured to reduce the impedance between the gate of the first MOS transistor M1 and the source of the first MOS transistor M1. Figure 1 As shown, the impedance attenuation circuit 50 may include a first impedance attenuation MOS transistor ZM1, a second impedance attenuation MOS transistor ZM2, and a resistor R1. The drain of the first impedance attenuation MOS transistor ZM1 is connected to the gate of the first MOS transistor M1, and the source of the first impedance attenuation MOS transistor ZM1 is connected to the output terminal OUT. The gate of the second impedance attenuation MOS transistor ZM2 is connected to the gate of the first impedance attenuation MOS transistor ZM1, and the source of the second impedance attenuation MOS transistor ZM2 is connected to the output terminal OUT. One end of the resistor R1 is connected to the drain of the first impedance attenuation MOS transistor ZM1, and the other end of the resistor R1 is connected to a first connection node P1 where the gate of the second impedance attenuation MOS transistor ZM2 and the drain of the second impedance attenuation MOS transistor ZM2 are connected.

[0039] According to this disclosure, Figure 1 In the embodiment shown, the impedance between HS_Gate and the source of the first MOS transistor M1 can be reduced through the low impedance path formed by ZM1, ZM2 and R1. Therefore, the bias current Ib flows into ZM2 through QM2, thereby establishing a bias voltage for the low impedance path. The bias current Ib is significantly smaller than the current of the loop where M2 is located. The principle of increasing the loop bandwidth by the low impedance path is described in detail below.

[0040] When the loop is established and the current of M3 flows to ZM2, Ib can be ignored. ZM1 and ZM2 have the same gate-source voltage and can be low-voltage MOS tubes. ZM1 and ZM2 are both operated in proportional mode. ZM2 is low current, ZM1 is mA current, and the currents of the two are mirrored in a ratio of N:1. In some embodiments, the current of ZM2 is small, about uA level, and the resistor R1 is usually in the KΩ level in the integrated circuit design. Therefore, the equivalent resistance of the impedance attenuation circuit can be simplified to:

[0041]

[0042] Therefore, the equivalent resistance Req can be determined by adjusting the resistance value of R1 and the mirror ratio between ZM1 and ZM2. Through the above low impedance path and the selection of the above parameters, even if there is a high impedance node (such as a current mirror) in the comparison module 32 and a large parasitic capacitance node (such as an LDMOS tube) in the loop, the bandwidth of the loop can be effectively widened.

[0043] Figure 2 FIG. 2 is a schematic circuit diagram of a current-type driving circuit 200 according to a second embodiment of the present disclosure. Figure 2 The embodiment shown is Figure 1 The embodiments shown are similar, and the description will focus on their differences while omitting the description of the same parts.

[0044] In some embodiments, Figure 2 As shown, the comparison module 32 may also include a first current mirror and a capacitor C1. The first current mirror includes a first current mirror MOS tube JM1 and a second current mirror MOS tube JM2. The first current mirror MOS tube JM1 is configured to convert the sampled current into a first sampling current. The drain of the first current mirror MOS tube JM1 is connected to the drain of the second MOS tube M2, the source of the first current mirror MOS tube JM1 is connected to the source of the second current mirror MOS tube JM2, and the gate of the first current mirror MOS tube JM1 is connected to the gate of the second current mirror MOS tube JM2. One end of the capacitor C1 is connected to a second connection node P2 where the drain of the second current mirror MOS tube JM2 and the gate of the third MOS tube M3 are connected to each other, and the other end of the capacitor C1 is connected to a third connection node P3 where the source of the first current mirror MOS tube JM1 and the source of the first current mirror MOS tube JM1 are connected to each other, and the third connection node P3 is connected to the power supply node VM. By setting the capacitor C1, the bandwidth of the loop can be further adjusted.

[0045] In some embodiments, the comparison module 32 may further include a second current mirror that converts the first reference current Iref2 into the reference current Iref1. The second current mirror includes a third current mirror MOS tube JM3 and a fourth current mirror MOS tube JM4, the gate of the third current mirror MOS tube JM3 is connected to the gate of the fourth current mirror MOS tube JM4, the source of the third current mirror MOS tube JM3 is connected to the source of the fourth current mirror MOS tube JM4, the drain of the third current mirror MOS tube JM3 is connected to the second connection node P2, and the drain of the fourth current mirror MOS tube JM4 is configured to receive the first reference current Iref2.

[0046] The design of loop stability mainly focuses on high impedance nodes and large parasitic capacitance nodes, which are easy to introduce poles. The drain outputs of JM2 and JM3 are high impedance nodes, and the gates HS_Gate of the power tubes M1 and M2 are large capacitance nodes. In some embodiments, considering the low-power circuit design, the current of JM3 and JM2 is small, and the output impedance will be relatively large. It can be considered to design the node P2 as the main pole of the loop; by introducing capacitor C1 into the node, the main pole can be set in the mid-frequency band. A large capacitor is introduced into the gate HS_Gate of the power tubes M1 and M2, and the pole at the node P2 must be pushed to the high frequency. The parasitic capacitance of the power tube M1 and the low impedance Req constitute a high-frequency pole. Therefore, the loop bandwidth is expanded by pushing the pole at the gate HS_Gate of the power tube to the high frequency to achieve a fast loop response.

[0047] In some embodiments, the driving circuit 100 may further include one or more control nodes to control the startup of corresponding modules of the driving circuit 100. Figure 2 As shown, the gates of the first clamping MOS transistor QM1 and the second clamping MOS transistor QM2 are connected to the first control node. The first control node may be a logic control node HS_ctrl_B, and the first clamping MOS transistor QM1 and the second clamping MOS transistor QM2 are turned on or off based on the level of the logic control node HS_ctrl_B.

[0048] In some embodiments, Figure 2 As shown, the first current mirror may further include a first control MOS transistor CM1, the source of the first control MOS transistor CM1 is connected to the third connection node P3, the drain of the first control MOS transistor CM1 is connected to the drain of the second MOS transistor M2, and the gate of the first control MOS transistor CM1 is connected to the second control node. The second control node is a logic control node HS_ctrl, and the first control MOS transistor CM1 is turned on or off based on the potential of the second control node.

[0049] In some embodiments, Figure 2 As shown, the second current mirror may further include a second control MOS tube CM2, the gate of the second control MOS tube CM2 is connected to the third control node HS_ctrl_B, the drain of the second control MOS tube CM2 is connected to the gate of the fourth current mirror MOS tube JM4 and the gate of the third current mirror MOS tube JM3, and the second control MOS tube CM2 is turned on or off based on the potential of the third control node.

[0050] In some embodiments, Figure 2 and Figure 3 As shown, the first control node and the third control node are connected to the same logic potential, while the second control node is connected to an opposite logic potential. It should be understood that the logic shown is exemplary.

[0051] In some embodiments, Figure 2 As shown, HS_ctrl is the control logic for turning on and off the drive circuit. When HS_ctrl is high, the drive circuit is turned on, and when HS_ctrl is low, the drive circuit is turned off. Iref2 is the drive reference current, which can be generated externally or internally from the chip; the drive output current Iout is proportional to Iref2. VM is the high-voltage power supply voltage source, FGND is the floating reference potential, and the voltage difference between VM and FGND is low voltage (for example, not more than 5.5V). OUT is the drive output, which will change from GND to VM. ZM1 and ZM2 are in the floating voltage domain between OUT and the gate of the power tube.

[0052] exist Figure 2 When the driving circuit shown is in operation, when HS_ctrl is high, HS_ctrl_B is low, CM1 and CM2 are turned off, and QM1 and QM2 are turned on. Iref2 is mirrored to JM2 via JM1 as the reference current Iref1, and then the drive output current Iout is adjusted through the loop. M1 and M2 have the same gate-source voltage Vgs, and their drain-source voltages Vds differ only by the gate-source voltage of JM1. Considering the channel modulation effect of the high-voltage LDMOS, the drain-source voltages of M1 and M2 differ very little. In high-voltage applications of tens of volts, M2 can almost accurately sample the current of M1. It should be understood that the illustrated embodiments are merely exemplary, and the control logic of each node can be implemented in other ways based on different MOS tubes.

[0053] Figure 3 FIG. 4 is a schematic circuit diagram of a current-type driving circuit 300 according to a third embodiment of the present disclosure. Figure 3 The embodiment shown is Figure 2 The embodiments shown are similar, and the differences are described emphatically, while the description of the same parts is omitted. Figure 2 In the embodiment shown, both power transistors M1 and M2 are MOS transistors (such as LDMOS) that withstand high voltage. M1 and M2 are arranged in a loop, so their gain has a significant impact on the performance of the loop. In the integrated circuit process, the LDMOS is optimized to have a minimum channel length, mainly to facilitate the use of voltage-type drive circuits; while the analog characteristics of the LDMOS tube are not paid much attention to. This may result in the analog characteristics (i.e., proportional characteristics) of M1 and M2 being unsatisfactory in some cases. Figure 3 In the illustrated embodiment, the power transistors M1 and M2 in the loop that are subjected to high voltage are replaced with low-voltage MOS transistors (eg, NMOS or PMOS), which is beneficial for further improving the loop performance.

[0054] In some embodiments, Figure 3As shown, M1 and M2 are low-voltage MOS transistors, for example, NMOS or PMOS. The driving circuit 300 may also include a second voltage clamping module configured to clamp the drain voltage of the first MOS transistor M1 and the drain voltage of the second MOS transistor M2. The second voltage clamping module includes a third clamping MOS transistor QM3, a fourth clamping MOS transistor QM4, and a fifth clamping MOS transistor QM5. The source of the third clamping MOS transistor QM3 is connected to the drain of the second MOS transistor M2, the source of the fourth clamping MOS transistor QM4 is connected to the drain of the first MOS transistor M1, the gate of the third clamping MOS transistor QM3 is connected to the gate of the fourth clamping MOS transistor QM4, the drain of the fifth clamping MOS transistor QM5 is connected to the gate of the third clamping MOS transistor QM3 and the gate of the fourth clamping MOS transistor QM4, and the source of the fifth clamping MOS transistor QM5 is applied with a second bias current Ib1.

[0055] According to the present disclosure, the third clamping MOS tube QM3, the fourth clamping MOS tube QM4 and the fifth clamping MOS tube QM5 are tolerant to a first voltage, and the first MOS tube M1 and the second MOS tube M2 are configured as MOS tubes that tolerate a second voltage lower than the first voltage. M1 and M2 are low-voltage MOS tubes with good analog characteristics. The output current of M3 adjusts the gate potential of M1 and M2 on the equivalent impedance Req. QM3, QM4, and QM5 do not act on the loop gain. Therefore, the MOS tubes in the loop adjustment are all low voltage, and the performance can be further guaranteed.

[0056] In some embodiments, Figure 3 As shown, the driving circuit 300 also includes a current limiting module, which is configured to clamp the gate voltage of the third clamping MOS tube QM3 and the gate voltage of the fourth clamping MOS tube QM4. In some embodiments, the current limiting module may include a Zener tube Z1, and Z1 is used to clamp the gate voltages of QM3 and QM4 to turn on QM3 and QM4. Ib1 is the bias current of Z1. QM5 is, for example, a high-voltage P-type LDMOS tube, which is used to clamp the low-voltage MOS tube. When the high-side drive is turned on, QM5 is turned on; when the high-side drive is turned off, QM5 is turned off, there is no current on Z1, and the gate voltages of the power tubes QM3 and QM4 are pulled down.

[0057] According to the present disclosure, by nesting the low-voltage MOS tube with the high-voltage LDMOS, the error introduced by the inaccuracy of the high-voltage LDMOS tube can be avoided, so that the drive output current can be better adjusted. On the other hand, the drive circuit has a current limiting function. The gate voltage of QM3 is clamped by Z1, and the voltage is fixed, which is the superposition of the gate-source voltage of QM3 and the drain-source voltage of M1. When OUT or the reference current generating circuit is short-circuited, the gate-source voltage Vgs of M1 increases rapidly; if the drive output current is to be increased, the gate-source voltage Vgs of QM3 must be increased, which will reduce the drain-source voltage of M1, causing M1 to enter the linear region, and finally the current on QM3 and M1 reaches a balanced state. Thus, the current limiting function can be achieved. By limiting the maximum current that the drive circuit can output, this has a protective effect on the drive circuit in a short-circuit state, thereby improving the reliability of the drive circuit. On the other hand, low-voltage MOS tubes are used to adjust the output drive current in the loop. Under the same current capacity, low-voltage MOS tubes have a smaller area than high-voltage LDMOS, so their gate parasitic capacitance will also be reduced; this can set the secondary point frequency to a higher frequency, further increasing the loop bandwidth, which is more conducive to achieving high-speed response to meet high-frequency applications.

[0058] In addition, although each operation is described in a specific order, this should be understood as requiring such operation to be performed in the specific order shown or in a sequential order, or requiring that all illustrated operations should be performed to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation can also be implemented in multiple implementations individually or in any suitable sub-combination mode.

[0059] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

[0060] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A current-type driving circuit, comprising: An output module (10) comprises a first MOS transistor (M1) and an output end (OUT), wherein the drain of the first MOS transistor (M1) is connected to a power supply node (VM), and the source of the first MOS transistor (M1) is connected to the output end (OUT); A sampling module (20), comprising a second MOS tube (M2) configured to sample a current flowing through the first MOS tube (M1), wherein a source of the second MOS tube (M2) is connected to the output end (OUT), and a gate of the second MOS tube (M2) is connected to a gate of the first MOS tube (M1); as well as The loop control module (30) comprises: a third MOS transistor (M3), wherein a first end of the third MOS transistor (M3) is connected to a gate of the second MOS transistor (M2) and a gate of the first MOS transistor (M1); as well as A comparison module (32) is configured to compare the current sampled by the second MOS transistor (M2) with a reference current (Iref1), and output the compared difference to the gate of the third MOS transistor (M3), so that the first MOS transistor (M1) adjusts the output current at the output terminal (OUT) based on the compared difference.

2. The driving circuit according to claim 1, wherein the driving circuit further comprises a first voltage clamping module (40) configured to clamp the drain voltage of the third MOS tube (M3); the first voltage clamping module (40) comprises a first clamping MOS tube (QM1) and a second clamping MOS tube (QM2); The source of the first clamping MOS transistor (QM1) is connected to the first end of the third MOS transistor (M3), and the drain of the first clamping MOS transistor (QM1) is connected to the gate of the second MOS transistor (M2) and the gate of the first MOS transistor (M1); The gate of the first clamping MOS transistor (QM1) is connected to the gate of the second clamping MOS transistor (QM2), and a first bias current (Ib) is applied to the source of the second clamping MOS transistor (QM2); The first clamping MOS transistor (QM1) and the second clamping MOS transistor (QM2) are configured to withstand a first voltage, and the third MOS transistor (M3) is configured to withstand a second voltage lower than the first voltage; The first clamping MOS transistor (QM1) and the second clamping MOS transistor (QM2) are configured to operate in a switch mode, and the first MOS transistor (M1), the second MOS transistor (M2) and the third MOS transistor (M3) are configured to operate in a proportional mode.

3. The driving circuit according to claim 2, wherein the gate of the first clamping MOS transistor (QM1) and the gate of the second clamping MOS transistor (QM2) are connected to a first control node so as to turn on or off the first clamping MOS transistor (QM1) and the second clamping MOS transistor (QM2) based on the potential of the first control node.

4. The driving circuit according to any one of claims 2 to 3, further comprising an impedance attenuation circuit (50), wherein the impedance attenuation circuit (50) is configured to reduce the impedance between the gate of the first MOS transistor (M1) and the source of the first MOS transistor (M1).

5. The driving circuit according to claim 4, wherein the impedance attenuation circuit (50) comprises: a first impedance attenuation MOS transistor (ZM1), wherein the drain of the first impedance attenuation MOS transistor (ZM1) is connected to the gate of the first MOS transistor (M1), and the source of the first impedance attenuation MOS transistor (ZM1) is connected to the output end (OUT); a second impedance attenuation MOS transistor (ZM2), wherein the gate of the second impedance attenuation MOS transistor (ZM2) is connected to the gate of the first impedance attenuation MOS transistor (ZM1), the source of the second impedance attenuation MOS transistor (ZM2) is connected to the output end (OUT), and the drain of the second impedance attenuation MOS transistor (ZM2) is connected to the drain of the second clamping MOS transistor (QM2); as well as A resistor (R1), one end of the resistor (R1) is connected to the drain of the first impedance reduction MOS transistor (ZM1), and the other end of the resistor (R1) is connected to a first connection node (P1) at which the gate of the second impedance reduction MOS transistor (ZM2) is connected to the drain of the second impedance reduction MOS transistor (ZM2).

6. The driving circuit according to any one of claims 2 to 3 and 5, wherein the first MOS transistor (M1) and the second MOS transistor (M2) are laterally diffused metal oxide semiconductors (LDMOS).

7. The driving circuit according to any one of claims 1 to 3 and 5, wherein the driving circuit further comprises a second voltage clamping module configured to clamp the drain voltage of the first MOS tube (M1) and the drain voltage of the second MOS tube (M2), The second voltage clamping module includes a third clamping MOS transistor (QM3), a fourth clamping MOS transistor (QM4), and a fifth clamping MOS transistor (QM5). The source of the third clamping MOS transistor (QM3) is connected to the drain of the second MOS transistor (M2), the source of the fourth clamping MOS transistor (QM4) is connected to the drain of the first MOS transistor (M1), The gate of the third clamping MOS transistor (QM3) is connected to the gate of the fourth clamping MOS transistor (QM4), The drain of the fifth clamping MOS transistor (QM5) is connected to the gate of the third clamping MOS transistor (QM3) and the gate of the fourth clamping MOS transistor (QM4), and the second bias current (Ib1) is applied to the source of the fifth clamping MOS transistor (QM5); The third clamping MOS transistor (QM3), the fourth clamping MOS transistor (QM4) and the fifth clamping MOS transistor (QM5) are tolerant to a first voltage, and the first MOS transistor (M1) and the second MOS transistor (M2) are configured as MOS transistors tolerant to a second voltage lower than the first voltage; The third clamping MOS transistor (QM3), the fourth clamping MOS transistor (QM4) and the fifth clamping MOS transistor (QM5) are configured to operate in a switching mode, and the first MOS transistor (M1), the second MOS transistor (M2) and the third MOS transistor (M3) are configured to operate in a proportional mode.

8. The driving circuit according to claim 7, further comprising a current limiting module, wherein the current limiting module is configured to clamp the gate voltage of the third clamping MOS tube (QM3) and the gate voltage of the fourth clamping MOS tube (QM4). 9 . The driving circuit according to claim 8 , wherein the current limiting module comprises a Zener diode.

10. The driving circuit according to any one of claims 1-3, 5, 8, and 9, wherein the comparison module (32) comprises a first current mirror, the first current mirror comprises a first current mirror MOS tube (JM1) and a second current mirror MOS tube (JM2), the first current mirror MOS tube (JM1) being configured to convert the sampled current into a first sampling current, The drain of the first current mirror MOS tube (JM1) is connected to the drain of the second MOS tube (M2), the source of the first current mirror MOS tube (JM1) is connected to the source of the second current mirror MOS tube (JM2), and the gate of the first current mirror MOS tube (JM1) is connected to the gate of the second current mirror MOS tube (JM2).

11. The driving circuit according to claim 10, further comprising a capacitor (C1), one end of the capacitor (C1) being connected to a second connection node (P2) at which the drain of the second current mirror MOS tube (JM2) and the gate of the third MOS tube (M3) are interconnected, the other end of the capacitor (C1) being connected to a third connection node (P3) at which the source of the first current mirror MOS tube (JM1) and the source of the first current mirror MOS tube (JM1) are interconnected, and the third connection node (P3) is connected to a power supply node (VM).

12. The driving circuit according to claim 11, wherein the first current mirror further comprises a first control MOS tube (CM1), a source of the first control MOS tube (CM1) being connected to the third connection node (P3), a drain of the first control MOS tube (CM1) being connected to the drain of the second MOS tube (M2), and a gate of the first control MOS tube (CM1) being connected to a second control node so as to turn on or off the first control MOS tube (CM1) based on the potential of the second control node.

13. The driving circuit according to claim 12, wherein the comparison module (32) further comprises a second current mirror for converting the first reference current (Iref2) into the reference current (Iref1), the second current mirror comprising a third current mirror MOS tube (JM3) and a fourth current mirror MOS tube (JM4), the gate of the third current mirror MOS tube (JM3) being connected to the gate of the fourth current mirror MOS tube (JM4), the source of the third current mirror MOS tube (JM3) being connected to the source of the fourth current mirror MOS tube (JM4), the drain of the third current mirror MOS tube (JM3) being connected to the second connection node (P2), and the drain of the fourth current mirror MOS tube (JM4) being configured to receive the first reference current (Iref2).

14. The driving circuit according to claim 13, wherein the second current mirror further comprises a second control MOS tube (CM2), a gate of the second control MOS tube (CM2) being connected to a third control node, a drain of the second control MOS tube (CM2) being connected to a gate of the fourth current mirror MOS tube (JM4) and a gate of the third current mirror MOS tube (JM3), so as to turn on or off the second control MOS tube (CM2) based on the potential of the third control node.

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