Metal gate filling method

Abstract

The invention discloses a metal gate filling method which comprises the steps that a high dielectric constant layer and a first material layer are sequentially deposited in a gate trench of a substrate structure, and the first material layer is formed on the surface of the high dielectric constant layer. And depositing a sacrificial layer in the gate trench based on the first material layer, and etching to remove a part of thickness of the sacrificial layer in the gate trench so as to expose a part of the first material layer on the side wall of the top of the gate trench. And sequentially etching and removing the exposed first material layer and the exposed high dielectric constant layer based on the exposed position of the first material layer to form a first opening. And removing the remaining sacrificial layer in the gate trench to form a second opening at the position where the remaining sacrificial layer is removed, the opening width of the first opening being greater than the opening width of the second opening. Therefore, the phenomenon that the bottom cannot be completely deposited due to the fact that the top of the gate trench is deposited too thick is avoided, cavities or gaps are effectively prevented from being formed in the bottom of the gate electrode, and the electrical performance of the gate electrode is improved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor manufacturing, and in particular to a metal gate filling method. Background Art

[0002] In advanced manufacturing processes, in order to meet the requirements of device performance, a high-K metal gate (HK gate) is introduced. The process of forming HK gate includes two processes: HK First and HK Last. With the continuous improvement of the process, the gate size is gradually reduced, resulting in increasing difficulty in filling the metal gate electrode material. Especially in the HK Last process, since HK deposition will reduce the process window for subsequent electrode material filling, it will become more difficult to deposit the gate electrode material into the gate trench.

[0003] like Figure 1 As shown, the deposition rate at the top edge of the gate trench is always greater than the deposition rate at the bottom, resulting in the gate electrode material at the top edge being too thick, which can easily seal the gate opening and form a void / seam at the bottom, which will affect the electrical performance of the gate electrode.

[0004] In the prior art, physical vapor deposition (PVD) is used to deposit bulk aluminum (bulk Al) and hot reflow technology is used to improve the morphology of aluminum deposition to avoid defects such as voids or seams; or at low temperatures, chemical vapor deposition (CVD) process is used to deposit metal W to replace Al. However, compared with the PVD aluminum deposition process, the performance of the device will be reduced by these two methods.

[0005] Therefore, it is necessary to provide a metal gate filling method to avoid the above problems. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a metal gate filling method to avoid the problem of excessively fast deposition rate at the top edge of the gate trench leading to formation of voids or gaps at the bottom of the gate electrode.

[0007] In order to achieve the above object and other related objects, the present invention provides a metal gate filling method, comprising the following steps:

[0008] Providing a substrate structure, in which a gate trench is formed;

[0009] Depositing a high dielectric constant layer and a first material layer in the gate trench in sequence, so that the high dielectric constant layer covers the bottom and sidewalls of the gate trench, and the first material layer is formed on the surface of the high dielectric constant layer;

[0010] Depositing a sacrificial layer in the gate trench based on the first material layer so that the sacrificial layer fills the gate trench;

[0011] Etching and removing a portion of the sacrificial layer in the gate trench to expose a portion of the first material layer on the top sidewall of the gate trench;

[0012] Sequentially etching and removing the exposed first material layer and the exposed high dielectric constant layer based on the exposed position of the first material layer to form a first opening;

[0013] The remaining sacrificial layer in the gate trench is removed to form a second opening at the position where the remaining sacrificial layer is removed, and the opening width of the first opening is greater than the opening width of the second opening.

[0014] Optionally, a substrate structure is provided, and a gate trench is formed in the substrate structure, including:

[0015] providing a substrate;

[0016] forming a gate oxide layer and a polysilicon gate layer in sequence on the surface of the substrate;

[0017] Etching the polysilicon gate layer to form a plurality of spaced polysilicon gate structures on the surface of the gate oxide layer;

[0018] forming a spacer layer on the sidewall of the polysilicon gate structure and the surface of the exposed gate oxide layer;

[0019] Depositing an oxide layer in the space between adjacent sidewall layers so that the oxide layer is flush with the sidewall layer and the polysilicon gate structure;

[0020] The polysilicon gate structure is removed to form a gate trench.

[0021] Optionally, after the step of removing the remaining sacrificial layer in the gate trench by etching to form a second opening at the position where the remaining sacrificial layer is removed, the method further includes:

[0022] Depositing a second material layer in the gate isolation groove so that the second material layer covers the sidewalls of the first opening and the second opening at the same time;

[0023] A third material layer is deposited on the surface of the second material layer.

[0024] Optionally, after depositing the third material layer on the surface of the second material layer, the method further comprises:

[0025] A metal seed layer is deposited on the surface of the third material layer.

[0026] Optionally, after depositing a metal seed layer on the surface of the third material layer, the method further comprises:

[0027] A metal electrode layer is deposited on the surface of the metal seed layer so that the metal electrode layer completely fills the gate trench.

[0028] Optionally, the sacrificial layer is a bottom anti-reflection layer or a carbon coating; preferably, in the step of filling the gate trench with the sacrificial layer, the thickness of the sacrificial layer is

[0029] Optionally, the step of sequentially etching and removing the exposed first material layer and the exposed high dielectric constant layer based on the exposed position of the first material layer includes:

[0030] The exposed portion of the first material layer and the exposed high dielectric constant layer are etched away by wet etching.

[0031] Optionally, the step of etching and removing a portion of the sacrificial layer in the gate trench includes:

[0032] A partial thickness of the sacrificial layer in the gate trench is etched away by dry etching. Preferably, the partial thickness accounts for at least 1 / 30 of the thickness of the entire sacrificial layer and at most 1 / 8 of the thickness of the entire sacrificial layer.

[0033] Optionally, the step of removing the remaining sacrificial layer in the gate trench includes:

[0034] The remaining sacrificial layer in the gate trench is removed by an ashing process.

[0035] Optionally, the step of removing the remaining sacrificial layer in the gate trench by an ashing process further includes:

[0036] Ozone is introduced to remove pollutants generated in the process of removing the sacrificial layer by an ashing process.

[0037] Compared with the prior art, the metal gate filling method of the present invention has at least the following beneficial effects:

[0038] The metal filling method of the present invention comprises depositing a high dielectric constant layer and a first material layer in the gate trench of the substrate structure in sequence, so that the high dielectric constant layer covers the bottom and sidewalls of the gate trench, and the first material layer is formed on the surface of the high dielectric constant layer. Based on the first material layer, a sacrificial layer is deposited in the gate trench so that the sacrificial layer fills the gate trench, and a portion of the thickness of the sacrificial layer in the gate trench is etched away to expose a portion of the first material layer on the top sidewall of the gate trench. Based on the exposed position of the first material layer, the exposed first material layer and the exposed high dielectric constant layer are etched away in sequence to form a first opening. The remaining sacrificial layer in the gate trench is removed to form a second opening at the position where the remaining sacrificial layer is removed, and the opening width of the first opening is greater than the opening width of the second opening. Thus, the present invention first forms a first opening at the top of the gate trench and a second opening at the bottom of the gate trench. Since the opening width of the first opening is greater than the opening width of the second opening, when the metal electrode is deposited in the gate groove, even if the deposition rate at the top of the gate groove is too fast, the first opening with a larger opening width will be filled first, and the phenomenon of the gate electrode being unable to be completely deposited at the bottom due to excessive deposition in the first opening will not occur, which effectively avoids the formation of voids or gaps at the bottom of the gate electrode and improves the deposition quality and electrical performance of the gate electrode.

[0039] Furthermore, the first material layer in the present invention can be used as an etching barrier layer, and the first material layer can protect the high dielectric constant layer during the process of etching and removing the sacrificial layer, ensuring that the etching process will not damage the bottom high dielectric constant medium. Furthermore, the first material layer can also be used as one of the functional layers, without the need for a removal step, thus simplifying the preparation process.

[0040] Furthermore, the sacrificial layer in the present invention is a bottom anti-reflection coating (Bottom Anti-Reflection Coating, BARC) or a carbon coating (Spin On Carbon, SOC), wherein the carbon coating is a polymer with a high carbon content. BARC or SOC can be directly spin-coated into the gate groove, and the preparation process is simple; and the BARC / SOC material has strong fluidity and has a high filling capacity for graphics of different densities, and its application range is wider. The sacrificial layer can be removed by the subsequent ashing process, and the polymer contaminants generated by the ashing process can be removed by introducing ozone. The preparation process is simple and easy to operate, and will not have a significant impact on the entire process, thereby simplifying the preparation process and reducing the preparation cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 This is a scanning electron microscope photo of a gate material deposited in a gate partition in the prior art;

[0042] Figure 2 is a method flow chart of a metal gate filling method described in an embodiment of the present invention;

[0043] Figure 3 A schematic structural diagram of a substrate structure is provided in an embodiment of the present invention;

[0044] Figure 4 It is a schematic diagram of the structure after a high dielectric constant layer, a first material layer and a sacrificial layer are sequentially formed in the gate trench in an embodiment of the present invention;

[0045] Figure 5 It is a schematic diagram of the structure after etching a sacrificial layer of a partial thickness in an embodiment of the present invention;

[0046] Figure 6 It is a schematic diagram of the structure after the first material layer and the high dielectric constant layer are exposed by etching a portion of the sacrificial layer to form a first opening in an embodiment of the present invention;

[0047] Figure 7 It is a schematic diagram of the structure after the remaining sacrificial layer is etched away to form a second opening in an embodiment of the present invention;

[0048] Figure 8 It is a schematic diagram of the structure after a second material layer, a third material layer, a metal seed layer and a metal electrode layer are sequentially deposited based on the first opening and the second opening in an embodiment of the present invention.

[0049] List of reference numerals:

[0050] 100 Substrate

[0051] 101 Gate Oxide

[0052] 102 side wall layer

[0053] 103 Oxide layer

[0054] 104 Gate trench

[0055] 200 High dielectric constant layer

[0056] 300 First material layer

[0057] 400 Sacrificial Layer

[0058] 500 First Opening

[0059] 600 Second Opening

[0060] 700 Second Material Layer

[0061] 800 Third Material Layer

[0062] 900 Metal seed layer

[0063] 1000 Metal electrode layer DETAILED DESCRIPTION

[0064] The following specific embodiments illustrate the embodiments of the present invention, and those familiar with the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0065] It should be noted that the diagrams provided in the embodiments of the present invention are only used to illustrate the basic concept of the present invention in a schematic manner. Although the diagrams only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of each component can be changed at will during actual implementation, and the layout of the components may also be more complex. The structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions that can be implemented in this application, so they have no technical substantive significance. Any structural modification, change in proportional relationship or adjustment of size should still fall within the scope of the technical content disclosed in this application without affecting the effects and purposes that can be achieved by the present invention.

[0066] This embodiment discloses a metal gate filling method to increase the filling process window at the top corner of the gate trench for filling the metal gate, so as to avoid the gate material at the top corner of the gate trench being too thick to block the deposition of the bottom gate material, thereby generating a void defect at the bottom and affecting the electrical performance of the gate. Specifically, the metal gate filling method described in this embodiment refers to Figure 2 , including the following steps:

[0067] S101: providing a substrate structure, and forming a gate trench in the substrate structure;

[0068] Specifically, refer to Figure 3 , a substrate structure is provided, and the substrate structure can be formed by the following formation steps: first, a substrate 100 is provided, a gate oxide layer 101 and a polysilicon gate layer (not shown in the figure) are sequentially formed on the surface of the substrate 100, and the polysilicon gate layer is etched to form a plurality of spaced polysilicon gate structures on the surface of the gate oxide layer 101. A sidewall layer 102 is formed on the sidewall of the polysilicon gate structure and the surface of the exposed gate oxide layer 101, an oxide layer 103 is deposited in the space between adjacent sidewall layers 102, the oxide layer 103 and the sidewall layer 102 are made flush with the polysilicon gate structure, and the polysilicon gate structure is removed to form a gate trench 104.

[0069] Optionally, the substrate 100 may include any semiconductor material, and the semiconductor material may include Si, SiC, SiGe, SiGeC, Ge alloy, GeAs, InAs, etc. Optionally, the semiconductor substrate may include an epitaxial layer. The semiconductor substrate may also include an organic semiconductor or a layered semiconductor of Si / SiGe, silicon on insulator (SOI) or insulator SiGe. In the present embodiment, the substrate 100 is a silicon substrate, and the sidewall layer 102 is a silicon nitride layer. The gate oxide layer 101 and the oxide layer 103 are both silicon dioxide layers. Since silicon dioxide has good insulation, thermal stability, low defect density, small lattice mismatch with Si substrate, and can form a good interface with Si, it can be used as a material for forming a gate oxide layer.

[0070] S102: depositing a high dielectric constant layer and a first material layer in the gate trench in sequence, so that the high dielectric constant layer covers the bottom and sidewalls of the gate trench, and the first material layer is formed on the surface of the high dielectric constant layer;

[0071] Specifically, refer to Figure 4 , a high dielectric constant layer 200 and a first material layer 300 are sequentially deposited in the gate trench, so that the high dielectric constant layer 200 covers the bottom and sidewalls of the gate trench, and the first material layer 300 is formed on the surface of the high dielectric constant layer 200. Optionally, the high dielectric constant layer 200 can be H f O, H f ZrO、H f ZrON、H f SiON、H f TaO, Al2O3 and Si3N4 etc. can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD) etc., so that the deposited high dielectric constant layer 200 has good coverage on the sidewall surface of the gate trench. f The material of the first material layer 300 may be TaN, Ta, TaAl, or may also be a thin film layer of titanium, titanium aluminum nitride, titanium aluminum, cobalt, or lanthanum, and may also be formed by a suitable process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0072] S103: depositing a sacrificial layer in the gate trench based on the first material layer, so that the sacrificial layer fills the gate trench;

[0073] Specifically, continue to refer to Figure 4, a sacrificial layer 400 is deposited in the gate trench based on the first material layer 300, so that the sacrificial layer 400 fills the gate trench. Optionally, the sacrificial layer 400 can be a bottom anti-reflection coating (BARC) or a carbon coating (Spin On Carbon, SOC), wherein the carbon coating is a polymer with a high carbon content. BARC or SOC can be directly spin-coated into the gate trench. In this embodiment, the thickness of the deposited sacrificial layer 400 is between

[0074] It should be noted that the sacrificial layer 400 deposited in the gate trench needs to completely fill the trench and be higher than the trench by a certain height. Due to the width error of each gate trench, some trenches can be filled with the sacrificial layer 400 in the same process, while some gate trenches cannot be filled. Completely filling the gate trench with the sacrificial layer 400 and raising it to a certain height can ensure that each gate trench can be filled, so as to avoid adverse effects on subsequent etching process if individual gate trenches are not completely filled with the sacrificial layer 400.

[0075] S104: etching and removing a portion of the sacrificial layer in the gate trench to expose a portion of the first material layer on the sidewall of the gate trench;

[0076] Specifically, refer to Figure 5 , a portion of the thickness of the sacrificial layer 400 in the gate trench is etched away to expose a portion of the first material layer 300 on the sidewall of the gate trench. It should be noted that the thickness of the sacrificial layer 400 in the gate trench should be at least 1 / 30 of the thickness of the entire sacrificial layer 400, and at most 1 / 8 of the thickness of the entire sacrificial layer 400. In this embodiment, a dry etching process can be used to remove a portion of the thickness of the sacrificial layer 400 at the top of the gate trench, and the thickness removal amount of the sacrificial layer 400 is Dry etching processes include, but are not limited to, reactive ion etching (RIE), ion beam etching, and plasma etching. For example, when plasma etching is used, the etching gas may be an oxygen-based gas, and specifically, a plasma gas with relatively low radio frequency energy and capable of generating pressure and high density may be used to achieve dry etching. The etching gas for dry etching may also be hydrogen bromide, carbon tetrafluoride, or nitrogen trifluoride gas. The above etching method is merely exemplary and is not limited to this method, and those skilled in the art may choose other commonly used methods.

[0077] S105: etching and removing the exposed first material layer and the exposed high dielectric constant layer in sequence based on the exposed position of the first material layer to form a first opening;

[0078] Specifically, refer to Figure 6After removing part of the sacrificial layer 400 in the gate trench, the exposed first material layer 300 and the exposed high dielectric constant layer 200 are sequentially etched away based on the exposed position of the first material layer 300 to form a first opening 500. Optionally, wet etching can be used to etch away the exposed first material layer 300 and the exposed high dielectric constant layer 200. Wet etching can be specifically performed using diluted hydrofluoric acid, and the height of the first material layer 300 and the high dielectric constant layer 200, that is, the height of the first opening 500, is controlled by controlling the etching time.

[0079] S106: removing the remaining sacrificial layer in the gate trench to form a second opening at the position where the remaining sacrificial layer is removed, and the opening width of the first opening is greater than the opening width of the second opening.

[0080] Specifically, refer to Figure 7 , remove the remaining sacrificial layer 400 in the gate trench. Optionally, an ashing process can be used to remove the remaining sacrificial layer 400 in the gate trench. The ashing process described in this embodiment is a common process in the prior art and will not be described in detail here. After the ashing process, some polymers may generally remain, which may contaminate or affect subsequent processes.

[0081] This embodiment further includes cleaning the polymer generated in the ashing process by introducing ozone after the ashing process, thereby completely removing the polymer contaminants generated in the removal of the sacrificial layer without affecting the subsequent processes.

[0082] It should be noted that, in this embodiment, a first material layer 300 is formed on the surface of the high dielectric constant layer 200 to etch and form the second opening. The first material layer 300 can protect the high dielectric constant layer during the process of etching and removing the sacrificial layer, ensuring that the etching process will not damage the bottom high dielectric constant medium.

[0083] After the remaining sacrificial layer 400 in the gate trench is completely removed, a second opening 600 is formed at the position of the remaining sacrificial layer 400 , and the opening width of the first opening 500 is greater than the opening width of the second opening 600 .

[0084] In this embodiment, after step S106, the method further includes: S107: depositing a second material layer based on the first opening and the second opening so that the second material layer covers the sidewalls of the first opening and the second opening at the same time, and depositing a third material layer on the surface of the second material layer.

[0085] Specifically, refer to Figure 8The second material layer 700 is deposited based on the first opening 500 and the second opening 600, so that the second material layer 700 simultaneously covers the sidewalls of the first opening 500 and the second opening 600. At the same time, the third material layer 800 is deposited based on the surface of the second material layer 700.

[0086] In the present embodiment, the first material layer 300, the second material layer 700 and the third material layer 800 are formed as a functional layer. The functional layer is formed into a multilayer structure. The materials of the first material layer 300, the second material layer 700 and the third material layer 800 can be TaN, Ta, TaAl or can also be thin film layers such as titanium, titanium aluminum nitride, titanium aluminum, cobalt or lanthanum, and can also be formed by suitable processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD). In the present embodiment, the material of the first material layer 300 is a titanium nitride layer, the second material layer 700 is a tantalum nitride layer, and the third material layer 800 is a titanium nitride layer. In other embodiments, the first material layer 300 can also be formed as a barrier layer or other functional layers, and the second material layer 700 and the third material layer 800 are formed as functional layers. Alternatively, the first material layer 300 and the second material layer 700 are formed as barrier layers, and the third material layer 800 is formed as a functional layer. This embodiment does not limit the specific function of the first material layer 300.

[0087] Optionally, continue to refer to Figure 8 , after depositing the second material layer 700 and the third material layer 800 in sequence based on the first opening 500 and the second opening 600, it also includes depositing a metal seed layer 900 on the surface of the third material layer 800, and the metal seed layer 900 is used to form a metal electrode layer 1000. Then, after depositing the metal seed layer 900, it also includes depositing the metal electrode layer 1000 based on the formed metal seed layer 900, so that the metal electrode layer 1000 completely fills the gate trench. Optionally, the metal seed layer 900 and the metal electrode layer 1000 are made of the same material, which can be tungsten metal. The metal seed layer 900 and the metal electrode layer 1000 can be deposited and formed by a chemical vapor deposition process.

[0088] In summary, the metal filling method described in the present invention includes sequentially depositing a high dielectric constant layer and a first material layer in the gate trench of the substrate structure, so that the high dielectric constant layer covers the bottom and sidewalls of the gate trench, and the first material layer is formed on the surface of the high dielectric constant layer. Based on the first material layer, a sacrificial layer is deposited in the gate trench, so that the sacrificial layer fills the gate trench, and a portion of the thickness of the sacrificial layer in the gate trench is etched away to expose a portion of the first material layer on the top sidewall of the gate trench. Based on the exposed position of the first material layer, the exposed first material layer and the exposed high dielectric constant layer are sequentially etched away to form a first opening. The remaining sacrificial layer in the gate trench is removed to form a second opening at the position where the remaining sacrificial layer is removed, and the opening width of the first opening is greater than the opening width of the second opening. Therefore, the present invention forms a first opening at the top of the gate trench and a second opening at the bottom of the gate trench. Since the opening width of the first opening is greater than the opening width of the second opening, when the metal electrode is deposited in the gate trench, even if the deposition rate at the top of the gate trench is too fast, the first opening with a larger opening width will be filled first, and the phenomenon of incomplete deposition at the bottom due to excessive deposition in the first opening will not occur, which effectively avoids the formation of voids or gaps at the bottom of the gate electrode and improves the deposition quality and electrical performance of the gate electrode.

[0089] Furthermore, the first material layer in the present invention can be used as an etching barrier layer. The first material layer 300 can protect the high dielectric constant layer during the process of etching and removing the sacrificial layer, ensuring that the etching process will not damage the bottom high dielectric constant medium. Furthermore, the first material layer can also be used as one of the functional layers, without the need for a removal step, thus simplifying the preparation process.

[0090] Furthermore, the sacrificial layer in the present invention is a bottom anti-reflection coating (Bottom Anti-Reflection Coating, BARC) or a carbon coating (Spin On Carbon, SOC), wherein the carbon coating is a polymer with a high carbon content. BARC or SOC can be directly spin-coated into the gate groove, the preparation process is simple, and the fluidity of the BARC / SOC material is strong, and it has a high filling capacity for graphics of different densities, and its application range is wider. The sacrificial layer can be removed by the subsequent ashing process, and the polymer pollutants generated by the ashing process can be removed by introducing ozone. The preparation process is simple and easy to operate, and will not have a significant impact on the entire process, simplifying the preparation process and reducing the preparation cost.

[0091] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A metal gate filling method, characterized in that: The following steps are involved: Providing a substrate structure, wherein a gate trench is formed in the substrate structure; Depositing a high dielectric constant layer and a first material layer in the gate trench in sequence, so that the high dielectric constant layer covers the bottom and sidewalls of the gate trench, and the first material layer is formed on the surface of the high dielectric constant layer; Depositing a sacrificial layer in the gate trench based on the first material layer, so that the sacrificial layer fills the gate trench; Etching and removing a portion of the sacrificial layer in the gate trench to expose a portion of the first material layer on the top sidewall of the gate trench; Sequentially etching and removing the exposed first material layer and the exposed high dielectric constant layer based on the exposed position of the first material layer to form a first opening; The remaining sacrificial layer in the gate trench is removed to form a second opening at the position where the remaining sacrificial layer is removed, and the opening width of the first opening is greater than the opening width of the second opening.

2. The metal gate filling method according to claim 1, characterized in that: A substrate structure is provided, and a gate trench is formed in the substrate structure, including: providing a substrate; forming a gate oxide layer and a polysilicon gate layer in sequence on the surface of the substrate; Etching the polysilicon gate layer to form a plurality of spaced polysilicon gate structures on the surface of the gate oxide layer; forming a spacer layer on the sidewall of the polysilicon gate structure and the surface of the exposed gate oxide layer; Depositing an oxide layer in the space between adjacent sidewall layers, so that the oxide layer is flush with the sidewall layer and the polysilicon gate structure; The polysilicon gate structure is removed to form a gate trench.

3. The metal gate filling method according to any one of claims 1 to 2, characterized in that: After the step of removing the remaining sacrificial layer in the gate trench by etching to form a second opening at the position where the remaining sacrificial layer is removed, the method further includes: Depositing a second material layer in the gate trench so that the second material layer covers the sidewalls of the first opening and the second opening at the same time; A third material layer is deposited on the surface of the second material layer.

4. The metal gate filling method according to claim 3, characterized in that: After depositing a third material layer on the surface of the second material layer, the method further comprises: A metal seed layer is deposited on the surface of the third material layer.

5. The metal gate filling method according to claim 4, characterized in that: After depositing a metal seed layer on the surface of the third material layer, the method further comprises: A metal electrode layer is deposited on the surface of the metal seed layer so that the metal electrode layer completely fills the gate trench.

6. The metal gate filling method according to any one of claims 1 to 2, characterized in that: The sacrificial layer is a bottom anti-reflection layer or a carbon coating. Preferably, in the step of filling the gate trench with the sacrificial layer, the thickness of the sacrificial layer is 7. The metal gate filling method according to any one of claims 1 to 2, characterized in that: The step of etching and removing a portion of the sacrificial layer in the gate trench comprises: A partial thickness of the sacrificial layer in the gate trench is etched away by dry etching. Preferably, the partial thickness accounts for at least 1 / 30 of the entire sacrificial layer thickness and at most 1 / 8 of the entire sacrificial layer thickness.

8. The metal gate filling method according to any one of claims 1 to 2, characterized in that: The step of sequentially etching and removing the exposed first material layer and the exposed high dielectric constant layer based on the exposed position of the first material layer includes: The exposed portion of the first material layer and the exposed high dielectric constant layer are etched away by wet etching.

9. The metal gate filling method according to any one of claims 1 to 2, characterized in that: The step of removing the remaining sacrificial layer in the gate trench includes: The remaining sacrificial layer in the gate trench is removed by an ashing process.

10. The metal gate filling method according to claim 9, characterized in that: The step of removing the remaining sacrificial layer in the gate trench by an ashing process further includes: Ozone is introduced to remove pollutants generated in the process of removing the sacrificial layer by an ashing process.

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