High-speed clock and data recovery circuit supporting dual-mode input

Abstract

The invention provides a high-speed clock and data recovery circuit supporting dual-mode input. The high-speed clock and data recovery circuit comprises a linear phase discriminator, a voltage / current converter, a loop filter, an LC voltage-controlled oscillator, an injection locking type multi-phase clock generation circuit, a data recovery circuit and a logic decision circuit. The linear phase discriminator can carry out direct phase discrimination on NRZ and PAM4 data, high gain and linearity are realized by matching with the logic decision circuit, and the loop bandwidth is increased; according to the injection locking type multiphase clock generation circuit, good locking stability and low noise performance of an LC voltage-controlled oscillator are achieved, and mutual deterioration of jitter tolerance and recovery clock jitter phase noise caused by a traditional architecture is eliminated. According to the invention, high jitter tolerance and good clock phase noise recovery performance can be realized at the same time, the bit energy consumption is relatively low, and dual-mode input is supported.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit design, and specifically discloses a high-speed clock and data recovery circuit supporting dual-mode input. Background Art

[0002] Although the continuous evolution of CMOS technology has significantly reduced the feature size, Rent's law points out that as the integration of transistors surges, the demand for I / O pins must also increase accordingly to meet the growing demand for communication bandwidth and multimedia content. In particular, the expansion of global Internet users has led to a doubling of the total I / O bandwidth every two years, while chips operating at high frequencies also require more power / ground pins to suppress switching noise. Limited by packaging costs and pin counts, I / O growth lags far behind the integration speed of transistors, forcing a single I / O interface to bear higher bandwidth, posing a challenge to chip, board-level and system interconnection. Therefore, parallel interfaces are gradually replaced by Serdes-based serial interface technology due to high cost, high interference, and significant power consumption. Serdes, with its many advantages such as low pin count, small area, and high speed, has become an indispensable standard interface for high-performance CPUs, DSPs, and communication chips.

[0003] However, due to channel loss and power consumption limitations, most transmitters in Serdes circuits only send data but not clocks. High-speed clock and data recovery circuits (CDR) have become an indispensable part of Serdes, and the performance of CDR is directly related to the overall performance of the Serdes system. In existing designs, a Bang-Bang phase detector is used to achieve high gain, but this will cause the oscillator control voltage to have large jitter, resulting in large spurious signals in the recovered clock, which will lead to deterioration of noise performance. At the same time, due to the poor phase noise of the loop oscillator itself, the loop bandwidth may be further deteriorated. Therefore, the CDR circuit currently used in high-speed Serdes is limited by the compromise between input data type and rate, jitter tolerance, recovered clock root mean square jitter, and power efficiency, making it difficult to obtain a high-performance high-speed CDR circuit. How to compromise various key indicators to design a high-speed CDR circuit and method is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The object of the present invention is to provide a high-speed clock and data recovery circuit supporting dual-mode input to solve the defects of the above-mentioned existing clock and data recovery circuits used in high-speed SerDes that are limited by the compromise of input data type and rate, jitter tolerance, recovered clock root mean square jitter and power consumption efficiency.

[0005] The present invention is achieved through the following technical solutions: The present invention provides a high-speed clock and data recovery circuit supporting dual-mode input, comprising: a linear phase detector, a voltage / current converter, a loop filter, an LC voltage-controlled oscillator, an injection-locked multi-phase clock generation circuit, a data recovery circuit and a logic decision circuit; A first input terminal of the linear phase detector is connected to high-speed input data, a second input terminal of the linear phase detector is connected to an output terminal of an injection-locked multi-phase clock generating circuit, an output terminal of the linear phase detector is connected to a first input terminal of a voltage / current converter, a second input terminal of the voltage / current converter is connected to an output terminal of a logic decision circuit, an output terminal of the voltage / current converter is connected to an input terminal of a loop filter, an output terminal of the loop filter is connected to an input terminal of an LC voltage-controlled oscillator, an output terminal of the LC voltage-controlled oscillator is connected to an input terminal of an injection-locked multi-phase clock generating circuit, an output terminal of the injection-locked multi-phase clock generating circuit is connected to a second input terminal of a data recovery circuit and a first input terminal of a logic decision circuit, a first input terminal of the data recovery circuit is connected to high-speed input data, and an output terminal of the data recovery circuit is connected to a second input terminal of the logic decision circuit.

[0006] Preferably, the loop filter comprises: a resistor R L , capacitor C L1 and capacitor C L2 ; Resistance R L The input terminal of the voltage / current converter and the output terminal of the capacitor C L2 The input terminal is connected; capacitor C L1 The input terminal and the resistor R L The output end is connected; capacitor C L1 The output end of the capacitor is connected to the ground level; L2 The output end of the capacitor is connected to the ground level; L2 The input end of is connected to the input end of the LC voltage controlled oscillator.

[0007] Preferably, the injection-locked multi-phase clock generation circuit comprises: a voltage-controlled delay line, a voltage-controlled ring oscillator, first to sixteenth injection buffers, a frequency detector, a phase detector, a resistor R, a capacitor C 1 , charge pump and capacitor C 2 ; The voltage-controlled delay line includes first to eighth delay units, and the voltage-controlled ring oscillator includes first to eighth delay units; The differential input end of the first delay unit of the voltage-controlled delay line is connected to the output end of the LC voltage-controlled oscillator; the first to eighth delay units of the voltage-controlled delay line are arranged in sequence, the positive output end of the previous delay unit is connected to the negative input end of the next delay unit, and the negative output end of the previous delay unit is connected to the positive input end of the next delay unit; the first to eighth delay units of the voltage-controlled ring oscillator are arranged in sequence, the positive output end of the previous delay unit is connected to the negative input end of the next delay unit, and the negative output end of the previous delay unit is connected to the positive input end of the next delay unit; the first to eighth delay units of the voltage-controlled delay line correspond to the first to eighth delay units of the voltage-controlled ring oscillator one by one, the positive output end of each delay unit of the voltage-controlled delay line is connected to the positive output end of the corresponding delay unit in the voltage-controlled ring oscillator through an injection buffer, and the negative output end of each delay unit of the voltage-controlled delay line is connected to the negative output end of the corresponding delay unit in the voltage-controlled ring oscillator through an injection buffer; the positive output end CK of the fourth delay unit of the voltage-controlled delay line r3 Connected to the first input terminal of the frequency detector, the reverse output terminal CK r11 Connected to the second input terminal of the frequency detector and the phase detector; the positive output terminal CK of the eighth delay unit of the voltage-controlled delay line r15 Connected to the third input terminal of the frequency detector, the reverse output terminal CK r7 The output end of the phase frequency detector is connected to the input end of the resistor R; the output end of the resistor R is connected to the capacitor C 1 The input end of the capacitor C is connected to the input end of the charge pump; 1 The output end of the charge pump is connected to the ground level; the output end of the charge pump V COSC With capacitor C 2 The input end of the voltage controlled delay line and the voltage controlled input end of the voltage controlled ring oscillator are connected; the capacitor C 2 The output terminal is connected to the ground level.

[0008] Preferably, the data recovery circuit includes: a sampling and holding circuit, a resistor R 1 , resistor R 2 , resistor R 3 , resistor R 4 , resistor R 5 , resistor R 6 , first comparator, second comparator, third comparator, first D flip-flop DFF 1 , the second D flip-flop DFF 2 , the third D flip-flop DFF 3 , the fourth D flip-flop DFF 4 , the fifth D flip-flop DFF 5 , XNOR gate and AND gate; The first input terminal of the sampling and holding circuit is connected to the high-speed input data; the second input terminal of the sampling and holding circuit is connected to the output terminal CK of the injection-locked multi-phase clock generating circuit. 2n The output end of the sampling and holding circuit is connected to the first input end of the first comparator, the first input end of the second comparator and the first input end of the third comparator; the resistor R 1 The input terminal is connected to the ground level; the resistor R 1 The output terminal V RefL With resistor R 2 The input terminal of the resistor R is connected to the second input terminal of the third comparator; 2 The output terminal and the resistor R 3 The input terminal is connected; the resistor R 3 The output terminal V RefM With resistor R 4 The input terminal of the resistor R is connected to the second input terminal of the second comparator; 4 The output terminal and the resistor R 5 The input terminal is connected; the resistor R 5 The output terminal V RefH With resistor R 6 The input terminal of the first comparator is connected to the second input terminal of the first comparator; the resistor R 6 The output terminal and the input reference voltage V Ref The third input terminal of the first comparator, the third input terminal of the second comparator and the third input terminal of the third comparator are connected to the output terminal CK of the injection locked multi-phase clock generating circuit 2n+1 The output terminal of the first comparator is connected to the first D flip-flop DFF 1 The output terminal of the second comparator is connected to the second D flip-flop DFF 2 The output terminal of the third comparator is connected to the third D flip-flop DFF 3 The first input terminal of the first D flip-flop DFF is connected; 1 The output terminal T H Connected to the first input terminal of the XOR gate; the second D flip-flop DFF 2 The output terminal T M The second input terminal of the XOR gate and the fourth D flip-flop DFF 4 The output end of the XOR gate is connected to the first input end of the AND gate; the third D flip-flop DFF 3 The output terminal T L The output terminal of the AND gate is connected to the second input terminal of the AND gate; the output terminal of the AND gate is connected to the fifth D flip-flop DFF 5 The input end of the first D flip-flop DFF is connected; 1 The second input terminal of the second D flip-flop DFF2 The second input terminal of the third D flip-flop DFF 3 The second input terminal is connected to the output terminal CK of the injection locked multi-phase clock generating circuit 2n+4 Connected; the fourth D flip-flop DFF 4 The second input terminal of the fifth D flip-flop DFF 5 The second input terminal is connected to the output terminal CK of the injection locked multi-phase clock generating circuit 3 are connected.

[0009] Furthermore, the logic decision circuit includes: a fourth comparator, a first XOR gate 1 , the second XOR gate 2 , the third XOR gate 3 , the sixth D flip-flop DFF 6 , the seventh D flip-flop DFF 7 , the eighth D flip-flop DFF 8 、Ninth D flip-flop DFF 9 , the first XOR gate 1 , the second XOR gate 2 , the third XOR gate 3 , the first NAND gate 1 , the second NAND gate 2 , the first NOR gate 1 and the second NOR gate 2 ; The input end of the fourth comparator is connected to the output end of the sampling and holding circuit in the data recovery circuit; the output end of the fourth comparator is connected to the sixth D flip-flop DFF 6 The first input terminal of the first XOR gate is connected; 1 The input terminal of the second XOR gate 2 The input terminal and the third XOR gate XOR 3 The input end of the data recovery circuit is connected to the output end T H , T M , T L Connected; first XOR gate XOR 1 The output terminal of the first NAND gate 1 The first input terminal of the first NOR gate 1 The first input terminal and the second NAND gate 2 The first input terminal of the second XOR gate is connected; 2 The output of the first NAND gate 1 The second input terminal of the first NOR gate 1 The second input terminal and the second NAND gate 2The second input terminal of the third XOR gate is connected; 3 The output end of the NOT gate is connected to the input end of the NOT gate; the output end of the NOT gate is connected to the first NAND gate NAND 1 The third input terminal and the second NOR gate NOR 2 The second input terminal of the first NAND gate is connected; 1 The output terminal of the seventh D flip-flop DFF 7 The first input terminal is connected to the second NOR gate 2 The output terminal of the eighth D flip-flop DFF 8 The first input terminal is connected to the second NAND gate NAND 2 The output terminal of the ninth D flip-flop DFF 9 The first input terminal of the seventh D flip-flop DFF is connected; 7 The second input terminal of the eighth D flip-flop DFF 8 The second input terminal and the ninth D flip-flop DFF 9 The second input terminals of are connected to the output terminals of the injection locked multi-phase clock generating circuit; The sixth D flip-flop DFF 6 The first output terminal and the second output terminal are respectively used as the output terminals V of the logic decision circuit CP and output terminal V CN ; The seventh D flip-flop DFF 7 The first output terminal and the second output terminal are respectively used as the output terminals V of the logic decision circuit CP1P 、V CP1N ; The eighth D flip-flop DFF 8 The first output terminal and the second output terminal are respectively used as the output terminals V of the logic decision circuit CP2P and V CP2N ; The ninth D flip-flop DFF 9 The first output terminal and the second output terminal are respectively used as the output terminals V of the logic decision circuit CP3P and V CP3N .

[0010] Furthermore, the voltage / current converter includes a polarity conversion switch, a voltage / current conversion unit and an output control circuit, wherein the output end of the polarity conversion switch is connected to the input end of the voltage / current conversion unit, and the output end of the voltage / current conversion unit is connected to the input end of the output control circuit; the input end of the polarity conversion switch is connected to the output end V of the logic decision circuit. CP 、V CN connected; the input end of the output control circuit and the output end V of the logic decision circuit CP1P 、V CP2P 、V CP3P 、V CP1N 、V CP2N 、VCP3N are connected.

[0011] Furthermore, the polarity conversion switch includes a first switch S 1 , the second switch S 2 , the third switch S 3 , the fourth switch S 4 ; The voltage / current conversion unit includes a first voltage / current conversion unit, a second voltage / current conversion unit, and a third voltage / current conversion unit; The output control circuit includes a first transmission gate TG 1 , the second transmission gate TG 2 , the third transmission gate TG 3 ; The first switch S 1 The first input terminal V P The positive output of the linear phase detector and the second switch S 2 The third switch S 3 The first input terminal V N The inverting output terminal of the linear phase detector and the fourth switch S 4 The first input terminal is connected to the first switch S 1 The second input terminal and the third switch S 3 The second input terminal and the output terminal V CP connected; the second switch S 2 The second input terminal and the fourth switch S 4 The second input terminal is connected to the output terminal V CN Connected; first switch S 1 The output terminal of the fourth switch S 4 The output terminal of the first voltage / current conversion unit, the inverting input terminal of the second voltage / current conversion unit and the inverting input terminal of the third voltage / current conversion unit are connected; the second switch S 2 The output terminal of the third switch S 3 The output end of the first voltage / current conversion unit is connected to the positive phase input end of the first voltage / current conversion unit, the positive phase input end of the second voltage / current conversion unit and the positive phase input end of the third voltage / current conversion unit; the output end of the first voltage / current conversion unit is connected to the first transmission gate TG 1 The output end of the second voltage / current conversion unit is connected to the second transmission gate TG 2 The output end of the third voltage / current conversion unit is connected to the third transmission gate TG 3 The first input terminal of the first transmission gate TG is connected; 1 The positive control input terminal of the second transmission gate TG 2 The positive control input terminal and the third transmission gate TG 3The positive control input terminal of the logic decision circuit is connected to the output terminal V CP1P 、V CP2P and V CP3P connected; first transmission gate TG 1 The reverse control input terminal of the second transmission gate TG 2 The reverse control input terminal and the third transmission gate TG 3 The reverse control input terminal is connected to the output terminal V CP1N 、V CP2N and V CP3N connected; first transmission gate TG 1 The output terminal of the second transmission gate TG 2 The output terminal and the third transmission gate TG 3 connected to the output terminal.

[0012] Preferably, the high-speed input data is NRZ data or PAM4 data.

[0013] Preferably, the linear phase detector is formed by 8 identical linear phase detector slice units connected in parallel, the input ends of the 8 linear phase detector slice units are connected in series to receive the same high-speed input data, and the outputs of the 8 linear phase detector slice units are used to control the voltage / current converter in parallel.

[0014] Preferably, the voltage / current converter is composed of 8 identical voltage / current converter slice units connected in parallel, and the outputs of the 8 voltage / current converter slice units are connected in series to control the loop filter and the LC voltage-controlled oscillator; the data recovery circuit is composed of 8 identical data recovery circuit slice units connected in parallel, and the parallel outputs of the 8 data recovery circuit slice units are used to control the logic decision circuit; the logic decision circuit is composed of 8 identical logic decision circuit slice units connected in parallel, and the outputs of the 8 logic decision circuit slice units control the voltage / current converter.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The high-speed clock and data recovery circuit supporting dual-mode input of the present invention adopts a linear phase detector, which can directly detect the phase of NRZ and PAM4 data, and achieves high gain and linearity in combination with a logic decision circuit, thereby increasing the loop bandwidth. The present invention adopts the injection-locked multi-phase clock generation circuit to achieve better locking stability and low noise performance of the LC voltage-controlled oscillator, eliminating the mutual deterioration of jitter tolerance and recovered clock jitter phase noise caused by the traditional architecture. The present invention can simultaneously achieve high jitter tolerance and good recovered clock phase noise performance, has lower bit energy consumption, and supports dual-mode input.

[0016] Furthermore, the present invention adopts a multi-phase clock sampling and slicing method to achieve the operation of the entire circuit at a 1 / 16 baud rate frequency, thereby reducing the delay requirements for manufacturing process devices and the complexity of circuit design, while reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic diagram of the structure of a high-speed clock and data recovery circuit supporting dual-mode input according to an embodiment of the present invention; Figure 2 A schematic diagram of the structure of an injection-locked multi-phase clock generating circuit according to an embodiment of the present invention; Figure 3 is a structural schematic diagram of a data recovery circuit according to an embodiment of the present invention; Figure 4 Schematic diagram of the structure of a logic decision circuit according to an embodiment of the present invention; Figure 5 FIG. 4 is a schematic diagram of a circuit structure of a voltage / current converter according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0020] It should be noted that the process equipment or devices not specifically specified in the following embodiments are all conventional equipment or devices in the art.

[0021] It should be noted that the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. Moreover, unless otherwise specified, the numbering of each method step is only a convenient tool for identifying each method step, and is not intended to limit the order of arrangement of each method step or to define the scope of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the present invention without substantially changing the technical content.

[0022] In addition, it should be noted that the terms "first", "second", etc. of the present invention are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. The orientation or position relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention; in addition, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements.

[0023] refer to Figure 1 The high-speed clock and data recovery circuit supporting dual-mode input of the present invention includes: a linear phase detector, a voltage / current converter, a loop filter, an LC voltage-controlled oscillator (VOC), an injection-locked multi-phase clock generation circuit, a data recovery circuit and a logic decision circuit.

[0024] Wherein, the first input end of the linear phase detector is connected to the high-speed input data, the second input end of the linear phase detector is connected to the output end of the injection-locked multi-phase clock generating circuit, the output end of the linear phase detector is connected to the first input end of the voltage / current converter, the second input end of the voltage / current converter is connected to the output end of the logic decision circuit, the output end of the voltage / current converter is connected to the input end of the loop filter, the output end of the loop filter is connected to the input end of the LC voltage-controlled oscillator, the output end of the LC voltage-controlled oscillator is connected to the input end of the injection-locked multi-phase clock generating circuit, the output end of the injection-locked multi-phase clock generating circuit is connected to the second input end of the data recovery circuit and the first input end of the logic decision circuit, the first input end of the data recovery circuit is connected to the high-speed input data, and the output end of the data recovery circuit is connected to the second input end of the logic decision circuit.

[0025] In one embodiment of the present invention, the loop filter comprises: a resistor R L , capacitor C L1 , capacitor C L2 ; Wherein, the resistor R L The input terminal of the voltage / current converter and the output terminal of the capacitor C L2 The input end is connected; the capacitor C L1 The input terminal and the resistor R L The output end is connected; the capacitor C L1 The output end is connected to the ground level; the capacitor C L2 The output end is connected to the ground level; the capacitor C L2 The input end of is connected to the input end of the LC voltage-controlled oscillator.

[0026] The linear phase detector of the present invention can directly perform linear phase detection on the input high-speed NRZ (non-return-to-zero code) and PAM4 (four-level pulse amplitude modulation signal), and has a large phase detection gain. The closed-loop transfer function of the Type-Ⅱ loop structure adopted by the present invention is calculated as follows:

[0027] in, K PD is the gain of the linear phase detector, I CP is the charge pump current, K VCO is the gain of the LC voltage-controlled oscillator, R L is the resistance in the loop filter,C L1 is the first-order filter capacitor in the loop filter, C L2 It is the second-order filter capacitor in the loop filter.

[0028] Furthermore, the loop bandwidth is calculated as follows:

[0029] It should be noted that increasing the linear phase detector gain can not only increase the closed-loop bandwidth, but also reduce the in-band noise of the charge pump and the LC voltage-controlled oscillator.

[0030] refer to Figure 2 In one embodiment of the present invention, the injection-locked multi-phase clock generation circuit includes: a voltage-controlled delay line, a voltage-controlled ring oscillator, a phase frequency detector PFD, a resistor R, a capacitor C 1 , charge pump CP and capacitor C 2 The voltage-controlled delay line input is a complementary clock generated by a low-frequency LC voltage-controlled oscillator in the loop, and outputs a 16-phase clock with the same frequency. Since the injection intensity generated by the multi-phase clock injection technology is very large, the requirement for phase accuracy is relatively low. The multi-phase injection technology can simultaneously generate a high-precision and low-noise multi-phase clock. The phase frequency detector PFD performs phase detection on the orthogonal injection clock, and the output high-frequency phase detection result is filtered to a low frequency and then sent to the charge pump to achieve phase and frequency alignment.

[0031] It should be noted that the bandwidth of the injection-locked multi-phase clock generating circuit is very large, and the noise of the generated multi-phase clock is mainly the noise of the input reference clock, and it is very easy to realize a low-noise low-frequency LC voltage-controlled oscillator. At the same time, since a linear phase detector is used, the output clock has lower spuriousness, which can generate stronger injection-locking strength and realize a high-precision, low-noise multi-phase clock.

[0032] Specifically, the injection-locked multi-phase clock generating circuit includes: a first delay unit of a voltage-controlled delay line, a second delay unit of the voltage-controlled delay line, a third delay unit of the voltage-controlled delay line, a fourth delay unit of the voltage-controlled delay line, a fifth delay unit of the voltage-controlled delay line, a sixth delay unit of the voltage-controlled delay line, a seventh delay unit of the voltage-controlled delay line, an eighth delay unit of the voltage-controlled delay line, a first injection buffer, a second injection buffer, a third injection buffer, a fourth injection buffer, a fifth injection buffer, a sixth injection buffer, a seventh injection buffer, an eighth injection buffer, a ninth injection buffer, a tenth injection buffer, an eleventh injection buffer, a twelfth injection buffer, a thirteenth injection buffer, a fourteenth injection buffer, a fifteenth injection buffer, a sixteenth injection buffer, a first delay unit of a voltage-controlled ring oscillator, a second delay unit of the voltage-controlled ring oscillator, a third delay unit of the voltage-controlled ring oscillator, a fourth delay unit of the voltage-controlled ring oscillator, a fifth delay unit of the voltage-controlled ring oscillator, a sixth delay unit of the voltage-controlled ring oscillator, a seventh delay unit of the voltage-controlled ring oscillator, an eighth delay unit of the voltage-controlled ring oscillator, a phase frequency detector PFD, a resistor R, and a capacitor C 1 , charge pump CP and capacitor C 2 .

[0033] The differential input end of the first delay unit of the voltage-controlled delay line is connected to the output end of the LC voltage-controlled oscillator; the positive output end CK of the first delay unit of the voltage-controlled delay line is connected to the output end of the LC voltage-controlled oscillator; r8 The reverse input terminal CK of the second delay unit of the voltage-controlled delay line and the input terminal of the first injection buffer are connected; the reverse output terminal CK of the first delay unit of the voltage-controlled delay line r0 The positive input terminal of the second delay unit of the voltage-controlled delay line and the input terminal of the second injection buffer are connected; the positive output terminal CK of the second delay unit of the voltage-controlled delay line r1 The reverse input terminal CK of the third delay unit of the voltage-controlled delay line and the input terminal of the third injection buffer are connected; the reverse output terminal CK of the second delay unit of the voltage-controlled delay line r9 The positive input terminal of the third delay unit of the voltage-controlled delay line and the input terminal of the fourth injection buffer are connected; the positive output terminal CK of the third delay unit of the voltage-controlled delay line r10 The reverse input terminal CK of the fourth delay unit of the voltage-controlled delay line and the input terminal of the fifth injection buffer are connected; the reverse output terminal CK of the third delay unit of the voltage-controlled delay line r2 The positive input terminal of the fourth delay unit of the voltage-controlled delay line and the input terminal of the sixth injection buffer are connected; the positive output terminal CK of the fourth delay unit of the voltage-controlled delay line r3The reverse input terminal CK of the fifth delay unit of the voltage-controlled delay line and the input terminal of the seventh injection buffer are connected; the reverse output terminal CK of the fourth delay unit of the voltage-controlled delay line r11 The positive input terminal of the fifth delay unit of the voltage-controlled delay line and the input terminal of the eighth injection buffer are connected; the positive output terminal CK of the fourth delay unit of the voltage-controlled delay line r3 The reverse input terminal CK of the fifth delay unit of the voltage-controlled delay line, the input terminal of the seventh injection buffer and the first input terminal of the frequency detector and phase detector are connected; the reverse output terminal CK of the fourth delay unit of the voltage-controlled delay line r11 The positive input terminal of the fifth delay unit of the voltage-controlled delay line, the input terminal of the eighth injection buffer and the second input terminal of the frequency detector and phase detector are connected; the positive output terminal CK of the fifth delay unit of the voltage-controlled delay line r12 The reverse input terminal CK of the sixth delay unit of the voltage-controlled delay line and the input terminal of the ninth injection buffer are connected; the reverse output terminal CK of the fifth delay unit of the voltage-controlled delay line r4 The positive input terminal of the sixth delay unit of the voltage-controlled delay line and the input terminal of the tenth injection buffer are connected; the positive output terminal CK of the sixth delay unit of the voltage-controlled delay line r5 The reverse input terminal CK of the seventh delay unit of the voltage-controlled delay line and the input terminal of the eleventh injection buffer are connected; the reverse output terminal CK of the sixth delay unit of the voltage-controlled delay line r13 The positive input terminal of the seventh delay unit of the voltage-controlled delay line and the input terminal of the twelfth injection buffer are connected; the positive output terminal CK of the seventh delay unit of the voltage-controlled delay line r14 The reverse input terminal CK of the eighth delay unit of the voltage-controlled delay line and the input terminal of the thirteenth injection buffer are connected; the reverse output terminal CK of the seventh delay unit of the voltage-controlled delay line r6 The positive input terminal of the eighth delay unit of the voltage-controlled delay line and the input terminal of the fourteenth injection buffer are connected; the positive output terminal CK of the eighth delay unit of the voltage-controlled delay line r15 connected to the input terminal of the fifteenth injection buffer and the third input terminal of the frequency detector and the phase detector; the reverse output terminal CK of the eighth delay unit of the voltage-controlled delay line r7 The output end of the first injection buffer is connected to the positive output end CK of the first delay unit of the voltage-controlled ring oscillator. 8The output end of the second injection buffer is connected to the reverse output end CK of the first delay unit of the voltage-controlled ring oscillator. 0 The output end of the third injection buffer is connected to the positive output end CK of the second delay unit of the voltage-controlled ring oscillator. 1 The output end of the fourth injection buffer is connected to the reverse output end CK of the second delay unit of the voltage-controlled ring oscillator. 9 The output end of the fifth injection buffer is connected to the positive output end CK of the third delay unit of the voltage-controlled ring oscillator. 10 The output end of the sixth injection buffer is connected to the reverse output end CK of the third delay unit of the voltage-controlled ring oscillator. 2 The output end of the seventh injection buffer is connected to the positive output end CK of the fourth delay unit of the voltage-controlled ring oscillator. 3 The output end of the eighth injection buffer is connected to the reverse output end CK of the fourth delay unit of the voltage-controlled ring oscillator. 11 The output end of the ninth injection buffer is connected to the positive output end CK of the fifth delay unit of the voltage-controlled ring oscillator. 12 The output end of the tenth injection buffer is connected to the reverse output end CK of the fifth delay unit of the voltage-controlled ring oscillator. 4 The output end of the eleventh injection buffer is connected to the positive output end CK of the sixth delay unit of the voltage-controlled ring oscillator. 5 The output end of the twelfth injection buffer is connected to the reverse output end CK of the sixth delay unit of the voltage-controlled ring oscillator. 13 The output end of the thirteenth injection buffer is connected to the positive output end CK of the seventh delay unit of the voltage-controlled ring oscillator. 14The output end of the fourteenth injection buffer is connected to the reverse output end CK of the seventh delay unit of the voltage-controlled ring oscillator. 6 The output end of the fifteenth injection buffer is connected to the positive output end CK of the eighth delay unit of the voltage-controlled ring oscillator. 7 The output end of the sixteenth injection buffer is connected to the reverse output end CK of the eighth delay unit of the voltage-controlled ring oscillator. 15 The output end of the phase detector is connected to the input end of the resistor R; the output end of the resistor R is connected to the capacitor C 1 The input end of the capacitor C is connected to the input end of the charge pump; 1 The output end of the charge pump is connected to the ground level; the output end V COSC With the capacitor C 2 The input end of the voltage controlled delay line and the voltage controlled input end of the voltage controlled ring oscillator are connected; the capacitor C 2 The output terminal is connected to the ground level.

[0034] refer to Figure 3 In one embodiment of the present invention, the data recovery circuit includes a comparator, a D flip-flop and a logic circuit. For NRZ data, the reference voltage is directly used as the intermediate reference voltage V RefM The comparator and the D flip-flop can get the restored low-frequency data. For PAM4 data, three reference voltages are required, namely, high reference voltage V RefH , intermediate reference voltage V RefM , low reference voltage V RefL The comparator then passes through three D flip-flops to generate a three-bit thermometer code T H , T M , T L Specifically, for the four level signals of input PAM4 data -3, -1, +1, +3, a three-bit thermometer code T is generated. H , T M , T L They are 000, 001, 011 and 111 respectively.

[0035] The logic circuit implements the following logical operation:

[0036] When the three-digit thermometer code T H , TM , T L When the two bits are 000, 001, 011, and 111 respectively, the two bits of binary code generated by the logic circuit are 00, 01, 10, and 11 respectively. The two bits of binary code are then retimed to generate recovered low-frequency parallel data.

[0037] Specifically, the data recovery circuit includes: a sampling and holding circuit, a resistor R 1 , resistor R 2 , resistor R 3 , resistor R 4 , resistor R 5 , resistor R 6 , first comparator, second comparator, third comparator, first D flip-flop DFF 1 , the second D flip-flop DFF 2 , the third D flip-flop DFF 3 , the fourth D flip-flop DFF 4 , the fifth D flip-flop DFF 5 , XNOR gate and AND gate.

[0038] The first input terminal of the sampling and holding circuit is connected to the high-speed input data; the second input terminal of the sampling and holding circuit is connected to the output terminal CK of the injection-locked multi-phase clock generating circuit. 2n The output end of the sampling and holding circuit is connected to the first input end of the first comparator, the first input end of the second comparator and the first input end of the third comparator; the resistor R 1 The input terminal is connected to the ground level; the resistor R 1 The output terminal V RefL With the resistor R 2 The input terminal of the resistor R is connected to the second input terminal of the third comparator; 2 The output terminal and the resistor R 3 The input end is connected; the resistor R 3 The output terminal V RefM With the resistor R 4 The input terminal of the resistor R is connected to the second input terminal of the second comparator; 4 The output terminal and the resistor R 5 The input end is connected; the resistor R 5 The output terminal V RefH With the resistor R 6 The input terminal of the resistor R is connected to the second input terminal of the first comparator; 6 The output terminal and the input reference voltage V RefThe third input terminal of the first comparator, the third input terminal of the second comparator and the third input terminal of the third comparator are connected to the output terminal CK of the injection locked multi-phase clock generating circuit 2n+1 The output terminal of the first comparator is connected to the first D flip-flop DFF 1 The output end of the second comparator is connected to the second D flip-flop DFF 2 The output end of the third comparator is connected to the third D flip-flop DFF 3 The first D flip-flop DFF 1 The output terminal T H connected to the first input terminal of the XOR gate; the second D flip-flop DFF 2 The output terminal T M The second input terminal of the XOR gate and the fourth D flip-flop DFF 4 The output end of the XOR gate is connected to the first input end of the AND gate; the third D flip-flop DFF 3 The output terminal T L connected to the second input terminal of the AND gate; the output terminal of the AND gate is connected to the AND fifth D flip-flop DFF 5 The input end is connected; the first D flip-flop DFF 1 The second input terminal of the second D flip-flop DFF 2 The second input terminal of the third D flip-flop DFF 3 The second input terminal is connected to the output terminal CK of the injection locked multi-phase clock generating circuit. 2n+4 connected; the fourth D flip-flop DFF 4 The second input terminal of the fifth D flip-flop DFF 5 The second input terminal is connected to the output terminal CK of the injection locked multi-phase clock generating circuit. 3 are connected.

[0039] refer to Figure 4 In one embodiment of the present invention, the logic decision circuit includes a comparator, a D flip-flop and a logic circuit.

[0040] It should be noted that the logic decision circuit realizes the following two functions: deciding the transition direction of the input data and deciding the transition type.

[0041] Specifically, the comparator input is the data sampling voltage V before the data transition edge. n And the data sampling voltage V after the data jump edge n+1 , the output is the judgment result V CP 、VCN The judgment result controls the input polarity of the voltage / current converter to realize logic control. The judgment jump type is realized by a logic circuit. First, the three-digit thermometer code T corresponding to the data before the data jump edge and the data after the data jump edge is calculated. H[n] , T M[n] , T L[n] and T H[n+1] , T M[n+1] , T L[n+1] The XOR operation is performed in sequence, and the XOR gate outputs to the logic circuit, which implements the following logical operation:

[0042] Furthermore, for the edge with the smallest jump type, i.e., 000→001, 001→000, 001→011, 011→001, 011→111, 111→011, the judgment results are V CP1P 、V CP2P 、V CP3P is 111; for the intermediate transition type edge, i.e. 000→011, 011→000, 001→111, 111→001, the judgment is V CP1P 、V CP2P 、V CP3P is 110 or 001; for the edge with the largest jump type, that is, 000→111, 111→000, the judgment is V CP1P 、V CP2P 、V CP3P 010. Only three-level logic circuits are used to achieve minimum delay logic control.

[0043] Specifically, the logic decision circuit includes: a fourth comparator, a first XOR gate 1 , the second XOR gate 2 , the third XOR gate 3 , the sixth D flip-flop DFF 6 , the seventh D flip-flop DFF 7 , the eighth D flip-flop DFF 8 、Ninth D flip-flop DFF 9 , the first XOR gate 1 , the second XOR gate 2 , the third XOR gate 3 , the first NAND gate 1 , the second NAND gate 2 , the first NOR gate 1 , the second NOR gate 2 .

[0044] The input end of the fourth comparator is connected to the output end of the sampling and holding circuit in the data recovery circuit; the output end of the fourth comparator is connected to the sixth D flip-flop DFF 6 The first input terminal of the first XOR gate is connected; 1 The input terminal of the second XOR gate 2 The input terminal and the third XOR gate XOR 3 The input end of the data recovery circuit is respectively connected to the output end T H , T M , T L connected; the first XOR gate XOR 1 The output terminal of the first NAND gate 1 The first input terminal of the first NOR gate 1 The first input terminal and the second NAND gate NAND 2 The first input terminal of the second XOR gate is connected; 2 The output of the first NAND gate 1 The second input terminal of the first NOR gate 1 The second input terminal and the second NAND gate NAND 2 The second input terminal of the third XOR gate is connected; 3 The output end of the NOT gate is connected to the input end of the NOT gate; the output end of the NOT gate is connected to the first NAND gate NAND 1 The third input terminal and the second NOR gate NOR 2 The second input terminal of the first NAND gate is connected; 1 The output terminal of the seventh D flip-flop DFF 7 The first input terminal is connected to the second NOR gate 2 The output terminal of the eighth D flip-flop DFF 8 The first input terminal is connected to the second NAND gate NAND 2 The output terminal of the ninth D flip-flop DFF 9 The first input terminal of the seventh D flip-flop DFF is connected; 7 The second input terminal of the eighth D flip-flop DFF 8 The second input terminal and the ninth D flip-flop DFF 9 The second input end of each is connected to the output end of the injection locked multi-phase clock generating circuit.

[0045] The sixth D flip-flop DFF 6 The first output terminal and the second output terminal are respectively used as the output terminals V of the logic decision circuit CPand output terminal V CN ; The seventh D flip-flop DFF 7 The first output terminal and the second output terminal are respectively used as the output terminals V of the logic decision circuit CP1P 、V CP1N The eighth D flip-flop DFF 8 The first output terminal and the second output terminal are respectively used as the output terminals V of the logic decision circuit CP2P and V CP2N The ninth D flip-flop DFF 9 The first output terminal and the second output terminal are respectively used as the output terminals V of the logic decision circuit CP3P and V CP3N .

[0046] join Figure 5 In one embodiment of the present invention, the voltage / current converter comprises a polarity conversion switch, a voltage / current conversion unit and an output control circuit, wherein the polarity conversion switch is controlled by a decision result V generated by a logic decision circuit. CP 、V CN When the decision result of the jump edge direction is reversed, the input polarity of the voltage / current conversion unit is also reversed.

[0047] The output control circuit is composed of the logic decision circuit V CP1P 、V CP2P 、V CP3P and V CP1N 、V CP2N 、V CP3N Control is used to achieve an output current of 1:1:1 when the input voltage difference is 1:2:3, which improves the circuit phase linearity and further improves the gain and stability.

[0048] Specifically, the polarity conversion switch includes a first switch S 1 , the second switch S 2 , the third switch S 3 , the fourth switch S 4 ; The voltage / current conversion unit includes a first voltage / current conversion unit, a second voltage / current conversion unit, and a third voltage / current conversion unit; The output control circuit includes a first transmission gate TG 1 , the second transmission gate TG 2 , the third transmission gate TG 3 .

[0049] Wherein, the first switch S 1 The first input terminal V P The positive output terminal of the linear phase detector and the second switch S 2 The first input terminal is connected to the third switch S 3The first input terminal V N The inverting output terminal of the linear phase detector and the fourth switch S 4 The first input terminal is connected to the first switch S 1 The second input terminal and the third switch S 3 The second input terminal and the output terminal V of the logic decision circuit CP The second switch S 2 The second input terminal and the fourth switch S 4 The second input terminal is connected to the output terminal V of the logic decision circuit. CN The first switch S 1 The output terminal of the fourth switch S 4 The output end of the first voltage / current conversion unit, the inverting input end of the second voltage / current conversion unit and the inverting input end of the third voltage / current conversion unit are connected; the second switch S 2 The output terminal of the third switch S 3 The output end of the first voltage / current conversion unit is connected to the positive phase input end of the first voltage / current conversion unit, the positive phase input end of the second voltage / current conversion unit and the positive phase input end of the third voltage / current conversion unit; the output end of the first voltage / current conversion unit is connected to the first transmission gate TG 1 The output end of the second voltage / current conversion unit is connected to the second transmission gate TG 2 The output end of the third voltage / current conversion unit is connected to the third transmission gate TG 3 The first input terminal of the first transmission gate TG is connected; 1 The positive control input terminal of the second transmission gate TG 2 The positive control input terminal and the third transmission gate TG 3 The positive control input terminal is respectively connected to the output terminal V CP1P 、V CP2P and V CP3P connected; the first transmission gate TG 1 The reverse control input terminal of the second transmission gate TG 2 The inverting control input terminal and the third transmission gate TG 3 The reverse control input terminal is respectively connected to the output terminal V CP1N 、V CP2N and V CP3N connected; the first transmission gate TG 1 The output terminal of the second transmission gate TG 2The output terminal and the third transmission gate TG 3 connected to the output terminal.

[0050] In one embodiment of the present invention, the linear phase detector can support high-speed input data of two data types, NRZ and PAM4, and realize a dual-mode data input function.

[0051] In one embodiment of the present invention, the linear phase detector is formed by connecting 8 identical linear phase detector slice units in parallel. In this structure, 8 input terminals are connected in series to receive the same high-speed input data, and the 8 parallel circuit outputs of the linear phase detector are used to control the voltage / current converter in parallel.

[0052] The voltage / current converter is formed by connecting 8 identical voltage / current converter slice units in parallel. In this structure, the 8 parallel outputs are connected in series to control the loop filter and the LC voltage-controlled oscillator.

[0053] In one embodiment of the present invention, the data recovery circuit is formed by connecting 8 identical data recovery circuit slice units in parallel. In this structure, the 8 parallel outputs control the logic decision circuit.

[0054] In one embodiment of the present invention, the logic decision circuit is formed by connecting 8 identical logic decision circuit slice units in parallel. The 8 parallel outputs control the voltage / current converter.

[0055] The present invention achieves high jitter tolerance through a high-gain linear phase detector. At the same time, the high linearity reduces the control voltage ripple of the LC voltage-controlled oscillator in the loop when stable, further reduces the clock peak jitter of the LC voltage-controlled oscillator when stable, and can perform multi-phase locking to generate a low-noise multi-phase clock, thereby achieving simultaneous improvement of jitter tolerance and phase noise, and achieving lower bit energy consumption while supporting dual-mode input.

[0056] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A high-speed clock and data recovery circuit supporting dual-mode input, characterized in that: include: Linear phase detector, voltage / current converter, loop filter, LC voltage-controlled oscillator, injection-locked multi-phase clock generation circuit, data recovery circuit and logic decision circuit; A first input terminal of the linear phase detector is connected to high-speed input data, a second input terminal of the linear phase detector is connected to an output terminal of an injection-locked multi-phase clock generating circuit, an output terminal of the linear phase detector is connected to a first input terminal of a voltage / current converter, a second input terminal of the voltage / current converter is connected to an output terminal of a logic decision circuit, an output terminal of the voltage / current converter is connected to an input terminal of a loop filter, an output terminal of the loop filter is connected to an input terminal of an LC voltage-controlled oscillator, an output terminal of the LC voltage-controlled oscillator is connected to an input terminal of an injection-locked multi-phase clock generating circuit, an output terminal of the injection-locked multi-phase clock generating circuit is connected to a second input terminal of a data recovery circuit and a first input terminal of a logic decision circuit, a first input terminal of the data recovery circuit is connected to high-speed input data, and an output terminal of the data recovery circuit is connected to a second input terminal of the logic decision circuit.

2. The high-speed clock and data recovery circuit supporting dual-mode input according to claim 1, characterized in that: The loop filter includes: resistor R L , capacitor C L1 and capacitor C L2 ; Resistance R L The input terminal of the voltage / current converter and the output terminal of the capacitor C L2 The input terminal is connected; capacitor C L1 The input terminal and the resistor R L The output end is connected; capacitor C L1 The output end of the capacitor is connected to the ground level; L2 The output end of the capacitor is connected to the ground level; L2 The input end of is connected to the input end of the LC voltage controlled oscillator.

3. The high-speed clock and data recovery circuit supporting dual-mode input according to claim 1, characterized in that: The injection-locked multi-phase clock generation circuit comprises: a voltage-controlled delay line, a voltage-controlled ring oscillator, first to sixteenth injection buffers, a frequency detector, a resistor R, a capacitor C1, a charge pump and a capacitor C2; the voltage-controlled delay line comprises first to eighth delay units, and the voltage-controlled ring oscillator comprises first to eighth delay units; The differential input end of the first delay unit of the voltage-controlled delay line is connected to the output end of the LC voltage-controlled oscillator; the first to eighth delay units of the voltage-controlled delay line are arranged in sequence, the positive output end of the previous delay unit is connected to the negative input end of the next delay unit, and the negative output end of the previous delay unit is connected to the positive input end of the next delay unit; the first to eighth delay units of the voltage-controlled ring oscillator are arranged in sequence, the positive output end of the previous delay unit is connected to the negative input end of the next delay unit, and the negative output end of the previous delay unit is connected to the positive input end of the next delay unit; the first to eighth delay units of the voltage-controlled delay line correspond to the first to eighth delay units of the voltage-controlled ring oscillator one by one, the positive output end of each delay unit of the voltage-controlled delay line is connected to the positive output end of the corresponding delay unit in the voltage-controlled ring oscillator through an injection buffer, and the negative output end of each delay unit of the voltage-controlled delay line is connected to the negative output end of the corresponding delay unit in the voltage-controlled ring oscillator through an injection buffer; the positive output end CK of the fourth delay unit of the voltage-controlled delay line r3 Connected to the first input terminal of the frequency detector, the reverse output terminal CK r11 Connected to the second input terminal of the frequency detector and the phase detector; the positive output terminal CK of the eighth delay unit of the voltage-controlled delay line r15 Connected to the third input terminal of the frequency detector, the reverse output terminal CK r7 The output terminal of the phase frequency detector is connected to the input terminal of the resistor R; the output terminal of the resistor R is connected to the input terminal of the capacitor C1 and the input terminal of the charge pump; the output terminal of the capacitor C1 is connected to the ground level; the output terminal of the charge pump V COSC It is connected to the input end of capacitor C2, the voltage control input end of the voltage-controlled delay line and the voltage control input end of the voltage-controlled ring oscillator; and the output end of capacitor C2 is connected to the ground level.

4. The high-speed clock and data recovery circuit supporting dual-mode input according to claim 1, characterized in that: The data recovery circuit includes: a sampling and holding circuit, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a first comparator, a second comparator, a third comparator, a first D flip-flop DFF1, a second D flip-flop DFF2, a third D flip-flop DFF3, a fourth D flip-flop DFF4, a fifth D flip-flop DFF5, an XNOR gate and an AND gate; The first input terminal of the sampling and holding circuit is connected to the high-speed input data; the second input terminal of the sampling and holding circuit is connected to the output terminal CK of the injection-locked multi-phase clock generating circuit. 2n The output end of the sampling and holding circuit is connected to the first input end of the first comparator, the first input end of the second comparator and the first input end of the third comparator; the input end of the resistor R1 is connected to the ground level; the output end V RefL The input end of the resistor R2 and the second input end of the third comparator are connected; the output end of the resistor R2 is connected to the input end of the resistor R3; the output end V RefM The input end of the resistor R4 is connected to the second input end of the second comparator; the output end of the resistor R4 is connected to the input end of the resistor R5; the output end V RefH The input terminal of the resistor R6 and the second input terminal of the first comparator are connected; the output terminal of the resistor R6 is connected to the input reference voltage V Ref The third input terminal of the first comparator, the third input terminal of the second comparator and the third input terminal of the third comparator are connected to the output terminal CK of the injection locked multi-phase clock generating circuit 2n+1 The output terminal of the first comparator is connected to the first input terminal of the first D flip-flop DFF1; the output terminal of the second comparator is connected to the first input terminal of the second D flip-flop DFF2; the output terminal of the third comparator is connected to the first input terminal of the third D flip-flop DFF3; the output terminal T of the first D flip-flop DFF1 ... T of the second comparator is connected to the first input terminal of the second D flip-flop DFF3; the output terminal T of the first D flip-flop DFF1 is connected to the first input terminal of the second D flip-flop DFF2; the output terminal T of the second comparator is connected H The output terminal T of the second D flip-flop DFF2 is connected to the first input terminal of the XOR gate; M The second input terminal of the AND gate is connected to the first input terminal of the fourth D flip-flop DFF4; the output terminal of the AND gate is connected to the first input terminal of the AND gate; the output terminal T of the third D flip-flop DFF3 is connected to the first input terminal of the AND gate; L The output end of the AND gate is connected to the input end of the fifth D flip-flop DFF5; the second input end of the first D flip-flop DFF1, the second input end of the second D flip-flop DFF2, and the second input end of the third D flip-flop DFF3 are all connected to the output end CK of the injection locked multi-phase clock generating circuit. 2n+4 a second input terminal of the fourth D flip-flop DFF4 and a second input terminal of the fifth D flip-flop DFF5 are both connected to the output terminal CK3 of the injection locked multi-phase clock generating circuit.

5. The high-speed clock and data recovery circuit supporting dual-mode input according to claim 4, characterized in that: The logic decision circuit includes: a fourth comparator, a first XOR gate XOR1, a second XOR gate XOR2, a third XOR gate XOR3, a sixth D flip-flop DFF6, a seventh D flip-flop DFF7, an eighth D flip-flop DFF8, a ninth D flip-flop DFF9, a first XOR gate XOR1, a second XOR gate XOR2, a third XOR gate XOR3, a first NAND gate NAND1, a second NAND gate NAND2, a first NOR gate NOR1 and a second NOR gate NOR2; The input end of the fourth comparator is connected to the output end of the sampling and holding circuit in the data recovery circuit; the output end of the fourth comparator is connected to the first input end of the sixth D flip-flop DFF6; the input end of the first XOR gate XOR1, the input end of the second XOR gate XOR2 and the input end of the third XOR gate XOR3 are respectively connected to the output end T H 、T M 、T L connected; the output end of the first XOR gate XOR1 is connected to the first input end of the first NAND gate NAND1, the first input end of the first NOR gate NOR1 and the first input end of the second NAND gate NAND2; the output end of the second XOR gate XOR2 is connected to the second input end of the first NAND gate NAND1, the second input end of the first NOR gate NOR1 and the second input end of the second NAND gate NAND2; the output end of the third XOR gate XOR3 is connected to the input end of the NAND gate; the output end of the NAND gate is connected to the third input end of the first NAND gate NAND1 and the second input end of the second NOR gate NOR2; the output end of the first NAND gate NAND1 is connected to the first input end of the seventh D flip-flop DFF7; the output end of the second NOR gate NOR2 is connected to the first input end of the eighth D flip-flop DFF8; the output end of the second NAND gate NAND2 is connected to the first input end of the ninth D flip-flop DFF9; the second input end of the seventh D flip-flop DFF7, the second input end of the eighth D flip-flop DFF8 and the second input end of the ninth D flip-flop DFF9 are all connected to the output end of the injection locked multi-phase clock generating circuit; The first output terminal and the second output terminal of the sixth D flip-flop DFF6 are respectively used as the output terminal V CP and output terminal V CN The first output terminal and the second output terminal of the seventh D flip-flop DFF7 are respectively used as the output terminal V of the logic decision circuit CP1P 、V CP1N The first output terminal and the second output terminal of the eighth D flip-flop DFF8 are respectively used as the output terminal V of the logic decision circuit CP2P and V CP2N The first output terminal and the second output terminal of the ninth D flip-flop DFF9 are respectively used as the output terminal V of the logic decision circuit CP3P and V CP3N .

6. The high-speed clock and data recovery circuit supporting dual-mode input according to claim 5, characterized in that: The voltage / current converter comprises a polarity conversion switch, a voltage / current conversion unit and an output control circuit. The output end of the polarity conversion switch is connected to the input end of the voltage / current conversion unit, and the output end of the voltage / current conversion unit is connected to the input end of the output control circuit. The input end of the polarity conversion switch is connected to the output end V of the logic decision circuit. CP 、V CN connected; the input end of the output control circuit and the output end V of the logic decision circuit CP1P 、V CP2P 、V CP3P 、V CP1N 、V CP2N 、V CP3N are connected.

7. The high-speed clock and data recovery circuit supporting dual-mode input according to claim 6, characterized in that: The polarity conversion switch includes a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4; the voltage / current conversion unit includes a first voltage / current conversion unit, a second voltage / current conversion unit, and a third voltage / current conversion unit; the output control circuit includes a first transmission gate TG1, a second transmission gate TG2, and a third transmission gate TG3; The first input terminal V of the first switch S1 P The positive output terminal of the linear phase detector is connected to the first input terminal of the second switch S2; the first input terminal V N The second input terminal of the first switch S1 and the second input terminal of the third switch S3 are connected to the output terminal V CP The second input terminal of the second switch S2 and the second input terminal of the fourth switch S4 are connected to the output terminal V CN The output end of the first switch S1 is connected to the output end of the fourth switch S4, the inverting input end of the first voltage / current conversion unit, the inverting input end of the second voltage / current conversion unit and the inverting input end of the third voltage / current conversion unit; the output end of the second switch S2 is connected to the output end of the third switch S3, the positive phase input end of the first voltage / current conversion unit, the positive phase input end of the second voltage / current conversion unit and the positive phase input end of the third voltage / current conversion unit; the output end of the first voltage / current conversion unit is connected to the first input end of the first transmission gate TG1; the output end of the second voltage / current conversion unit is connected to the first input end of the second transmission gate TG2; the output end of the third voltage / current conversion unit is connected to the first input end of the third transmission gate TG3; the positive control input end of the first transmission gate TG1, the positive control input end of the second transmission gate TG2 and the positive control input end of the third transmission gate TG3 are respectively connected to the output end V CP1P 、V CP2P and V CP3P The reverse control input terminal of the first transmission gate TG1, the reverse control input terminal of the second transmission gate TG2 and the reverse control input terminal of the third transmission gate TG3 are respectively connected to the output terminal V CP1N 、V CP2N and V CP3N The output end of the first transmission gate TG1 is connected to the output end of the second transmission gate TG2 and the output end of the third transmission gate TG3.

8. The high-speed clock and data recovery circuit supporting dual-mode input according to claim 1, characterized in that: The high-speed input data is NRZ data or PAM4 data.

9. The high-speed clock and data recovery circuit supporting dual-mode input according to claim 1, characterized in that: The linear phase detector is formed by connecting 8 identical linear phase detector slice units in parallel, the input ends of the 8 linear phase detector slice units are connected in series to receive the same high-speed input data, and the outputs of the 8 linear phase detector slice units are used to control the voltage / current converter in parallel.

10. The high-speed clock and data recovery circuit supporting dual-mode input according to claim 1, characterized in that: The voltage / current converter is composed of 8 identical voltage / current converter slice units connected in parallel, and the outputs of the 8 voltage / current converter slice units are connected in series to control the loop filter and the LC voltage-controlled oscillator; the data recovery circuit is composed of 8 identical data recovery circuit slice units connected in parallel, and the parallel outputs of the 8 data recovery circuit slice units are used to control the logic decision circuit; the logic decision circuit is composed of 8 identical logic decision circuit slice units connected in parallel, and the outputs of the 8 logic decision circuit slice units control the voltage / current converter.

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