Ultra-low power consumption microcontroller architecture design method and system

Abstract

The invention relates to the technical field of ultra-low power consumption microcontrollers, and discloses an ultra-low power consumption microcontroller architecture design method and system, and the method comprises the steps: constructing a heterogeneous dual-core processor comprising a high-performance core and a low-power consumption core, and dividing the heterogeneous dual-core processor into a plurality of independent power domains; constructing a sub-threshold voltage operation system on a plurality of independent power supply domains, and configuring a multi-layer storage structure in the heterogeneous dual-core processor; recording task characteristic data by using a multi-level storage structure, executing task dynamic allocation between dual cores, and creating a dynamic task allocation mechanism; and performing static analysis and function block division on the application code based on a dynamic task allocation mechanism to obtain a plurality of function code blocks, and performing storage hierarchy and processor core allocation on the plurality of function code blocks to obtain a function code allocation result. According to the method, the dynamic migration of the workload and the optimal resource allocation are realized, and the energy consumption of the microcontroller in various working scenes is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of ultra-low power consumption microcontrollers, and in particular to an ultra-low power consumption microcontroller architecture design method and system. Background Art

[0002] Most existing ultra-low power microcontroller architectures rely on a single CPU frequency and a simple sleep-wake mechanism. This design lacks flexibility when facing variable workloads and cannot achieve true energy efficiency optimization. When processing complex computing tasks, microcontrollers with a single architecture either have insufficient performance or too high power consumption; and in low-load scenarios, even in sleep mode, there is still unnecessary static power loss. This "one-size-fits-all" design approach is difficult to meet the dual requirements of performance and power consumption at the same time.

[0003] As process nodes continue to shrink, the static power consumption problem caused by leakage current is becoming increasingly serious. Traditional dynamic voltage and frequency adjustment technology has limited effect in the subthreshold voltage region, and it is difficult to balance performance and energy efficiency. Existing subthreshold design methods mainly optimize specific circuit modules, lacking system-level collaborative design and global energy efficiency considerations, resulting in greatly reduced effectiveness in practical applications. In addition, existing technologies lack effective prediction and adaptability to dynamic changes in workloads, and are unable to dynamically adjust the system's operating state according to actual computing needs, resulting in unnecessary energy waste. Summary of the invention

[0004] The present invention provides an ultra-low power consumption microcontroller architecture design method and system, which realizes dynamic migration of workloads and optimized resource allocation, thereby reducing the energy consumption of the microcontroller in various working scenarios.

[0005] In a first aspect, the present invention provides an ultra-low power consumption microcontroller architecture design method, the ultra-low power consumption microcontroller architecture design method comprising: Constructing a heterogeneous dual-core processor including a high-performance core and a low-power core, and dividing the heterogeneous dual-core processor into a plurality of independent power domains including the high-performance core, the low-power core, permanently online peripherals, on-demand peripherals, and memory; Constructing a subthreshold voltage operation system on the multiple independent power domains, and configuring a multi-level storage structure in the heterogeneous dual-core processor according to the subthreshold voltage operation system; Using the multi-level storage structure to record task characteristic data, and performing dynamic task allocation between dual cores, a dynamic task allocation mechanism is created; Based on the dynamic task allocation mechanism, the application code is statically analyzed and divided into functional blocks to obtain multiple functional code blocks, and the multiple functional code blocks are allocated to storage levels and processor cores to obtain functional code allocation results.

[0006] In a second aspect, the present invention provides an ultra-low power microcontroller architecture design system, the ultra-low power microcontroller architecture design system comprising: A building module for building a heterogeneous dual-core processor including a high-performance core and a low-power core, and dividing the heterogeneous dual-core processor into a plurality of independent power domains including the high-performance core, the low-power core, permanently online peripherals, on-demand peripherals and memory; A configuration module, configured to construct a subthreshold voltage operation system on the plurality of independent power domains, and configure a multi-level storage structure in the heterogeneous dual-core processor according to the subthreshold voltage operation system; A recording module, used to record task characteristic data using the multi-level storage structure, and to perform dynamic task allocation between the two cores, thereby creating a dynamic task allocation mechanism; The allocation module is used to perform static analysis and functional block division on the application code based on the dynamic task allocation mechanism to obtain multiple functional code blocks, and to allocate storage levels and processor cores to the multiple functional code blocks to obtain functional code allocation results.

[0007] In the technical solution provided by the present invention, a heterogeneous dual-core design is adopted to enable the system to intelligently select the most suitable processing core according to the complexity of the task, and minimize the energy consumption of task migration through a zero-overhead context switching mechanism; the refined power domain division realizes independent power state control, so that each functional module can work at the lowest necessary voltage; the subthreshold voltage operation system ensures stable operation within a low voltage range through a fully digital phase-locked loop and a timing error prediction circuit, and supports a wide range of frequency adjustment; the multi-level storage architecture optimizes storage access power consumption through ultra-low leakage SRAM, regional bit row activation main SRAM and adaptive instruction cache; hardware-assisted task characteristic analysis and event-driven task scheduling realize dynamic migration of workloads and resource optimization allocation; the closed-loop optimization design combines compile-time static analysis with runtime monitoring, and performs code reorganization and storage optimization according to task characteristics. The present invention significantly reduces the energy consumption of microcontrollers in various working scenarios, extends the operating time of battery-powered devices, and provides a more efficient energy utilization solution for IoT terminals and sensor nodes.

[0008] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0009] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A schematic diagram of an embodiment of a method for designing an ultra-low power consumption microcontroller architecture according to an embodiment of the present invention; Figure 2 A schematic diagram of an embodiment of an ultra-low power consumption microcontroller architecture design system in an embodiment of the present invention. DETAILED DESCRIPTION

[0011] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0012] The terms "including" and "having" and any variations thereof mentioned in the embodiments of the present invention are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device end including a series of steps or units is not limited to the listed steps or units, but may optionally include other steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or device ends.

[0013] To facilitate understanding of this embodiment, firstly, a method for designing an ultra-low power consumption microcontroller architecture disclosed in an embodiment of the present invention is described in detail. Figure 1 As shown, the method comprises the following steps: 101. Build a heterogeneous dual-core processor including a high-performance core and a low-power core, and divide the heterogeneous dual-core processor into multiple independent power domains including the high-performance core, the low-power core, the always-on peripherals, the on-demand peripherals and the memory; It is understandable that the execution subject of the present invention may be an ultra-low power microcontroller architecture design system, or a terminal or a server, which is not specifically limited here. The embodiment of the present invention is described by taking a server as the execution subject as an example.

[0014] Specifically, a heterogeneous dual-core processor including a high-performance core and a low-power core is constructed. In the dual-core processor, the ARM Cortex-M4 core is used as the high-performance core. The core is appropriately set to operate at a higher frequency, such as 80MHz, according to the characteristics of the task being processed, to ensure that it can process computationally intensive tasks. At the same time, in order to meet the needs of more complex computing tasks, the Cortex-M4 core is configured with a floating-point operation unit and a DSP instruction set extension, so that the core can efficiently perform floating-point operations and digital signal processing, improve its processing capabilities, and is suitable for tasks that require high computing capabilities. The ARM Cortex-M0+ core is used as a low-power core. When configured, its operating frequency should be set to a lower frequency, such as 32MHz, to optimize its static power consumption. The low-frequency configuration enables the Cortex-M0+ to maintain extremely low energy consumption when processing low-power tasks without affecting the overall efficiency and functionality of the system. The Cortex-M0+ core adopts a reduced instruction set architecture, which itself has low power consumption characteristics. Therefore, this configuration ensures energy efficiency optimization under low-load conditions and avoids unnecessary power consumption. In terms of storage architecture, the Cortex-M4 high-performance core is configured with a 16KB instruction cache and a 16KB data cache. The cache configuration helps to improve the processing speed of the Cortex-M4 core, reduce memory access latency, and improve the execution efficiency of computationally intensive tasks. The high-performance storage access architecture is designed for computationally intensive tasks and can effectively support the core to perform fast calculations. For the Cortex-M0+ low-power core, since it mainly processes low-power tasks, it does not configure a cache system, but directly accesses the low-power SRAM. A hardware semaphore register is established between the computationally intensive processing unit and the static power optimization processing unit to achieve inter-core resource synchronization. The hardware semaphore register provides atomic operation support to ensure that there will be no competition conditions or data conflicts when accessing resources between different cores, thereby realizing multi-core task processing. In order to optimize inter-core data exchange, a hardware message queue is designed between the two cores. The hardware message queue contains 64 32-bit message slots for storing data to be exchanged, and each slot independently performs data write and read operations. The controller of the message queue will provide message writing, reading and status query functions. Based on this, the data exchange between processors is triggered by the interrupt mechanism, thereby improving the efficiency and response speed of data transmission. The interrupt-driven data exchange system enables the two cores to work together efficiently and flexibly schedule between multiple tasks. The computationally intensive processing unit, static power optimization processing unit, differentiated storage access architecture, inter-core resource synchronization interlocking mechanism and inter-core interrupt data exchange system are integrated into a single chip to form a heterogeneous dual-core processor system.In order to ensure the efficient collaboration of the two cores, a shared memory area is configured and a 32KB shared memory area is set to allow data exchange between the Cortex-M4 core and the Cortex-M0+ core. In the shared memory area, the Cortex-M4 core has read and write permissions, while the Cortex-M0+ core only has read permissions. The memory access is controlled by the memory protection unit to avoid data competition and access conflicts. The power domains of the heterogeneous dual-core processor are divided. The high-performance cores, low-power cores, permanent online peripherals, on-demand peripherals, and memories in the processor are divided into multiple independent power domains to achieve more refined power management. Each power domain is switched on and off separately according to demand, thereby effectively reducing power consumption in different working modes.

[0015] The high-performance core and its floating-point unit and tightly coupled peripherals in the heterogeneous dual-core processor are physically isolated to independently manage the power state of the high-performance core and ensure that the core obtains sufficient power supply when processing high-intensity computing tasks, thereby improving its processing power. Through physical isolation, the power domain of the high-performance core is separated to avoid unnecessary power loss. At the same time, the power domain is completely shut down when the core is not in use to reduce the static power consumption of the system. The low-power core and its directly connected interface in the heterogeneous dual-core processor are physically isolated to form a low-power core power domain. Through isolation design, the power domain of the low-power core is precisely regulated according to the needs of the task. When the task load is low, it effectively saves power by reducing the operating voltage or shutting down related peripherals to maximize the energy efficiency of the system. The real-time clock, power management unit and wake-up controller are physically isolated. These modules need to be kept running all the time, so they are divided into the permanent online peripheral power domain. Since these peripherals are always active in most operations, their power domains need to remain stable and are not allowed to be shut down when the system is in sleep mode. By isolating these peripherals separately, it is ensured that they can run in the lowest power mode at any time without interfering with the power management of other parts. At the same time, peripherals used on demand, such as USB interfaces, ADCs, DACs and other high-power modules, are powered according to the specific needs of the system. Therefore, peripherals such as USB interfaces, ADCs, DACs, etc. are divided into on-demand peripheral power domains. When these peripherals are inactive, the relevant power domains are turned off or power consumption is reduced; when necessary, the power of these modules is quickly activated to ensure that the system dynamically adjusts its power consumption according to external conditions. Shared memory and program memory are physically isolated to form independent memory power domains. Independent memory power domains adjust power according to the working status of the memory, thereby avoiding unnecessary power consumption when the memory is inactive. The high-performance core power domain, low-power core power domain, permanent online peripheral power domain, on-demand peripheral power domain and memory power domain are used as multiple independent power domains, and signal conversion circuits are set between multiple independent power domains to ensure smooth transmission of signals between different voltage domains.

[0016] 102. Construct a subthreshold voltage operation system on multiple independent power domains, and configure a multi-level storage structure in a heterogeneous dual-core processor based on the subthreshold voltage operation system; Specifically, multiple delay monitors are distributed on the target timing path of the heterogeneous dual-core processor. The delay monitors monitor the changes of the system timing in real time and detect the timing errors that occur. These monitors dynamically capture the delay information in the target path and feed it back to the timing management system. Based on the data fed back by the delay monitors, a timing error prediction circuit is obtained. This circuit predicts the timing errors that occur in advance by continuously tracking the changes of the processor timing and makes corresponding adjustments. The core of the timing error prediction circuit lies in its efficient delay acquisition and data conversion capabilities. By collecting the delay data in the timing path and converting these data through the central sampling unit and the prediction controller, the minimum stable working voltage value is obtained. Based on the minimum stable working voltage value, the characteristics of the external interrupt sources of multiple independent power domains are analyzed, different events are classified, and event classification results are generated. Event classification is divided into different categories, such as low frequency and low urgency, low frequency and high urgency, high frequency and low urgency, and high frequency and high urgency. The power consumption requirements and timeliness of each type of event are different. Based on the event classification results, a workload predictor and a state transition controller are constructed. The workload predictor predicts the upcoming workload and its demand for system resources by analyzing past workload data and combining it with real-time collected system status information. Through these predicted data, the workload predictor provides decision-making basis for the state transition controller, thereby determining what voltage and frequency state the system should be in at a specific moment to meet the upcoming load demand while maintaining the lowest energy consumption. According to the recommendations of the workload predictor, the state transition controller flexibly adjusts the voltage and frequency of each power domain so as to respond in time when the system demand changes, ensuring that the system operates efficiently in low-power mode. Through the collaborative work of the workload predictor and the state transition controller, the system adaptively adjusts the working state of each power domain according to the characteristics of the external interrupt source and the dynamic changes of the workload, ensuring that the processor operates stably at subthreshold voltage, minimizing power consumption, and ensuring the response speed and processing power of the system under different task loads, forming a subthreshold voltage operation system. According to the characteristics of the subthreshold voltage operation system, a multi-level storage structure is configured in the heterogeneous dual-core processor, so as to optimize storage access according to different types of task requirements and storage access modes, and reduce unnecessary storage power consumption. In this storage structure, multiple storage levels are used, including ultra-low power permanent online SRAM, regional bit row activated main SRAM, and adaptive instruction cache. Each storage level has different power consumption characteristics and storage capabilities. The appropriate storage level is dynamically selected for data storage and reading according to task requirements.

[0017] According to the low voltage working requirements of the subthreshold voltage operation system, a multi-level storage structure is designed and configured. Through fine storage management, while ensuring the low power operation of the system, sufficient storage access performance is provided to meet the needs of different tasks. In order to adapt to the low voltage working environment under subthreshold voltage, an 8KB ultra-low leakage SRAM is configured in the system. The SRAM has independent read and write paths and a dual-end stabilization circuit to form the L0 layer storage area. This storage area is specially used to store key status data and high-priority interrupt service programs, which can ensure stable operation under extremely low voltage. At the same time, due to its low leakage characteristics, it can maintain very low energy consumption even in low power mode. The independent read and write path design ensures that the reading and writing of data will not be disturbed, thereby improving storage efficiency, and the dual-end stabilization circuit ensures that the reading and writing process of data remains stable in a low voltage environment to avoid data errors caused by voltage fluctuations. In order to meet greater storage requirements and the characteristics of dynamic power supply control, a 32KB main SRAM is configured to form the L1 layer storage area. To improve storage access efficiency, the 32KB main SRAM in the L1 storage area is divided into eight 4KB storage blocks, each equipped with an independent row decoder and bit line driver. With this division, the storage blocks are only activated when needed, thereby reducing unnecessary power consumption. When a task accesses storage, only the accessed data block is activated, not the entire 32KB storage area. The design of the row decoder and bit line driver ensures that each 4KB storage block can effectively decode the address and drive the bit line when accessed, thereby improving the efficiency of data reading and reducing power consumption. The block storage design also facilitates the system to dynamically adjust the storage access mode according to the load, so that the system can flexibly respond to different storage requirements when running at low power. The mapping address space design of the L1 storage area ensures that the storage area efficiently interacts with other storage areas and is connected to the memory power domain, thereby optimizing the power management of the memory. Based on the L1 storage area, the L2 storage area is configured. The L2 storage area enables the system to flexibly access data by mapping it to the preset address space. Through the multi-level storage structure, the collaborative work of the L0, L1, and L2 storage areas ensures that the system can achieve efficient data access under different loads. Under this architecture, the L0 layer provides fast response and low power consumption services, the L1 layer optimizes data access by block storage, and the L2 layer complements the overall storage structure to ensure that the system can cope with more data requirements and larger storage space. Based on the L0 layer storage area, L1 layer storage area, and L2 layer storage area, an intelligent DMA controller with 8 independent channels is created. Each channel automatically transfers data and supports chain transfer functions. These DMA channels perform data transfer when the memory is not active, reducing the burden on the processor and improving the overall performance of the system.The DMA controller is designed to automatically select the best burst length and address increment mode according to the data transfer mode, thereby optimizing the efficiency of data transfer and minimizing the number of memory accesses and switching overhead. Through the intelligent DMA controller, the system efficiently transfers data between multiple storage areas, ensuring that data exchange between different storage areas does not affect the low-power operation of the system. The L0, L1, and L2 storage areas and the intelligent DMA controller together form a multi-level storage structure.

[0018] 103. Use a multi-level storage structure to record task characteristic data, and perform dynamic task allocation between dual cores to create a dynamic task allocation mechanism; Specifically, the instruction type, branch behavior and memory access pattern during task execution are statistically analyzed. The analysis process relies on a hardware-assisted task characteristic analyzer, which includes an instruction counter, a memory access monitor and an energy consumption estimation unit. The instruction counter monitors the instruction flow during task execution in real time, and provides data support for the task's computational complexity evaluation by counting the number of different types of instructions such as arithmetic operations, logical operations, and branch jumps. At the same time, the memory access monitor records the read and write operations of the task on the memory during execution, including data access frequency, address distribution, and whether there is a cache hit. The energy consumption estimation unit combines the instruction type and memory access pattern, and uses the built-in energy consumption model to estimate the energy consumption difference when the task is executed on a high-performance core and a low-power core. After analysis and processing, these data form the characteristic data of the task, including the task identifier, computational complexity, memory access characteristics and energy consumption estimation results. The task characteristic data is stored in the L0 layer storage area of ​​the multi-level storage structure. The L0 layer storage area is composed of 8KB ultra-low leakage SRAM, with independent read and write paths and dual-terminal stabilization circuits, which can provide reliable storage services under low voltage conditions. This storage area is used to store key task characteristic data and high-priority interrupt service routines to ensure that the key information of the task can still be quickly accessed when the system enters low-power mode. During the data storage process, each task is assigned a unique identifier, and the task's computational complexity index, memory access characteristics, and energy consumption estimation results are stored in a structured form in the L0 layer to form a task characteristic data set. Based on the task characteristic data set, tasks are divided into computationally intensive, data-intensive, hybrid, and lightweight types. Computationally intensive tasks consist of complex arithmetic and logical operations and are suitable for assignment to high-performance cores; data-intensive tasks involve a large number of memory read and write operations and are more dependent on memory bandwidth; hybrid tasks have certain loads in both computing and data processing, and require a comprehensive consideration of energy consumption and performance balance; lightweight tasks have low resource requirements and are suitable for low-power core processing. This classification process is automatically completed by the task classification unit, and the classification results are fed back to the task allocation system to dynamically adjust the task allocation strategy. Based on the task classification results and the system status information provided by the subthreshold voltage operating system, a core selector is constructed. By analyzing the current system power status, the load of each core, and the energy consumption prediction data of the task, the core selector dynamically determines whether each task should be assigned to a high-performance core or a low-power core for execution. This allocation mechanism can fully utilize the computing power of high-performance cores when the system load is high, and allocate tasks to low-power cores as much as possible under low-load conditions to maximize the system's energy efficiency. Based on the task allocation scheme, a migration controller is constructed that includes context preservation, shared data synchronization, and task state transition functions.When a task is switched from a high-performance core to a low-power core (or vice versa), the migration controller saves the execution context of the current task, including register data, stack status, and task execution progress. At the same time, data synchronization is implemented in the shared memory area to ensure that the two cores will not cause task errors due to data inconsistency during the switching process. The task state conversion module updates the task state information during task migration, so that the task can be seamlessly resumed on the new core to avoid task failure or restart due to state loss. In order to improve the efficiency of task migration, a hardware-supported snapshot register group is designed in the system, which can complete the save or restore operation of the entire processing core execution context in a single clock cycle. During the task migration process, the snapshot register group quickly transfers the context data to the L0 layer storage area to ensure that the integrity of the task data can be maintained when the system enters the low-power mode. When the task is rescheduled to another core, the register group restores the context data at the same fast speed, so that the task continues to execute on the new core with almost no delay. This zero-overhead context switching mechanism achieves efficient migration of tasks in heterogeneous dual-core systems through efficient hardware design and reasonable storage strategy, allowing the dynamic task allocation mechanism to run efficiently. Through the above steps, a dynamic task allocation mechanism is finally obtained, which enables the system to dynamically select the appropriate processing core according to the task characteristics and system status, thereby minimizing system power consumption while ensuring task execution efficiency.

[0019] 104. Based on the dynamic task allocation mechanism, static analysis and functional block division are performed on the application code to obtain multiple functional code blocks, and storage levels and processor cores are allocated to the multiple functional code blocks to obtain functional code allocation results.

[0020] Specifically, in the static analysis phase, the control flow graph is constructed for the application code, and the program control flow structure is generated by analyzing each branch, loop, and function call in the program. The control flow graph is a directed graph in which nodes represent basic code blocks and edges represent possible execution paths in the program. Through this structured analysis, all possible paths for program execution are obtained, which helps to identify key code paths and frequently executed code blocks. After the control flow graph is constructed, data dependency analysis is performed on the structure to obtain the program data dependency network. In the data dependency analysis, the data flow relationship between different code blocks is tracked, including data read and write operations, memory address references, and the order of data use. This analysis process helps the system identify data-intensive tasks and computation-intensive tasks. According to the program control flow structure and the program data dependency network, the application code is divided into functional blocks, and basic instruction blocks with similar characteristics and close dependencies are combined into independent functional code blocks. For example, for a code segment involving multiple mathematical calculations, it is divided into a computation-intensive functional block; while a data processing code segment that frequently accesses memory is divided into a data-intensive functional block. Through this division, the entire application is decomposed into several functional code blocks, each of which has clear computational complexity, memory access characteristics and energy consumption characteristics. After the functional code block division is completed, the instruction-level energy consumption evaluation is performed on each functional code block, and the theoretical energy consumption of these code blocks executed on the high-performance core (ARM Cortex-M4) and the low-power core (ARM Cortex-M0+) is calculated through the built-in energy consumption model. The energy consumption model evaluates the power consumption performance of each functional block when running on different cores based on the power consumption parameters and memory access patterns of different instruction types, combined with the system status information in the dynamic task allocation mechanism. Based on the energy consumption evaluation results, the functional block core allocation plan is generated to clarify the optimal choice for each functional code block to run on the high-performance core or the low-power core. On the basis of generating the functional block core allocation plan, combined with the functional block execution frequency analysis results, the code of multiple functional code blocks is reorganized to obtain the storage hierarchy allocation plan. In this process, the key codes executed at high frequency are preferentially placed in the L0 layer storage area (8KB ultra-low leakage SRAM) to ensure that these codes can respond to interrupt requests quickly and execute efficiently in low-power mode. The code blocks with moderate execution frequency will be placed in the L1 storage area (32KB main SRAM). Through the regional bit row activation technology, the system only activates the corresponding storage block when needed, thereby reducing unnecessary power consumption. The code blocks with low frequency execution are placed in the L2 storage area and accessed through the adaptive instruction cache, so that the access speed can be improved through the cache when needed, and the memory is kept in a low power state when not needed. In order to enable the system to dynamically adjust the task allocation decision according to the characteristics of the task at runtime, a runtime optimization monitor is created.The monitor includes the functions of collecting execution time, energy consumption and hardware resource utilization, which can continuously track the actual operation status of the system and feed back these real-time data to the dynamic task allocation mechanism. After the system runs for a period of time, the monitor analyzes the efficiency of the current task allocation based on the collected data, such as which tasks have low execution efficiency on the current core, which tasks have energy consumption exceeding expectations, etc. Based on these analysis results, the dynamic task allocation mechanism adjusts the task allocation decision parameters, such as modifying the weight parameters in the core selector and changing the task allocation strategy between high-performance cores and low-power cores. At the same time, the monitor updates the prediction model parameters in the dynamic power management unit to improve the system's prediction accuracy for future workloads, so that the system always maintains the optimal energy efficiency state when responding to different load changes. Through the above steps, the function code allocation result is finally obtained, which includes the specific allocation plan of the function code block in the storage hierarchy and clarifies which processing core each code block should be allocated to run on.

[0021] In the embodiment of the present invention, a heterogeneous dual-core design is adopted to enable the system to intelligently select the most suitable processing core according to the complexity of the task, and minimize the energy consumption of task migration through a zero-overhead context switching mechanism; the refined power domain division realizes independent power state control, so that each functional module can work at the lowest necessary voltage; the subthreshold voltage operation system ensures stable operation within a low voltage range through a full digital phase-locked loop and a timing error prediction circuit, and supports a wide range of frequency adjustment; the multi-level storage architecture optimizes storage access power consumption through ultra-low leakage SRAM, regional bit row activation main SRAM and adaptive instruction cache; hardware-assisted task characteristic analysis and event-driven task scheduling realize dynamic migration of workloads and resource optimization allocation; the closed-loop optimization design combines compile-time static analysis with runtime monitoring, and performs code reorganization and storage optimization according to task characteristics. The present invention significantly reduces the energy consumption of microcontrollers in various working scenarios, prolongs the operating time of battery-powered devices, and provides a more efficient energy utilization solution for Internet of Things terminals and sensor nodes.

[0022] In a specific embodiment, the process of executing step 101 may specifically include the following steps: Configure ARM Cortex-M4 as a high-performance core, set the operating frequency of the high-performance core and add a floating-point unit and DSP instruction set to obtain a computationally intensive processing unit; Configure ARM Cortex-M0+ as a low-power core, set the operating frequency of the low-power core, and obtain a static power optimization processing unit; Build 16KB instruction cache and 16KB data cache for compute-intensive processing units, configure direct access mode for static power-optimized processing units, and obtain a differentiated storage access architecture; A hardware semaphore register is established between the computationally intensive processing unit and the static power optimization processing unit, and an atomic operation is set to obtain an inter-core resource synchronization interlocking mechanism; Based on the inter-core resource synchronization interlock mechanism, a hardware message queue is constructed, and message writing, reading and status query registers are set to obtain an inter-core interrupt data exchange system; Integrate computationally intensive processing units, static power optimization processing units, differentiated memory access architecture, inter-core resource synchronization interlocking mechanism, and inter-core interrupt data exchange system into a single chip, and configure a shared memory area to obtain a heterogeneous dual-core processor; The heterogeneous dual-core processor is divided into multiple independent power domains containing high-performance cores, low-power cores, always-on peripherals, on-demand peripherals and memories.

[0023] Specifically, the ARM Cortex-M4 is configured as a high-performance core designed to handle computationally intensive tasks. By setting the operating frequency of the Cortex-M4 core to MHz, ensuring that it provides sufficient computing power under high computing requirements. At the same time, in order to improve the computing efficiency of the processor, a floating-point unit and a digital signal processing instruction set extension are added to the Cortex-M4 core. This configuration enables the Cortex-M4 to perform well in performing complex mathematical operations (such as FFT, matrix operations) and processing high-speed data streams. For a task that requires a large number of floating-point operations, the amount of calculation is expressed as: in, represents the total amount of computation, is the number of operations in the task, The computational complexity for each operand is . In the Cortex-M4 core equipped with FPU, the computational speed is significantly improved, assuming that the FPU can reduce the number of cycles per floating-point operation to cycle, then the total execution time of the task is: The efficient computing power makes the Cortex-M4 suitable for the role of computationally intensive processing units. At the same time, in order to achieve the low power consumption characteristics of the system, the ARM Cortex-M0+ is configured as a low power core and its operating frequency is set to MHz. The Cortex-MO+ core uses a reduced instruction set architecture and has extremely low static power consumption when processing low-complexity tasks, making it suitable as a static power optimization processing unit. For the same task executed on the Cortex-M0+, since it does not have an FPU, it is assumed that each floating-point operation requires cycles, the total execution time of the task is: Although the Cortex-M0+ does not perform as fast as the Cortex-M4 in computationally intensive tasks, it has a significant power consumption advantage when processing lightweight tasks, especially in standby or low-load mode, which can significantly reduce the overall energy consumption of the system. In order to support efficient data processing of the two cores, a 16KB instruction cache and a 16KB data cache are built for the computationally intensive processing unit (Cortex-M4 core) to improve the access speed of instructions and data. The cache hit rate is expressed as: in, is the number of cache hit accesses, is the total number of accesses. When it is higher, the average memory access time of the system is significantly reduced, thereby improving the processing speed. For the low-power core (Cortex-M0+ core), the direct access mode is used to bypass the cache structure and communicate directly with the low-power SRAM. This differentiated storage access architecture simplifies the hardware design of Cortex-MO+, reduces static power consumption, and avoids the additional energy consumption caused by cache maintenance. It is suitable for low-frequency access scenarios. Between the computationally intensive processing unit and the static power optimization processing unit, a hardware semaphore register is established, and an atomic operation is set to implement an inter-core resource synchronization interlocking mechanism. Assume that the system is configured with Each register performs addition, subtraction, assignment, and other operations through atomic operations, thereby avoiding data contention when two cores access the same resource at the same time. For example, when the Cortex-M4 core needs to access resources in shared memory, a flag bit is set through the semaphore register: , indicating resource occupancy; , indicating that resources are idle. When the Cortex-M0+ core detects When the resource is idle, access to the resource will be suspended until the resource is idle. This mechanism ensures the security of resource access and data consistency. Based on the inter-core resource synchronization interlock mechanism, a hardware message queue is constructed, and the message write, read and status query registers are set to obtain the inter-core interrupt data exchange system. Assume that the message queue contains 32-bit message slots, each of which can store a task or data packet. When the message queue receives new data, it triggers an interrupt signal to the processing core. For example, when the Cortex-M4 core completes a calculation task, it writes the result to the shared memory through the message queue: Then the Cortex-MO+ core is notified through the interrupt mechanism to read the data and continue to execute subsequent tasks. This hardware message queue design effectively improves the data exchange efficiency between the two cores and reduces the interrupt response time. The computationally intensive processing unit, static power optimization processing unit, differentiated storage access architecture, inter-core resource synchronization interlock mechanism and inter-core interrupt data exchange system are integrated into a single chip, and a 32KB shared memory area is configured to allow the two cores to access shared data through the same physical address space, but different access rights are set through the memory protection unit. For example, the Cortex-M4 core has read and write permissions, while the Cortex-M0+ core only has read permissions. This design can prevent the occurrence of data race conditions and provide flexibility for dynamic task allocation. After the chip design is completed, the heterogeneous dual-core processor is divided into multiple independent power domains, including high-performance core power domain, low-power core power domain, permanent online peripheral power domain, on-demand peripheral power domain and memory power domain. Each power domain independently controls the voltage and switch state, and the working state of each power domain is dynamically adjusted through the central power management controller. For example, when the system is in low-power mode, the high-performance core power domain is turned off, and only the power domains of the low-power core and permanently online peripherals are kept active, thereby minimizing the overall power consumption of the system. Signal isolation between power domains is performed through level converters to ensure that signal transmission between different voltage domains is not affected.

[0024] In a specific embodiment, the process of executing the step of dividing the heterogeneous dual-core processor into multiple independent power domains including high-performance cores, low-power cores, permanently online peripherals, on-demand peripherals and memories may specifically include the following steps: Physically isolate the high-performance core and its floating-point unit and tightly coupled peripherals in the heterogeneous dual-core processor to obtain a high-performance core power domain; Physically isolating the low-power core and its directly connected interface in the heterogeneous dual-core processor to obtain a low-power core power domain; Physically isolate the real-time clock, power management unit, and wake-up controller combination to obtain a permanently online peripheral power domain; Physically isolate the high-power peripheral combination of USB interface, ADC, and DAC to obtain the on-demand peripheral power domain, and physically isolate the shared memory and program memory to obtain the memory power domain; A high-performance core power domain, a low-power core power domain, a permanently online peripheral power domain, an on-demand peripheral power domain, and a memory power domain are taken as multiple independent power domains, and signal conversion circuits are set between the multiple independent power domains.

[0025] Specifically, when building a high-performance core power domain, the ARM Cortex-M4 high-performance core and its accompanying floating-point unit and tightly coupled peripherals are physically isolated. The design goal of the high-performance core power domain is to provide sufficient computing power when the system runs computationally intensive tasks, while allowing dynamic shutdown to reduce power consumption in non-high-load states. Assume that the voltage of the Cortex-M4 core during operation is , the operating frequency is MHz, its power consumption is expressed by the formula: in, The power consumption of the high-performance core is is the equivalent capacitance of the circuit. When running a computing task, if the number of instructions required to execute the task is , the average execution cycle of instructions is , then the total energy consumption to complete the task is expressed as: in, The execution time of the task. By physically isolating the high-performance core and its peripherals in the hardware design, the core is separated into a controllable power domain, so that the domain can be completely shut down when the system is in low-power mode, thereby reducing power consumption to near zero. At the same time, for the ARM Cortex-M0+ low-power core, a similar physical isolation method is used to assign the low-power core and its directly connected interfaces to an independent low-power core power domain. The voltage of the low-power core is set to , the operating frequency is MHz. When processing light tasks, its power consumption is calculated as: in, is the equivalent capacitance of the low-power core. Assume that the number of instructions required for a task to be executed on the low-power core is , the average execution time of each instruction is , the corresponding energy consumption is: Compared with the high-performance core, the low-power core consumes significantly less energy and is suitable for keeping basic functions running when the system is idle, such as handling external interrupts and low-speed data processing tasks. By physically isolating the low-power core into a separate power domain, the system can be kept running at the lowest energy consumption when the high-performance core is turned off. For the peripheral part of the system, in order to achieve 24-hour online function, the real-time clock, power management unit and wake-up controller are combined and physically isolated to form a permanently online peripheral power domain. The design goal of this power domain is to maintain the lowest power consumption when the system is in sleep or deep sleep mode. Assume that the operating voltage of the permanently online peripheral is , the static power consumption is , even during long sleep periods, this domain still needs to maintain basic system functions, such as timing, monitoring power status, and responding to external wake-up signals. Its total energy consumption is: in, is the length of time the system is in sleep mode. This design ensures that the system can quickly return to an active state when triggered by an external event, without causing a complete failure of the system due to shutting down all power domains. In addition, the high-power peripheral modules in the system, including USB interfaces, analog-to-digital converters, and digital-to-analog converters, are only used in specific scenarios, so these peripherals are combined and physically isolated to form an on-demand peripheral power domain. When the system does not need these peripherals, the power domain is completely shut down, thereby effectively reducing power consumption. In the storage part, shared memory and program memory also need to be physically isolated to obtain an independent memory power domain. The design of this power domain allows the memory to dynamically adjust the voltage according to the system load, such as maintaining a higher voltage when data is frequently accessed (for example, ), while dropping to a lower voltage when the data only retains the state (e.g. ). The power consumption of the memory is expressed as: in, is the equivalent capacitance of the memory, is the memory access frequency. This dual voltage power supply design can provide sufficient memory bandwidth when the system requires efficient data processing, and minimize the power consumption of the memory when the system is in low power mode. After completing the physical isolation of all independent power domains, a signal conversion circuit is set between these power domains. Since different power domains operate in different voltage ranges (such as 1.2V, 0.6V, 0.5V, etc.), the main function of the signal conversion circuit is to convert the signal level of one power domain to a level that can be recognized by another power domain. The signal conversion circuit includes a bidirectional level converter and a unidirectional level converter. For example, a 16-bit wide bidirectional level converter is used for data communication between a high-performance core and a low-power core, while a 32-bit unidirectional converter is used to transfer data between high-power peripherals and memory.

[0026] In a specific embodiment, the process of executing step 102 may specifically include the following steps: Distributing multiple delay monitors on the target timing path of the heterogeneous dual-core processor to obtain a timing error prediction circuit; Based on the timing error prediction circuit, a timing management system including a central sampling unit and a prediction controller is constructed, and the target path delay data is collected and converted to obtain the minimum stable operating voltage value; Based on the minimum stable operating voltage value, the external interrupt source characteristics of multiple independent power domains are analyzed to obtain event classification results. Based on the event classification results, a workload predictor and a state transition controller are constructed to obtain a sub-threshold voltage operation system. A multi-level storage structure is configured in a heterogeneous dual-core processor based on a subthreshold voltage operating system.

[0027] Specifically, multiple delay monitors are distributed on the target timing path of the heterogeneous dual-core processor to construct a timing error prediction circuit to ensure that the timing accuracy of data processing is guaranteed when the processor runs at a low voltage, thereby avoiding timing errors caused by voltage reduction. In the processor, the delay of the key timing path is the main factor affecting the stability of the system. By distributing delay monitors on these paths, information on delay changes in the circuit can be captured in real time. The working principle of the delay monitor is to compare the clock signal with the output of the key data path. When the delay of the data path exceeds the clock cycle, the monitor will generate a timing error signal. Assume that the clock cycle of the processor is , the data path delay is , when the conditions are met: When the timing error signal is triggered, the timing error signal will be triggered. By arranging multiple delay monitors on different timing paths, the actual delay data of each path can be obtained. Based on the timing error prediction circuit, a timing management system including a central sampling unit and a prediction controller is constructed. The function of the central sampling unit is to collect data from all delay monitors in each clock cycle and pass these data to the prediction controller in the form of digital signals. The prediction controller calculates the minimum stable operating voltage value required by the processor at the current operating frequency by analyzing these delay data. This minimum stable voltage value is a key parameter to ensure that all timing paths can complete data propagation within the clock cycle. Assume that the critical path delay of the processor is , the operating frequency is , then the minimum clock cycle required by the processor is: The predictive controller determines whether the current voltage is sufficient to support the current frequency operation by comparing the delay data with the clock cycle. If the delay is too large, the predictive controller will use the formula: Calculate the minimum stable operating voltage value ,in is the reference voltage, is the maximum delay detected, is the clock cycle. When the prediction controller detects that a higher voltage is needed to ensure correct timing, it will send a signal to the power management module to increase the operating voltage of the processor; when the delay margin is large, the voltage is reduced to save energy. Based on the minimum stable operating voltage value, the characteristics of the external interrupt sources of multiple independent power domains are analyzed to achieve dynamic load management of the system. The external interrupt sources in each power domain correspond to different types of tasks, and the frequency and urgency of these tasks vary. By analyzing the characteristics of the interrupt sources, the events are classified into four types: low frequency and low urgency, low frequency and high urgency, high frequency and low urgency, and high frequency and high urgency. Assuming the event arrival rate is , the processing time is , the urgency of an event is defined as: in, Indicates the urgency of the incident. When the urgency is high (e.g. ,in For events with low urgency, the system needs to respond to the event first and increase the processor voltage to ensure processing speed. For events with low urgency, the system chooses to reduce the frequency or switch to low-power core processing to save energy. Based on the event classification results, a workload predictor and state transition controller are constructed. The workload predictor predicts the possible future load conditions by analyzing the arrival rate, processing time and resource utilization of historical events. For example, based on past The average arrival rate of events and processing time , the load for the next period is predicted to be: The predicted load information will be passed to the state transition controller, which dynamically adjusts the working mode of each power domain according to the current system voltage and frequency status, such as switching the high-performance core to the low-power core, or putting some peripherals into sleep mode. This dynamic adjustment is achieved by adjusting the system's operating voltage and frequency. The optimal operating point calculated by the controller is expressed as: in, is the power consumption, is the circuit equivalent capacitance, is the voltage, is the frequency. At low load, reduce and Significantly reduces power consumption, while at high loads and To improve the system responsiveness. In order to keep the data access efficiency when the system is running at low voltage, a multi-level storage structure is configured in the heterogeneous dual-core processor based on the sub-threshold voltage operation system. This storage structure is divided into three storage areas: L0, L1 and L2, and each level has different power consumption and access speed characteristics. For example, the L0 layer uses 8KB ultra-low leakage SRAM to store critical data and high-priority tasks. The L1 layer is a 32KB main SRAM, and the dynamic activation of some storage blocks is achieved through regional bit row activation technology. The L2 layer is an adaptive instruction cache, which dynamically adjusts the cache size and association according to the data access mode. By activating only the L0 layer storage area in low power mode and activating both the L1 and L2 layer storage areas in high load mode, the system can flexibly adapt to different application scenarios, thereby achieving the lowest energy consumption while ensuring performance.

[0028] In a specific embodiment, the process of configuring a multi-level storage structure in a heterogeneous dual-core processor according to a subthreshold voltage operating system may specifically include the following steps: Based on the low voltage working requirements of the subthreshold voltage operation system, 8KB ultra-low leakage SRAM is configured and independent read and write paths and double-terminal stabilization circuits are added to obtain the L0 layer storage area; Based on the dynamic power supply control characteristics of the subthreshold voltage operation system, a 32KB main SRAM is configured and divided into eight 4KB storage blocks. Each 4KB storage block is equipped with an independent row decoder and bit line driver to obtain the L1 layer storage area. Map the L1 layer storage area to a preset address space and connect it to the memory power domain to obtain the L2 layer storage area; Based on the L0 layer storage area, the L1 layer storage area and the L2 layer storage area, an intelligent DMA controller including 8 independent channels is created to obtain a multi-level storage structure.

[0029] Specifically, based on the low voltage working requirements of the subthreshold voltage operating system, an 8KB ultra-low leakage SRAM is configured, and an independent read-write path and a two-terminal stabilization circuit are designed for it to form an L0 layer storage area. The design goal of the L0 layer storage area is to ensure fast access to key data when the system works in a low voltage environment, while avoiding excessive increase in power consumption. Due to the low voltage characteristics of the subthreshold voltage operating system, the L0 layer storage area needs to be equipped with an ultra-low leakage SRAM, which can work stably at extremely low voltages and has extremely low leakage current. In order to improve the reliability of data access, the SRAM is configured with independent read and write paths. These paths do not interfere with each other during different operations, ensuring that there will be no conflict between write operations and read operations, while avoiding additional energy consumption caused by inconsistency in memory access. In order to ensure the stability of the memory under low voltage conditions, the L0 layer adopts a two-terminal stabilization circuit. This circuit design prevents data errors when reading and writing by increasing the stability between the power supply and the ground, especially in the case of large voltage fluctuations. According to the dynamic power supply control characteristics of the sub-threshold voltage operating system, a 32KB main SRAM is configured and divided into 8 4KB storage blocks. Each 4KB storage block is equipped with an independent row decoder and bit line driver to form the L1 layer storage area. The design purpose of the L1 layer storage area is to reduce power consumption by dividing the storage space into blocks. Each storage block uses an independent row decoder and bit line driver so that only the required storage area is activated when the memory is accessed, thereby reducing unnecessary energy consumption. When performing storage operations, each 4KB storage block is activated according to the needs of data access. For example, if the task only needs to read part of the data, only the corresponding storage row will be activated, thereby reducing the power consumption caused by accessing other irrelevant data blocks. This design of activating storage blocks on demand reduces power consumption when processing lightweight tasks, allowing the system to work more efficiently under low load conditions. Assume that the activation power consumption of each storage block is , the number of activated storage blocks is , the total power consumption is expressed as: in, represents the power consumption of each storage block, Indicates the number of currently activated storage blocks. When the system load is low, the number of activated storage blocks is small and the power consumption is reduced accordingly. Based on the L1 layer storage area, the L2 layer storage area is designed as a mapping area of ​​the memory power domain. The L2 layer storage area forms a more efficient data transmission path by mapping the contents of the L1 layer storage area to the preset address space and connecting it to the memory power domain. The role of the L2 layer is to cache and transmit data more efficiently, especially when processing large-scale data. The L2 cache provides data pre-fetching and accelerated reading capabilities. When the L1 layer cannot meet the high-speed data access requirements, the data will be automatically loaded to the L2 layer to increase the subsequent access speed. Assume that the access speed of the L2 cache is , the capacity of L2 cache is , then its bandwidth is expressed as: in, is the bandwidth of the L2 cache, is the access speed of the cache, is the capacity of the cache. The addition of L2 cache can speed up data access and provide more storage space for the system, thereby reducing the pressure on the main memory and optimizing the overall performance of the system. Based on the L0 layer storage area, L1 layer storage area and L2 layer storage area, an intelligent DMA controller with 8 independent channels is created. This DMA controller is responsible for efficiently transferring data between multiple storage areas to avoid the CPU core being occupied due to data movement. The DMA controller reduces CPU intervention and improves the efficiency of data transmission by directly transferring data from one storage area to another. Assume that the transmission rate of each DMA channel is , the amount of data transmitted for each channel is , the total bandwidth of the DMA controller is expressed as: in, is the total bandwidth, is the transfer rate for each DMA channel, and 8 is the number of independent channels. With this design, the DMA controller completes data transfer with extremely low latency, and when the processor load is high, the DMA controller can still ensure the stability and reliability of the data flow. This multi-channel parallel data transmission mode improves the system's response speed during data processing and effectively reduces system power consumption. Combining the advantages of the L0, L1, and L2 layer storage structures, the design of the multi-level storage structure enables the system to flexibly select the most suitable storage area for data storage and access according to the needs of different tasks. When the system load is low, the L0 layer storage area provides fast data response, and when the load increases, the L1 and L2 layer storage areas can provide larger storage space and higher access bandwidth.

[0030] In a specific embodiment, the process of executing step 103 may specifically include the following steps: Perform statistical analysis on instruction types, branch behaviors, and memory access patterns during task execution to obtain task characteristic data; The task characteristic data is stored in the L0 layer storage area of ​​the multi-level storage structure, and the identifier, computational complexity index, memory access characteristics and energy consumption estimation result of each task are recorded to obtain the task characteristic data set; Based on the task feature data set, the tasks are divided into computationally intensive, data intensive, mixed and lightweight types to obtain the task classification results; According to the task classification results and the system status information provided by the subthreshold voltage operation system, a core selector is constructed to determine whether to allocate a task to a high-performance core or a low-power core, and a task allocation plan is obtained; Based on the task allocation scheme, a migration controller with context saving, shared data synchronization and task state transition functions is constructed to transfer the execution rights of tasks between high-performance cores and low-power cores, thus obtaining a task migration execution system. A hardware-supported snapshot register set is created for the task migration execution system, and the context data is stored in the 8KB ultra-low leakage SRAM in the L0 layer storage area to obtain a dynamic task allocation mechanism.

[0031] Specifically, statistical analysis is performed on instruction types, branch behaviors, and memory access patterns during task execution. Various behavioral data generated during task execution are collected in real time through hardware-assisted monitoring modules. Statistics of instruction types help to understand the operational characteristics involved in the task, such as whether it is a floating-point calculation, integer calculation, or logical operation. Branch behavior analysis can capture the frequency and pattern of jump instructions in the program, while analysis of memory access patterns reveals the memory access pattern of the task at runtime, such as the locality of the accessed memory address, the read-write ratio, etc. The statistically obtained task characteristic data is stored in the L0 layer storage area in the multi-level storage structure. The L0 layer storage area is designed as an 8KB ultra-low leakage SRAM. This storage area is designed to quickly access the characteristic data of the task while ensuring stable operation under low voltage. For each task, key characteristic data such as its identifier, computational complexity index, memory access characteristics, and energy consumption estimation results are recorded. Computational complexity index Memory access characteristics measured by the number and type of operations in a task This includes data access frequency, memory access timing and address mode. It is determined by the computational complexity and memory access pattern and is expressed by the following formula: in, To calculate the specific energy consumption of an operation, is the unit energy consumption of memory access, and They are the workload of calculation and storage respectively. The task feature data set obtained by calculation can help the system fully understand the nature of the task. Based on the task feature data set, the tasks are classified into calculation-intensive, data-intensive, hybrid and lightweight tasks. According to the characteristics of the task, the appropriate processing core is selected for it. Computation-intensive tasks mainly rely on the arithmetic operation capability of the CPU, data-intensive tasks rely more on the bandwidth of the memory, hybrid tasks have both calculation and data access characteristics, and lightweight tasks have fewer resource requirements. The formula for task classification is expressed as: in, is the type of task, For the computational complexity, is the memory access characteristic, function Determine the criteria for task classification. For example, when both the computational complexity and memory access characteristics are high, the task is classified as a hybrid task; if the computational complexity is low but the memory access is frequent, the task is classified as a data-intensive task. Based on the task classification results and the system status information provided by the subthreshold voltage operating system, a core selector is constructed to decide whether to assign the task to a high-performance core or a low-power core. The core selector makes decisions based on the task classification results. Computational-intensive tasks are preferentially assigned to high-performance cores (such as Cortex-M4), while data-intensive tasks are assigned to low-power cores (such as CortexMO+). Hybrid tasks dynamically select the most suitable core based on actual computing and storage requirements, while lightweight tasks are assigned to low-power cores to save energy. The core selection process is expressed by the following formula: in, For the selected core type, is the task type, is the current voltage state of the system. Based on the task type and the system voltage state, the core selector determines whether the task should run on a high-performance core or a low-power core. Based on the task allocation scheme, a migration controller is constructed to transfer the execution rights of tasks between high-performance cores and low-power cores. The main functions of the migration controller are to support context saving, shared data synchronization, and task state transition. The context saving process includes saving the current register state, memory data, and execution state of the task. When a task is transferred from one core to another, the original execution state needs to be restored. Shared data synchronization ensures that tasks executed between multiple cores can maintain data consistency when accessing shared resources. The task state transition function ensures that the task can resume execution smoothly during the migration process. For example, suppose the state of the task includes the calculation state and data status , these two states need to be saved and restored during the migration process: The migration controller ensures seamless migration of tasks between cores through context saving and state restoration. In order to improve the efficiency of task migration, hardware-supported snapshot register groups are created for the task migration execution system. These registers can quickly save and restore the execution context of the task when the task migrates. Each snapshot register group can complete the task state save and restore operations within one clock cycle, thus avoiding the delay and overhead caused by traditional software-controlled migration. During the migration process, the task context data is stored in the 8KB ultra-low leakage SRAM in the L0 layer storage area, ensuring that the task state can be saved and restored quickly and stably even in a low-voltage environment. Through dynamic task allocation and an efficient task migration execution mechanism, it is ensured that each task running on the heterogeneous dual-core processor can be executed on the appropriate core, thereby maximizing performance and minimizing power consumption.

[0032] In a specific embodiment, the process of executing step 104 may specifically include the following steps: Based on the dynamic task allocation mechanism, the control flow graph construction operation is performed on the application code to obtain the program control flow structure, and the data dependency analysis of the program control flow structure is performed to obtain the program data dependency network; According to the program control flow structure and the program data dependency network, the application code is divided into functional blocks to obtain multiple functional code blocks; Perform instruction-level energy consumption evaluation on multiple functional code blocks, calculate the theoretical energy consumption of each functional code block executed on a high-performance core and a low-power core, and obtain a functional block core allocation plan; According to the function block core allocation plan and the function block execution frequency analysis results, multiple function code blocks are reorganized to obtain a storage level allocation plan; Based on the storage hierarchy allocation scheme and the function block core allocation scheme, a runtime optimization monitor with execution time, energy consumption and hardware resource utilization collection functions is created, and the task allocation decision parameters in the dynamic task allocation mechanism are dynamically updated to obtain the function code allocation result.

[0033] Specifically, a control flow graph is constructed for the application code to obtain the control flow structure of the program. A control flow graph is a data structure that represents the execution path of a program. The nodes in the graph represent basic blocks, and the edges represent the control flow in the program, indicating which basic blocks the program may jump to when executing. By constructing this control flow graph, information such as jump instructions, loop structures, and conditional judgments in the program can be effectively captured. The construction of the control flow graph is based on the instruction type and branching behavior in the program. For example, suppose there is an if statement in the program, which will execute two different instruction paths depending on different conditions. The branching relationship of this path will be represented by the nodes and edges in the graph. Data dependency analysis is performed on the program control flow structure to obtain the program data dependency network. Data dependency analysis refers to determining which instructions depend on the results of other instructions by analyzing the data transfer relationship between each instruction in the program. In data dependency analysis, two types of data dependencies are mainly analyzed: value dependency and control dependency. Value dependency means that the output of one instruction is the input of another instruction, and control dependency means that the execution path of a certain instruction depends on the result of another instruction. Through this analysis, a data dependency network of the program is constructed, which reflects the execution order and dependency of each instruction in the program, and can help the system understand the computational structure of the task and potential execution bottlenecks. Assuming that there are two instructions in the program, and the output of instruction A is the input of instruction B, there is a value dependency relationship between instruction A and instruction B, which is represented by the edge in the graph. According to the program control flow structure and the program data dependency network, the application code is divided into functional blocks to obtain multiple functional code blocks. The program code is grouped according to its computing characteristics and data access characteristics, and each functional code block represents a data processing process with independent computing characteristics. For example, a computing-intensive task is divided into one functional code block, and a memory access-intensive task is divided into another functional code block. The purpose of functional block division is to enable the system to dynamically select the appropriate execution core according to the characteristics of each functional code block, thereby improving the overall performance and energy efficiency of the system. For each functional code block, it is marked as a computing-intensive, data-intensive, mixed or lightweight task according to its computational complexity and storage access characteristics. Computation-intensive tasks include a large number of arithmetic operations, while data-intensive tasks involve a large number of memory access operations. Hybrid tasks include both computation and data operations, while lightweight tasks have lower computation and memory requirements. Perform instruction-level energy consumption evaluation on multiple functional code blocks. Calculate the theoretical energy consumption of each functional code block on high-performance cores and low-power cores based on the execution instruction type, memory access pattern, and branch behavior of each functional code block. For example, suppose the computational complexity of a functional code block is , the energy consumption on the high-performance core is , the energy consumption on the low-power core is , the theoretical energy consumption of the functional code block on two cores is calculated by the following formula: in, and are the unit energy consumption of the high-performance core and the low-power core, respectively. On the high-performance core, the execution speed of the computing task is faster, but the corresponding power consumption is also higher; on the low-power core, the power consumption is lower, but the execution speed is slower. According to the energy consumption evaluation results of each functional code block, the most suitable core is selected for execution, and a functional block core allocation plan is formed. According to the functional block core allocation plan and the functional block execution frequency analysis results, multiple functional code blocks are reorganized to obtain a storage hierarchy allocation plan. The goal of code reorganization is to optimize memory access and data transmission according to the execution frequency and access mode of the functional code blocks. For example, frequently accessed functional code blocks are placed in the cache, while infrequently used code blocks are placed in the main memory. The storage hierarchy allocation scheme can effectively improve the system's memory bandwidth utilization and reduce memory access latency. Assume that the execution frequency of a certain functional code block is , the memory access latency is , then the memory access bandwidth of the code block is expressed as: During the code reorganization process, consider the cache hit rate of each functional code block to further improve access efficiency. When the data frequently accessed by a functional code block can be cached, the system chooses to cache its data in high-speed memory, thereby reducing unnecessary memory access. Create a runtime optimization monitor. The function of the runtime optimization monitor is to continuously track the execution time, energy consumption, and hardware resource utilization of the system, and dynamically update the task allocation decision parameters based on real-time data. The monitor evaluates the operating efficiency of the current task by collecting the usage of each core and memory. For example, suppose the execution time of a task is Energy consumption is , the hardware resource utilization is ,The monitor adjusts the core allocation and memory hierarchy allocation of tasks ,according to these parameters to ensure the lowest power consumption and ,optimal performance under different load situations.

[0034] The ultra-low power consumption microcontroller architecture design method in the embodiment of the present invention is described above. The ultra-low power consumption microcontroller architecture design system in the embodiment of the present invention is described below. Figure 2 , an embodiment of the ultra-low power consumption microcontroller architecture design system in the embodiment of the present invention includes: A construction module 201 is used to construct a heterogeneous dual-core processor including a high-performance core and a low-power core, and divide the heterogeneous dual-core processor into multiple independent power domains including the high-performance core, the low-power core, the permanent online peripherals, the on-demand peripherals and the memory; Configuration module 202, used to construct a subthreshold voltage operation system on multiple independent power domains, and configure a multi-level storage structure in a heterogeneous dual-core processor according to the subthreshold voltage operation system; The recording module 203 is used to record the task characteristic data using a multi-level storage structure, and to perform dynamic task allocation between the two cores to create a dynamic task allocation mechanism; The allocation module 204 is used to perform static analysis and functional block division on the application code based on the dynamic task allocation mechanism to obtain multiple functional code blocks, and allocate storage levels and processor cores to the multiple functional code blocks to obtain functional code allocation results.

[0035] Through the cooperation of the above components, the heterogeneous dual-core design enables the system to intelligently select the most suitable processing core according to the complexity of the task, and minimize the energy consumption of task migration through the zero-overhead context switching mechanism; the refined power domain division realizes independent power state control, so that each functional module can work at the lowest necessary voltage; the subthreshold voltage operation system ensures stable operation within the low voltage range through the full digital phase-locked loop and the timing error prediction circuit, and supports a wide range of frequency adjustment; the multi-level storage architecture optimizes storage access power consumption through ultra-low leakage SRAM, regional bit row activation main SRAM and adaptive instruction cache; hardware-assisted task characteristic analysis and event-driven task scheduling realize dynamic migration of workload and resource optimization allocation; the closed-loop optimization design combines compile-time static analysis with runtime monitoring, and performs code reorganization and storage optimization according to task characteristics. The present invention significantly reduces the energy consumption of the microcontroller in various working scenarios, prolongs the operating time of battery-powered devices, and provides a more efficient energy utilization solution for Internet of Things terminals and sensor nodes.

[0036] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, systems and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0037] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the whole or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0038] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for designing an ultra-low power microcontroller architecture, characterized in that: The method comprises: Constructing a heterogeneous dual-core processor including a high-performance core and a low-power core, and dividing the heterogeneous dual-core processor into a plurality of independent power domains including the high-performance core, the low-power core, permanently online peripherals, on-demand peripherals, and memory; Constructing a subthreshold voltage operation system on the multiple independent power domains, and configuring a multi-level storage structure in the heterogeneous dual-core processor according to the subthreshold voltage operation system; Using the multi-level storage structure to record task characteristic data, and performing dynamic task allocation between dual cores, a dynamic task allocation mechanism is created; Based on the dynamic task allocation mechanism, the application code is statically analyzed and divided into functional blocks to obtain multiple functional code blocks, and the multiple functional code blocks are allocated to storage levels and processor cores to obtain functional code allocation results.

2. The ultra-low power consumption microcontroller architecture design method according to claim 1, characterized in that: The construction includes a heterogeneous dual-core processor including a high-performance core and a low-power core, and the heterogeneous dual-core processor is divided into multiple independent power domains including a high-performance core, a low-power core, a permanent online peripheral, an on-demand peripheral, and a memory, including: Configuring ARM Cortex-M4 as a high-performance core, setting the operating frequency of the high-performance core and adding a floating-point operation unit and a DSP instruction set to obtain a computationally intensive processing unit; Configuring ARM Cortex-M0+ as a low-power core, setting the operating frequency of the low-power core, and obtaining a static power consumption optimization processing unit; Constructing a 16KB instruction cache and a 16KB data cache for the computationally intensive processing unit, configuring a direct access mode for the static power consumption optimized processing unit, and obtaining a differentiated storage access architecture; Establishing a hardware semaphore register between the computationally intensive processing unit and the static power consumption optimization processing unit, and performing atomic operation settings to obtain an inter-core resource synchronization interlocking mechanism; Based on the inter-core resource synchronization interlocking mechanism, a hardware message queue is constructed, and message writing, reading and status query registers are set to obtain an inter-core interrupt data exchange system; Integrate the computationally intensive processing unit, the static power consumption optimization processing unit, the differentiated storage access architecture, the inter-core resource synchronization interlocking mechanism and the inter-core interrupt data exchange system into a single chip, and configure a shared memory area to obtain a heterogeneous dual-core processor; The heterogeneous dual-core processor is divided into a plurality of independent power domains including a high-performance core, a low-power core, permanent online peripherals, on-demand peripherals and a memory.

3. The ultra-low power consumption microcontroller architecture design method according to claim 2, characterized in that: The heterogeneous dual-core processor is divided into a plurality of independent power domains including a high-performance core, a low-power core, a permanent online peripheral, an on-demand peripheral and a memory, including: Physically isolating the high-performance core and its floating-point operation unit and tightly coupled peripherals in the heterogeneous dual-core processor to obtain a high-performance core power domain; Physically isolating the low-power core in the heterogeneous dual-core processor and its directly connected interface to obtain a low-power core power domain; Physically isolate the real-time clock, power management unit, and wake-up controller combination to obtain a permanently online peripheral power domain; Physically isolate the high-power peripheral combination of USB interface, ADC, and DAC to obtain the on-demand peripheral power domain, and physically isolate the shared memory and program memory to obtain the memory power domain; The high-performance core power domain, the low-power core power domain, the permanent online peripheral power domain, the on-demand peripheral power domain and the memory power domain are used as multiple independent power domains, and signal conversion circuits are set between the multiple independent power domains.

4. The ultra-low power consumption microcontroller architecture design method according to claim 3, characterized in that: The step of constructing a subthreshold voltage operating system on the plurality of independent power domains and configuring a multi-level storage structure in the heterogeneous dual-core processor according to the subthreshold voltage operating system includes: Distributing a plurality of delay monitors on a target timing path of the heterogeneous dual-core processor to obtain a timing error prediction circuit; Based on the timing error prediction circuit, a timing management system including a central sampling unit and a prediction controller is constructed, and target path delay data is collected and converted to obtain a minimum stable operating voltage value; Based on the minimum stable operating voltage value, the external interrupt source characteristics of the multiple independent power domains are analyzed to obtain event classification results, and according to the event classification results, a workload predictor and a state transition controller are constructed to obtain a sub-threshold voltage operation system; A multi-level storage structure is configured in the heterogeneous dual-core processor according to the subthreshold voltage operating system.

5. The ultra-low power consumption microcontroller architecture design method according to claim 4, characterized in that: The configuring a multi-level storage structure in the heterogeneous dual-core processor according to the subthreshold voltage operation system includes: Based on the low voltage working requirements of the subthreshold voltage operating system, an 8KB ultra-low leakage SRAM is configured and an independent read / write path and a dual-terminal stabilization circuit are added to obtain an L0 layer storage area; Based on the dynamic power supply control characteristics of the subthreshold voltage operation system, a 32KB main SRAM is configured, and the 32KB main SRAM is divided into 8 4KB storage blocks, each 4KB storage block is equipped with an independent row decoder and a bit line driver, to obtain an L1 layer storage area; Mapping the L1 layer storage area to a preset address space and connecting it to the memory power domain to obtain an L2 layer storage area; Based on the L0 layer storage area, the L1 layer storage area and the L2 layer storage area, an intelligent DMA controller including 8 independent channels is created to obtain a multi-level storage structure.

6. The ultra-low power consumption microcontroller architecture design method according to claim 1, characterized in that: The method of using the multi-level storage structure to record task characteristic data and dynamically allocate tasks between the two cores to create a dynamic task allocation mechanism includes: Perform statistical analysis on instruction types, branch behaviors, and memory access patterns during task execution to obtain task characteristic data; The task characteristic data is stored in the L0 layer storage area of ​​the multi-level storage structure, and the identifier, computational complexity index, memory access characteristics and energy consumption estimation result of each task are recorded to obtain a task characteristic data set; Based on the task feature data set, the tasks are divided into computationally intensive, data intensive, mixed and lightweight types to obtain task classification results; According to the task classification result and the system status information provided by the subthreshold voltage operation system, a core selector is constructed to determine whether to allocate a task to a high-performance core or a low-power core, and a task allocation plan is obtained; Based on the task allocation scheme, a migration controller including context saving, shared data synchronization and task state conversion functions is constructed to transfer the execution right of tasks between the high-performance core and the low-power core to obtain a task migration execution system; A hardware-supported snapshot register group is created for the task migration execution system, and context data is stored in the 8KB ultra-low leakage SRAM in the L0 layer storage area to obtain a dynamic task allocation mechanism.

7. The ultra-low power consumption microcontroller architecture design method according to claim 1, characterized in that: The method of performing static analysis and functional block division on the application code based on the dynamic task allocation mechanism to obtain a plurality of functional code blocks, and performing storage hierarchy and processor core allocation on the plurality of functional code blocks to obtain a functional code allocation result includes: Based on the dynamic task allocation mechanism, a control flow graph construction operation is performed on the application code to obtain a program control flow structure, and a data dependency analysis is performed on the program control flow structure to obtain a program data dependency network; Dividing the application code into functional blocks according to the program control flow structure and the program data dependency network to obtain a plurality of functional code blocks; Performing instruction-level energy consumption evaluation on the multiple functional code blocks, calculating the theoretical energy consumption of each functional code block executed on the high-performance core and the low-power core, and obtaining a functional block core allocation plan; According to the function block core allocation scheme and the function block execution frequency analysis results, the plurality of function code blocks are reorganized to obtain a storage level allocation scheme; Based on the storage hierarchy allocation scheme and the functional block core allocation scheme, a runtime optimization monitor including execution time, energy consumption and hardware resource utilization collection functions is created, and the task allocation decision parameters in the dynamic task allocation mechanism are dynamically updated to obtain the function code allocation result.

8. An ultra-low power microcontroller architecture design system, characterized in that: The system is used to execute the ultra-low power consumption microcontroller architecture design method according to any one of claims 1 to 7, the system comprising: A building module for building a heterogeneous dual-core processor including a high-performance core and a low-power core, and dividing the heterogeneous dual-core processor into a plurality of independent power domains including the high-performance core, the low-power core, permanently online peripherals, on-demand peripherals and memory; A configuration module, configured to construct a subthreshold voltage operation system on the plurality of independent power domains, and configure a multi-level storage structure in the heterogeneous dual-core processor according to the subthreshold voltage operation system; A recording module, used to record task characteristic data using the multi-level storage structure, and to perform dynamic task allocation between the two cores, thereby creating a dynamic task allocation mechanism; The allocation module is used to perform static analysis and functional block division on the application code based on the dynamic task allocation mechanism to obtain multiple functional code blocks, and to allocate storage levels and processor cores to the multiple functional code blocks to obtain functional code allocation results.

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