Sense amplifier, operation method thereof and memory

Abstract

The invention provides a sense amplifier, an operation method thereof and a memory. The sensing amplifier comprises a sensing amplification circuit which comprises a first node, a second node, a third node and a fourth node and is configured to perform signal amplification processing in an amplification stage; the offset elimination circuit is coupled to the first node and the second node and is configured to perform offset elimination processing in an offset elimination stage; the first control circuit is coupled to the third node and is configured to control the connection state between the third node and the first voltage node when the first control circuit is in an offset elimination stage and control the current of the offset elimination stage by utilizing a current source in the first control circuit when the third node is coupled to the first voltage node; the second control circuit is coupled to the fourth node and is configured to control the connection state between the fourth node and the second voltage node when the second control circuit is in the offset elimination stage; wherein the voltage of the first voltage node is smaller than that of the second voltage node.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, including but not limited to a sense amplifier and an operation method thereof, and a memory. Background Art

[0002] The sense amplifier (SA) is an important component of the memory, which can amplify the signal on the bit line to perform a read or write operation. Due to differences in process technology and the influence of the working environment, the size and threshold voltage of each transistor in the sense amplifier may be different, and the performance of each transistor is usually not exactly the same, which will cause the sense amplifier to have an offset problem, seriously affecting the performance of the memory.

[0003] Therefore, there is an urgent need to improve the sense amplifier. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a sense amplifier and an operating method thereof, and a memory.

[0005] In a first aspect, an embodiment of the present disclosure provides a sense amplifier, the sense amplifier comprising: a sense amplifier circuit, comprising a first node, a second node, a third node and a fourth node, configured to perform signal amplification processing on the first node and the second node when the sense amplifier is in an amplification phase; an offset cancellation circuit, coupled to the first node and the second node, configured to perform offset cancellation processing on the sense amplifier when the sense amplifier is in an offset cancellation phase; a first control circuit, coupled to the third node, configured to control a connection state between the third node and a first voltage node in response to a first control signal when the sense amplifier is in the offset cancellation phase, and to control a current in the offset cancellation phase using a current source in the first control circuit when the third node is coupled to the first voltage node; a second control circuit, coupled to the fourth node, configured to control a connection state between the fourth node and the second voltage node in response to a second control signal when the sense amplifier is in the offset cancellation phase; wherein the voltage of the first voltage node is less than the voltage of the second voltage node.

[0006] In some embodiments, the first control circuit includes a first switch tube and the current source coupled to each other, and is configured to, when the sensing amplifier is in the offset cancellation stage, couple the third node to the first voltage node and use the current source to control the current in the offset cancellation stage according to the first switch tube being in the on state; and not couple the third node to the first voltage node according to the first switch tube being in the off state.

[0007] In some embodiments, the second control circuit includes a second switch tube, which is configured to couple the fourth node to the second voltage node according to the second switch tube being in an on state when the sense amplifier is in the offset cancellation stage; and not couple the fourth node to the second voltage node according to the second switch tube being in an off state.

[0008] In some embodiments, the offset elimination phase includes a first sub-phase, a second sub-phase, and a third sub-phase in sequence; in the first sub-phase, the first control circuit is configured to not couple the third node to the first voltage node, and the second control circuit is configured to couple the fourth node to the second voltage node; in the second sub-phase, the first control circuit is configured to couple the third node to the first voltage node, and the second control circuit is configured to couple the fourth node to the second voltage node; in the third sub-phase, the first control circuit is configured to couple the third node to the first voltage node, and the second control circuit is configured to not couple the fourth node to the second voltage node.

[0009] In some embodiments, the sense amplifier further includes: a third control circuit coupled to the third node, configured to control a connection state between the third node and the first voltage node in response to a third control signal when the sense amplifier is in a phase other than the offset cancellation phase.

[0010] In some embodiments, the sensing amplifier circuit includes: a first transistor, a second transistor, a third transistor and a fourth transistor; the first end of the first transistor and the first end of the second transistor are both coupled to the fourth node; the first end of the third transistor and the first end of the fourth transistor are both coupled to the third node; the second end of the first transistor, the control end of the second transistor, the second end of the third transistor and the control end of the fourth transistor are all coupled to the first node; the control end of the first transistor, the second end of the second transistor, the control end of the third transistor and the second end of the fourth transistor are all coupled to the second node; the control end of the third transistor is also coupled to a complementary bit line, and the control end of the fourth transistor is also coupled to a bit line.

[0011] In some embodiments, the offset elimination circuit includes: a fifth transistor and a sixth transistor; the first end of the fifth transistor is coupled to the first node, and the first end of the sixth transistor is coupled to the second node; the second end of the fifth transistor is coupled to the control end of the third transistor, and the second end of the sixth transistor is coupled to the control end of the fourth transistor; the control end of the fifth transistor and the control end of the sixth transistor both receive a debiasing control signal.

[0012] In some embodiments, the current source includes at least one of a basic current mirror structure, a Wilson current mirror structure, a basic cascode current mirror structure, a low-voltage cascode current mirror structure, and a self-biased cascode current mirror structure.

[0013] In a second aspect, an embodiment of the present disclosure provides a memory, wherein the memory includes the sense amplifier in the above technical solution.

[0014] In a third aspect, an embodiment of the present disclosure provides an operating method of a sense amplifier, and the operating method is applied to the sense amplifier in the above technical solution; the offset elimination stage includes a first sub-stage, a second sub-stage and a third sub-stage in sequence; the operating method includes: in the first sub-stage, the first control circuit does not couple the third node to the first voltage node, the second control circuit couples the fourth node to the second voltage node, and pre-charges the bit line and the complementary bit line coupled to the sense amplifier circuit; in the second sub-stage, the first control circuit couples the third node to the first voltage node, the second control circuit couples the fourth node to the second voltage node, and amplifies the voltage difference between the bit line and the complementary bit line; in the third sub-stage, the first control circuit couples the third node to the first voltage node, the second control circuit does not couple the fourth node to the second voltage node, and discharges the bit line and the complementary bit line.

[0015] The embodiment of the present disclosure provides a sense amplifier and an operation method thereof, and a memory. In the embodiment of the present disclosure, by using a first control circuit connected in series between a third node and a first voltage node of a sense amplifier circuit, when the sense amplifier is in an offset cancellation stage, a current source can control the current of the sense amplifier in the offset cancellation stage, thereby simultaneously reducing the error in the offset cancellation stage (i.e., improving the accuracy of the offset cancellation stage) and controlling the balance of the sense amplifier sensing 0 and 1. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of a sense amplifier provided in an embodiment of the present disclosure Figure 1 ;

[0017] Figure 2 Schematic diagram of a sense amplifier provided in an embodiment of the present disclosure Figure 2 ;

[0018] Figure 3 (a) is a basic current mirror structure; (b) is a Wilson current mirror structure; (c) is a basic cascode current mirror structure; (d) is a low-voltage cascode current mirror structure; (e) is a self-biased cascode current mirror structure;

[0019] Figure 4 A flowchart of an operating method of a sense amplifier is provided for an embodiment of the present disclosure;

[0020] FIG. 5A to FIG. 5C A schematic diagram of the connection relationship of the sense amplifier provided by the embodiment of the present disclosure in the offset cancellation stage;

[0021] Figure 6 A voltage timing diagram of a sense amplifier in an offset cancellation phase provided by an embodiment of the present disclosure;

[0022] Fig. 7A A simulation diagram of a sense amplifier provided for some embodiments;

[0023] Figure 7B A schematic diagram of a sense amplifier sensing 0 and 1 provided for some embodiments;

[0024] Figure 8 A simulation diagram of a sense amplifier provided in an embodiment of the present disclosure;

[0025] Fig. 9 A schematic diagram of a memory provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0027] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0028] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0029] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0030] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0031] Those skilled in the art will appreciate that the terms "offset" and "offset" have the same meaning, both referring to deviations caused by differences in transistors.

[0032] A memory, such as a dynamic random access memory (DRAM), may include a sense amplifier. Due to differences in process technology and the influence of the working environment, the size and threshold voltage of each transistor in the sense amplifier may be different, and the performance of each transistor is usually not exactly the same, which will cause the sense amplifier to have an offset problem, seriously affecting the performance of the memory.

[0033] For example, due to the difference in performance of each transistor in the sense amplifier, the sense amplifier may have an offset problem. At this time, if no processing is performed, when a read operation is performed from a storage unit in the memory, the originally stored 1 may be read as 0 and then outputted incorrectly, or the originally stored 0 may be read as 1 and then outputted incorrectly.

[0034] In view of this, embodiments of the present disclosure provide a sense amplifier and an operating method thereof, and a memory.

[0035] refer to Figure 1 , Figure 1 Schematic diagram of a sense amplifier provided in an embodiment of the present disclosure Figure 1 .like Figure 1As shown, the embodiment of the present disclosure provides a sense amplifier 100, which includes: a sense amplifier circuit 110, including a first node, a second node, a third node and a fourth node, configured to perform signal amplification processing on the first node and the second node when the sense amplifier 100 is in an amplification phase; an offset cancellation circuit 120, coupled to the first node and the second node, configured to perform offset cancellation (Offset Cancellation, OC) processing on the sense amplifier 100 when the sense amplifier 100 is in an offset cancellation phase; a first control circuit 130, coupled to To the third node, it is configured to control the connection state between the third node and the first voltage node in response to the first control signal when the sensing amplifier 100 is in the offset cancellation stage, and to control the current in the offset cancellation stage using the current source 132 in the first control circuit 130 when the third node is coupled to the first voltage node; the second control circuit 140 is coupled to the fourth node, and is configured to control the connection state between the fourth node and the second voltage node in response to the second control signal when the sensing amplifier 100 is in the offset cancellation stage; wherein the voltage of the first voltage node is less than the voltage of the second voltage node.

[0036] Here, the first control circuit 130 is configured to couple the third node to the first voltage node and control the current in the offset cancellation stage using the current source 132; or, the third node is not coupled to the first voltage node. In other words, the first control circuit 130 is used to control whether the third node of the sense amplifier circuit 110 is connected to the first voltage node, and when the third node of the sense amplifier circuit 110 is coupled to the first voltage node, the current in the offset cancellation stage is also controlled using the current source 132 in the first control circuit 130.

[0037] Here, the second control circuit 140 is configured to couple the fourth node to the second voltage node; or, not couple the fourth node to the second voltage node. In other words, the second control circuit 140 is used to control whether the fourth node of the sense amplifier circuit 110 is connected to the second voltage node.

[0038] refer to Figure 2 , Figure 2 Schematic diagram of a sense amplifier provided in an embodiment of the present disclosure Figure 2 .like Figure 2 As shown, in some embodiments, the first control circuit 130 includes a first switch tube 131 and a current source 132 coupled to each other, and is configured to, when the sensing amplifier 100 is in the offset cancellation stage, couple the third node SN to the first voltage node and use the current source 132 to control the current in the offset cancellation stage according to the first switch tube 131 being in the on state; and not couple the third node SN to the first voltage node according to the first switch tube 131 being in the off state.

[0039] Here, the first control circuit 130 includes a first switch tube 131 and a current source 132 connected in series. The first end of the first switch tube 131 is coupled to the first voltage node, the second end of the first switch tube 131 is coupled to the current source 132, and the control end of the first switch tube 131 receives a first control signal. When the sense amplifier is in the offset elimination stage, when the first switch tube 131 is in the on state, the first end of the first switch tube 131 is coupled to the first voltage node, and the current source 132 can provide a stable current for the sense amplifier circuit; when the first switch tube 131 is in the off state, the first end of the first switch tube 131 is not coupled to the first voltage node.

[0040] Here, the first switch tube 131 may include an N-type metal oxide semiconductor field effect transistor (NMOS tube). The first end may be a source (Source, S) of the first switch tube 131, the second end may be a drain (Drain, D) of the first switch tube 131, and the control end may be a gate (Gate, G) of the first switch tube 131.

[0041] Here, the voltage of the first voltage node may include a ground voltage (VSS).

[0042] refer to Figure 3 , Figure 3 Five different structures of the current source 132 are shown for exemplary description. Figure 3 Figure (a) shows a basic current mirror structure. When the channel modulation effect is ignored, the ratio of the output current Iout to the reference current Iref is only related to the width-to-length ratio of the transistors M1 and M2. By adjusting the width-to-length ratio of the transistors M1 and M2, current replication can be achieved. Figure 3 Figure (b) shows a Wilson current mirror structure. The ratio of the output current Iout to the reference current Iref is not only related to the width-to-length ratio of transistors M1 and M2, but also to the voltage between the gate and source of transistor M2 (Vgs2) and the voltage between the gate and source of transistor M3 (Vgs3). Figure 3 Figure (c) shows a basic cascode current mirror structure, including transistors M1, M2 and M3. The cascode current mirror eliminates the current error caused by the channel modulation effect and can obtain a more accurate current ratio (i.e., output current Iout / reference current Iref). Figure 3 The basic cascode current mirror structure shown in Figure (c) is Figure 3The low voltage common source and common gate current mirror structure shown in the middle (d) includes transistors M1, M2, M3 and M4, and has a larger output impedance, a stable output current and a larger output voltage swing; Figure 3 The self-biased cascode current mirror structure shown in Figure (e) includes transistors M1, M2, M3 and M4, and a resistor R is connected in series at the input end of the circuit to increase the range of the input current.

[0043] In the embodiment of the present disclosure, a first control circuit is connected in series between the third node and the first voltage node of the sensing amplifier circuit. When the sensing amplifier is in the offset cancellation stage, when the first switch tube is in the on state, the current source can provide a stable current for the sensing amplifier circuit, thereby controlling the current of the sensing amplifier when it is in the offset cancellation stage, thereby simultaneously reducing the error in the offset cancellation stage (i.e., improving the accuracy of the offset cancellation stage) and controlling the balance of the sensing amplifier sensing 0 and 1.

[0044] Still Figure 2 As shown, in some embodiments, the second control circuit 140 includes a second switch tube 141, which is configured to couple the fourth node SP to the second voltage node according to the second switch tube 141 being in the on state; and not couple the fourth node SP to the second voltage node according to the second switch tube 141 being in the off state.

[0045] Here, the second control circuit 140 includes a second switch tube 141, a first end of the second switch tube 141 is coupled to the fourth node SP, a second end of the second switch tube 141 is coupled to the second voltage node, and a control end of the second switch tube 141 receives a second control signal. When the second switch tube 141 is in the on state, the second end of the second switch tube 141 is coupled to the second voltage node; when the second switch tube 141 is in the off state, the second end of the second switch tube 141 is not coupled to the second voltage node.

[0046] Here, the second switch tube 141 may include an NMOS tube. The first end may be a source of the second switch tube 141 , the second end may be a drain of the second switch tube 141 , and the control end may be a gate of the second switch tube 141 .

[0047] In some other embodiments, the second switch tube 141 may also include a P-type metal oxide semiconductor field effect transistor (Positive channel Metal Oxide Semiconductor field effect transistor, PMOS tube). The first end of the PMOS tube is coupled to the second voltage node, the second end of the PMOS tube is coupled to the fourth node SP, and the control end of the PMOS tube receives the second control signal. Here, the first end may be the source of the PMOS tube, the second end may be the drain of the PMOS tube, and the control end may be the gate of the PMOS tube.

[0048] Here, the voltage of the second voltage node may include a power supply voltage (VDD).

[0049] In some embodiments, the sense amplifier 100 further includes: a third control circuit coupled to the third node, configured to control the connection state of the third node and the first voltage node in response to a third control signal when the sense amplifier is in a phase other than the offset cancellation phase.

[0050] Here, the third control circuit may include a third switch tube, a first end of the third switch tube is coupled to the first voltage node, a second end of the third switch tube is coupled to the third node, and a control end of the third switch tube receives a third control signal. When the sense amplifier is in a stage other than the offset elimination stage, when the third switch tube is in the on state, the first end of the third switch tube is coupled to the first voltage node; when the third switch tube is in the off state, the first end of the third switch tube is not coupled to the first voltage node.

[0051] In the embodiment of the present disclosure, the first control circuit and the third control circuit are both coupled to the third node. When the sense amplifier is in the offset cancellation stage, the first control circuit is used to realize that the third node of the sense amplifier circuit is coupled to the first voltage node, and when the sense amplifier is in other stages except the offset cancellation stage, the third control circuit is used to realize that the third node of the sense amplifier circuit is coupled to the first voltage node. The first control circuit and the third control circuit are used to control the connection relationship between the third node and the first voltage node in the offset cancellation stage and in other stages except the offset cancellation stage, respectively, which helps to meet the requirements of the sense amplifier in different stages.

[0052] like Figure 2As shown, in some embodiments, the sensing amplifier circuit 110 includes: a first transistor 111, a second transistor 112, a third transistor 113 and a fourth transistor 114; the first end of the first transistor 111 and the first end of the second transistor 112 are both coupled to the fourth node SP; the first end of the third transistor 113 and the first end of the fourth transistor 114 are both coupled to the third node SN; the second end of the first transistor 111, the control end of the second transistor 112, the second end of the third transistor 113 and the control end of the fourth transistor 114 are all coupled to the first node saa; the control end of the first transistor 111, the second end of the second transistor 112, the control end of the third transistor 113 and the second end of the fourth transistor 114 are all coupled to the second node sab; the control end of the third transistor 113 is also coupled to the complementary bit line bl_n, and the control end of the fourth transistor 114 is also coupled to the bit line bl.

[0053] like Figure 2 As shown, in some embodiments, the sensing amplifier circuit 110 also includes: a seventh transistor 115 and an eighth transistor 116; the first end of the seventh transistor 115 is coupled to the first node saa, and the second end of the seventh transistor 115 is coupled to the control end of the fourth transistor 114; the first end of the eighth transistor 116 is coupled to the second node sab, and the second end of the eighth transistor 116 is coupled to the control end of the third transistor 113; the control end of the seventh transistor 115 and the control end of the eighth transistor 116 both receive the amplification control signal blsb.

[0054] Here, the first transistor 111, the second transistor 112, the third transistor 113 and the fourth transistor 114 form a cross-coupling circuit. The control terminals of the seventh transistor 115 and the eighth transistor 116 both receive the amplification control signal blsb. When the seventh transistor 115 and the eighth transistor 116 are in the on state, the seventh transistor 115 and the eighth transistor 116 can be used as transmission gates. In this way, the cross-coupling circuit (including the first transistor 111, the second transistor 112, the third transistor 113 and the fourth transistor 114), the seventh transistor 115 and the eighth transistor 116 form an inverter latch structure connected head to tail, which is used to amplify the signal when the sense amplifier is in the amplification stage.

[0055] Here, the first transistor 111 and the second transistor 112 may include a PMOS tube, the first end may be the source of the PMOS tube, the second end may be the drain of the PMOS tube, and the control end may be the gate of the PMOS tube. The third transistor 113, the fourth transistor 114, the seventh transistor 115, and the eighth transistor 116 may include an NMOS tube, the first end may be the source of the NMOS tube, the second end may be the drain of the NMOS tube, and the control end may be the gate of the NMOS tube.

[0056] like Figure 2 As shown, in some embodiments, the offset elimination circuit 120 includes a fifth transistor 121 and a sixth transistor 122; the first end of the fifth transistor 121 is coupled to the first node saa, and the first end of the sixth transistor 122 is coupled to the second node sab; the second end of the fifth transistor 121 is coupled to the control end of the third transistor 113, and the second end of the sixth transistor 122 is coupled to the control end of the fourth transistor 114; the control end of the fifth transistor 121 and the control end of the sixth transistor 122 both receive the debiasing control signal blsa.

[0057] Here, the control ends of the fifth transistor 121 and the sixth transistor 122 both receive the debiasing control signal blsa. When the fifth transistor 121 and the sixth transistor 122 are both in the on state, when the sensing amplifier 100 is in the offset elimination stage, the sensing amplifier 100 can be subjected to offset elimination processing.

[0058] Here, the fifth transistor 121 and the sixth transistor 122 may include NMOS transistors, the first end may be a source of the NMOS transistor, the second end may be a drain of the NMOS transistor, and the control end may be a gate of the NMOS transistor.

[0059] like Figure 2 As shown, in some embodiments, the sense amplifier further includes a pre-charge circuit, and the pre-charge circuit includes a first pre-charge transistor 151 and a second pre-charge transistor 152 . Figure 2 Where bleq represents the precharge control signal, vblp represents the precharge source signal, and the voltage value of the precharge source signal vblp is the precharge voltage. The first precharge transistor 151 is connected in series between the first node saa and the precharge source signal vblp, and the second precharge transistor 152 is connected in series between the second node sab and the precharge source signal vblp. The control ends of the first precharge transistor 151 and the second precharge transistor 152 both receive the precharge control signal bleq. When the first precharge transistor 151 and the second precharge transistor 152 are both in the on state, when the sense amplifier 100 is in the precharge stage, the first node saa and the second node sab are precharged.

[0060] like Figure 2 As shown, in some embodiments, the sense amplifier further includes a signal transmission circuit, and the signal transmission circuit includes a first transmission transistor 161 and a second transmission transistor 162 . Figure 2Where Isae represents a transmission control signal, Idl represents a target transmission node, Idl_n represents a target complementary transmission node, a first transmission transistor 161 is connected in series between the target complementary transmission node Idl_n and the control end of the third transistor 113, and a second transmission transistor 162 is connected in series between the target transmission node Idl and the control end of the fourth transistor 114. The control ends of the first transmission transistor 161 and the second transmission transistor 162 both receive the transmission control signal Isae, and when the first transmission transistor 161 and the second transmission transistor 162 are both in the on state, when the sense amplifier 100 is in the signal transmission stage, the amplified signal is transmitted to the target transmission node Idl and the target complementary transmission node Idl_n.

[0061] refer to Figure 4 , Figure 4 A flow chart of an operation method of a sense amplifier is provided for an embodiment of the present disclosure. Figure 4 As shown, the embodiment of the present disclosure further provides an operating method of a sense amplifier, which is applied to the sense amplifier in the above technical solution; the offset elimination phase includes a first sub-phase, a second sub-phase and a third sub-phase in sequence; the operating method includes:

[0062] Step S410: In the first sub-phase, the first control circuit does not couple the third node to the first voltage node, the second control circuit couples the fourth node to the second voltage node, and performs a pre-charging process on the bit line and the complementary bit line coupled to the sense amplifier circuit;

[0063] Step S420: In the second sub-phase, the first control circuit couples the third node to the first voltage node, and the second control circuit couples the fourth node to the second voltage node, and amplifies the voltage difference between the bit line and the complementary bit line;

[0064] Step S430: In the third sub-phase, the first control circuit couples the third node to the first voltage node, the second control circuit does not couple the fourth node to the second voltage node, and discharges the bit line and the complementary bit line.

[0065] In some embodiments, before step S410, the operation method further includes a pre-charging stage, in which the first pre-charging transistor 151 and the second pre-charging transistor 152 are in a conducting state, and the sense amplifier 100 is pre-charged until the bit line bl and the complementary bit line bl_n are charged to the pre-charging voltage. Exemplarily, the pre-charging voltage may be 0.5VDD.

[0066] In some embodiments, after step S430, the operation method further includes an amplification stage, during which the cross-coupling circuit (including the first transistor 111, the second transistor 112, the third transistor 113 and the fourth transistor 114), the seventh transistor 115 and the eighth transistor 116 in the sensing amplifier circuit 110 are all in an on state, and the voltage difference between the bit line bl and the complementary bit line bl_n is amplified.

[0067] At this time, the sense amplifier 100 is in the amplification stage, not in the offset cancellation stage, so the fifth transistor 121 and the sixth transistor 122 in the offset cancellation circuit 120 are both in the off state. At this time, the sense amplifier 100 is not in the pre-charge stage either, so the first pre-charge transistor 151 and the second pre-charge transistor 152 in the pre-charge circuit are both in the off state. At this time, the sense amplifier 100 is not in the signal transmission stage either, so the first transmission transistor 161 and the second transmission transistor 162 in the signal transmission circuit are both in the off state.

[0068] In some embodiments, after the amplification stage, the operation method also includes a signal transmission stage, in which each transistor in the sensing amplifier circuit 110 and the first transmission transistor 161 and the second transmission transistor 162 in the signal transmission circuit are in an on state, and the amplified signal is transmitted to the target transmission node Idl and the target complementary transmission node Idl_n.

[0069] At this time, the sense amplifier 100 is in the signal transmission stage, but not in the offset cancellation stage, so the fifth transistor 121 and the sixth transistor 122 in the offset cancellation circuit 120 are both in the off state. At this time, the sense amplifier 100 is also not in the pre-charging stage, so the first pre-charging transistor 151 and the second pre-charging transistor 152 in the pre-charging circuit are both in the off state.

[0070] refer to FIG. 5A to FIG. 5C , FIG. 5A to FIG. 5C A schematic diagram of the connection relationship of the sense amplifier provided by an embodiment of the present disclosure in the offset cancellation stage. Figure 5A , Figure 5B and Figure 5C The circuit connection diagrams of the sense amplifier in the first sub-stage, the second sub-stage and the third sub-stage of the offset cancellation stage are respectively illustrated. FIG. 5A to FIG. 5C In the figure, the paths formed when each transistor is turned on are indicated by solid lines, and the disconnected paths formed when each transistor is turned off are indicated by dotted lines. Figure 6 The voltage timing diagram of the sense amplifier in the offset cancellation stage provided by the embodiment of the present disclosure will be combined with Figure 4 , FIG. 5A to FIG. 5C as well as Figure 6, the offset cancellation stage of the sense amplifier is described in detail.

[0071] In the embodiment of the present disclosure, in step S410, in the first sub-stage, the first control circuit does not couple the third node to the first voltage node, and the second control circuit couples the fourth node to the second voltage node, and pre-charges the bit line and the complementary bit line coupled to the sensing amplifier circuit.

[0072] like Figure 5A As shown, in the first sub-phase, the first switch tube 131 in the first control circuit 130 does not couple the third node SN to the ground voltage VSS, and the second switch tube 141 in the second control circuit 140 couples the fourth node SP to the power supply voltage VDD. Figure 5A The schematically illustrated sense amplifier 100 is in the first sub-stage of the offset cancellation stage, but not in the amplification stage. Therefore, the fifth transistor 121 and the sixth transistor 122 in the offset cancellation circuit 120 are both in the on state, and the seventh transistor 115 and the eighth transistor 116 in the sense amplifier circuit 110 are both in the off state.

[0073] Here, in the first sub-stage, the bit line bl and the complementary bit line bl_n are precharged. It should be noted that before the offset elimination stage, the sense amplifier 100 has undergone a precharge stage, and the bit line bl and the complementary bit line bl_n are precharged to a precharge voltage. The voltage of the bit line bl and the complementary bit line bl_n at the end of the precharge stage can be defined as a first precharge voltage, and the voltage of the bit line bl and the complementary bit line bl_n at the end of the first sub-stage in the offset elimination stage can be defined as a second precharge voltage; wherein the second precharge voltage is greater than the first precharge voltage.

[0074] Exemplarily, at the end of the precharge phase, the voltage of the bit line bl and the complementary bit line bl_n may be 0.5VDD, and at the end of the first sub-phase, the voltage of the bit line bl and the complementary bit line bl_n may be 0.8VDD.

[0075] Combination Figure 5A and Figure 6 As shown, in the first sub-stage, the second switch tube 141 is in the on state; the first switch tube 131 is in the off state; the bit line bl and the complementary bit line bl_n are precharged, and the voltages of the bit line bl and the complementary bit line bl_n are increased. At this time, the voltage difference ΔVbl between the bit line bl and the complementary bit line bl_n approaches zero.

[0076] It should be noted that the third transistor 113, the fourth transistor 114, and the fifth transistor 121 and the sixth transistor 122 in the offset elimination circuit 120 are diode-connected, and the offset elimination stage is mainly used to eliminate the threshold voltage difference between the third transistor 113 and the fourth transistor 114. Therefore, the error in the offset elimination stage is mainly caused by the threshold voltage difference between the first transistor 111 and the second transistor 112.

[0077] Further analysis shows that the longer the duration of the first sub-stage is, the greater the voltage of the bit line bl and the complementary bit line bl_n is at the end of the first sub-stage, and thus the greater the voltage of the bit line bl and the complementary bit line bl_n is at the end of the offset elimination stage. However, the longer the duration of the first sub-stage is, the greater the gain of the first transistor 111 and the second transistor 112 is, and the greater the error in the offset elimination stage is.

[0078] In the embodiment of the present disclosure, in step S420, in the second sub-stage, the first control circuit couples the third node to the first voltage node, and the second control circuit couples the fourth node to the second voltage node, and amplifies the voltage difference between the bit line and the complementary bit line.

[0079] like Figure 5B As shown, in the second sub-phase, the first switch tube 131 in the first control circuit 130 couples the third node SN to the ground voltage VSS, and the second switch tube 141 in the second control circuit 140 couples the fourth node SP to the power supply voltage VDD. Figure 5B The schematically illustrated sense amplifier 100 is in the offset cancellation stage, not in the amplification stage, therefore, the fifth transistor 121 and the sixth transistor 122 in the offset cancellation circuit 120 are both in the on state, and the seventh transistor 115 and the eighth transistor 116 in the sense amplifier circuit 110 are both in the off state.

[0080] Here, in the second sub-stage, the voltage difference ΔVbl between the bit line bl and the complementary bit line bl_n is amplified. At the same time, the threshold voltage difference of the NMOS transistor (i.e., the third transistor 113 and the fourth transistor 114) and the threshold voltage difference of the PMOS transistor (i.e., the first transistor 111 and the second transistor 112) are amplified, and the voltage difference ΔVbl between the bit line bl and the complementary bit line bl_n increases rapidly.

[0081] Combination Figure 5B and Figure 6 As shown, in the second sub-stage, the first switch tube 131 and the second switch tube 141 are both in the on state; the voltages of the bit line bl and the complementary bit line bl_n are both reduced, and the reduction rates of the voltages of the bit line bl and the complementary bit line bl_n are different, therefore, the voltage difference ΔVbl between the bit line bl and the complementary bit line bl_n increases rapidly.

[0082] Further analysis shows that the longer the duration of the second sub-stage is, the smaller the voltage of the bit line bl and the complementary bit line bl_n is at the end of the second sub-stage, and the smaller the voltage of the bit line bl and the complementary bit line bl_n is at the end of the offset elimination stage. The longer the duration of the second sub-stage is, the larger the voltage difference ΔVbl between the bit line bl and the complementary bit line bl_n is, the larger the calibration range of the offset elimination stage is, the smaller the voltage of the bit line bl and the complementary bit line bl_n is at the end of the offset elimination stage, and the smaller the error of the offset elimination stage is (that is, the accuracy of the offset elimination stage is higher).

[0083] In the disclosed embodiment, in step S430, in the third sub-stage, the first control circuit couples the third node to the first voltage node, and the second control circuit does not couple the fourth node to the second voltage node, and discharges the bit line and the complementary bit line.

[0084] like Figure 5C As shown, in the third sub-phase, the first switch tube 131 in the first control circuit 130 couples the third node SN to the ground voltage VSS, and the second switch tube 141 in the second control circuit 140 does not couple the fourth node SP to the power supply voltage VDD. Figure 5B The schematically illustrated sense amplifier 100 is in the offset cancellation stage, not in the amplification stage, therefore, the fifth transistor 121 and the sixth transistor 122 in the offset cancellation circuit 120 are both in the on state, and the seventh transistor 115 and the eighth transistor 116 in the sense amplifier circuit 110 are both in the off state.

[0085] Here, in the third sub-stage, the bit line bl and the complementary bit line bl_n are discharged. The PMOS tube (i.e., the first transistor 111 and the second transistor 112) are both in the off state, the influence of the threshold voltage difference between the first transistor 111 and the second transistor 112 is eliminated, and the end point of the discharge process is the threshold voltage of the NMOS tube.

[0086] Combination Figure 5C and Figure 6 As shown, in the third sub-stage, the second switch tube 141 is in the off state; the first switch tube 131 is in the on state; the voltages of the bit line bl and the complementary bit line bl_n both decrease, and the voltage difference ΔVbl between the bit line bl and the complementary bit line bl_n slowly increases.

[0087] Further analysis shows that the longer the duration of the third sub-stage is, the smaller the voltage of the bit line bl and the complementary bit line bl_n is at the end of the third sub-stage. The longer the duration of the third sub-stage is, the more thoroughly the influence of the threshold voltage difference of the PMOS tube is eliminated, and the smaller the voltage of the bit line bl and the complementary bit line bl_n is at the end of the offset elimination stage, the smaller the error in the offset elimination stage is (that is, the higher the accuracy of the offset elimination stage is).

[0088] refer to Fig. 7A , Fig. 7A A simulation diagram of a sense amplifier provided in some embodiments. The sense amplifier corresponding to the simulation diagram does not use a current source to control the current in the offset cancellation stage in the offset cancellation stage. Fig. 7A As shown, the horizontal axis is the threshold voltage difference between the NMOS tubes in the cross-coupled circuit (ΔVth of nsa pair), and the unit is volt (V); the vertical axis is the difference between the voltage difference ΔVbl and ΔVth between the bit line bl and the complementary bit line bl_n, that is, (ΔVbl-ΔVth), and the unit is volt (V). Fig. 7A The distribution range of the vertical coordinate value is shown to be -0.03 to 0.04. Therefore, at the end of the offset cancellation stage of the sense amplifier, there is still a certain error in the offset cancellation stage, and the accuracy of the offset cancellation stage needs to be further improved.

[0089] refer to Figure 7B , Figure 7B A schematic diagram of a sense amplifier sensing 0 and 1 is provided for some embodiments. Figure 7B As shown, the horizontal axis is the common mode voltage (Vcommon); the vertical axis is the sensing margin. Figure 7B It is shown that the sense0 curve represents the sensing tolerance change curve of the sense amplifier sense0, and the sense1 curve represents the sensing tolerance change curve of the sense amplifier sense1. The absolute value of the slope of the sense0 curve is the same as the absolute value of the slope of the sense1 curve, indicating that as the common mode voltage changes, the sum of the sensing tolerance value in the sense0 curve and the sensing tolerance value in the sense1 curve (i.e., the total sensing margin) remains unchanged. Usually, the sensing margin depends on the smaller value between the sense0 sensing tolerance value and the sense1 sensing tolerance value. As the common mode voltage changes, the sensing tolerance value in the sense0 curve tends to increase, and the sensing tolerance value in the sense1 curve tends to decrease. When the sense0 curve and the sense1 curve intersect, that is, when the sense0 sensing tolerance value = the sense1 sensing tolerance value, the optimal state of sense0 and sense1 is reached, and the balance of sense0 and sense1 is achieved. At this time, the optimal value of the common mode voltage = 0.5VDD.

[0090] refer to Figure 8 , Figure 8 This is a simulation diagram of a sensing amplifier provided in an embodiment of the present disclosure. The sensing amplifier corresponding to the simulation diagram uses a current source to control the current in the offset cancellation stage during the offset cancellation stage. Figure 8 As shown, the horizontal axis is the threshold voltage difference between the NMOS tubes in the cross-coupled circuit (ΔVth of nsa pair), and the unit is volt (V); the vertical axis is the difference between the voltage difference ΔVbl and ΔVth between the bit line bl and the complementary bit line bl_n, that is, (ΔVbl-ΔVth), and the unit is volt (V). Figure 8 The distribution range of the ordinate values ​​shown is -0.02 to 0.02. It should be noted that the closer the distribution of the ordinate values ​​in the simulation diagram is to 0, the smaller the error in the offset cancellation stage in the sense amplifier. Fig. 7A The common mode voltage is 454mV, and the power supply voltage VDD is 1.05V; Figure 8 The common-mode voltage is 487mV, which means that using a current source to control the current in the offset cancellation stage can not only reduce the error in the offset cancellation stage, but also make the common-mode voltage closer to the common-mode voltage when sense0 and sense1 are balanced, which is beneficial to controlling the balance of sense 0 and sense 1.

[0091] Comparative Analysis Fig. 7A and Figure 8 , using a current source in the offset cancellation stage can control the balance of sensing 0 and 1 while reducing the error in the offset cancellation stage.

[0092] The inventors of the present disclosure have found that if only a switch tube is connected in series between the third node SN and the first voltage node, many problems will occur in the offset elimination stage of the sense amplifier. On the one hand, the current Isn of the switch tube is easily affected by the process corner, that is, the current of the switch tube is greatly affected by the process voltage temperature (PVT). Therefore, the current Isn of the switch tube is unstable, and it is easy to have different offset elimination states at different process corners. For example, the offset elimination is insufficient at some process corners, or the offset elimination is excessive at other process corners. On the other hand, the voltage Vsn of the third node SN is also easily affected by the process corner. The switch tube works in the linear region, and the voltage Vsn of the third node SN is low, which is prone to a low common-mode voltage, usually lower than the optimal value of the common-mode voltage, which is not conducive to controlling the balance of the sense amplifier sensing 0 and 1. On the third aspect, the current Isn of the switch tube determines the voltage (Vgs) between the gate and source of the NMOS tube coupled to the third node SN. Therefore, the instability of the current Isn of the switch tube will also cause the voltage (Vgs) between the gate and source of the NMOS tube to be unstable. The bit line voltage Vbl is the sum of the voltage (Vgs) between the gate and source of the NMOS tube and the voltage Vsn of the third node SN. In order to improve the accuracy of the offset elimination stage, it is necessary to extend the duration of the second sub-stage and the third sub-stage in the offset elimination stage. While improving the accuracy of the offset elimination stage, it is inevitable to sacrifice the balance of the sense amplifier sensing 0 and 1. In summary, the inventors of the present disclosure have found that it is difficult to balance the improvement of the accuracy of the offset elimination stage and the improvement of the balance of the sense amplifier sensing 0 and 1 in the offset elimination stage of the sense amplifier. More specifically, in order to improve the accuracy of the offset elimination stage, it is necessary to extend the duration of the second sub-stage and the third sub-stage in the offset elimination stage. However, in the process of extending the duration of the offset elimination stage, it is easy to have a low common mode voltage, and it is difficult to improve the balance of the sense amplifier sensing 0 and 1. In other words, in order to improve the balance of the sensing amplifier sensing 0 and 1, it is necessary to shorten the duration of the offset cancellation phase. However, shortening the duration of the offset cancellation phase will lead to a larger error in the offset cancellation phase, making it difficult to improve the accuracy of the offset cancellation phase.

[0093] In the disclosed embodiment, a first switch tube and a current source connected in series are provided between the third node SN and the first voltage node. In this way, on the first hand, the current Isn of the first switch tube is relatively stable, will not be affected by PVT, and can maintain a consistent offset elimination state under various process angles. On the second hand, the current source operates in the saturation region, and the voltage Vsn of the third node SN is usually not too low, which can increase the common mode voltage so that the common mode voltage is closer to the common mode voltage when sense0 and sense1 are balanced. On the third hand, the current Isn of the first switch tube is relatively stable, and the voltage (Vgs) between the gate and the source of the NMOS tube coupled to the third node SN can also reach stability relatively quickly, and the accuracy of the offset elimination stage can be improved without extending the duration of the offset elimination stage. Therefore, the current of the sense amplifier when it is in the offset elimination stage can be controlled, and then the error of the offset elimination stage (that is, the accuracy of the offset elimination) and the balance of the sense amplifier sensing 0 and 1 can be reduced at the same time.

[0094] refer to Fig. 9 , Fig. 9 Schematic diagram of a memory provided by an embodiment of the present disclosure. Fig. 9 As shown, the embodiment of the present disclosure further provides a memory 200, which includes the sense amplifier 100 in the above technical solution.

[0095] Here, the memory 200 may include a static random access memory (SRAM), a DRAM, a synchronous dynamic random access memory (SDRAM), or a double data rate SDRAM (DDR SDRAM), etc., and the present disclosure does not make any specific limitation on this.

[0096] Here, the memory 200 may include a DRAM chip. The DRAM chip may not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, but may also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6, and the present disclosure does not specifically limit this.

[0097] The embodiment of the present disclosure provides a sense amplifier and an operation method thereof, and a memory. The sense amplifier includes: a sense amplifier circuit, including a first node, a second node, a third node, and a fourth node, configured to perform signal amplification processing on the first node and the second node when the sense amplifier is in an amplification phase; an offset elimination circuit, coupled to the first node and the second node, configured to perform offset elimination processing on the sense amplifier when the sense amplifier is in an offset elimination phase; a first control circuit, coupled to the third node, configured to control the connection state between the third node and the first voltage node in response to a first control signal when the sense amplifier is in an offset elimination phase, and to control the current in the offset elimination phase using a current source in the first control circuit when the third node is coupled to the first voltage node; a second control circuit, coupled to the fourth node, configured to control the connection state between the fourth node and the second voltage node in response to a second control signal when the sense amplifier is in an offset elimination phase; wherein the voltage of the first voltage node is less than the voltage of the second voltage node. In the embodiment of the present disclosure, by utilizing a first control circuit connected in series between a third node and a first voltage node of a sensing amplifier circuit, when the sensing amplifier is in an offset cancellation stage, a current source can control the current of the sensing amplifier when it is in an offset cancellation stage, thereby simultaneously reducing the error of the offset cancellation stage (i.e., improving the accuracy of the offset cancellation stage) and controlling the balance of the sensing amplifier sensing 0 and 1.

[0098] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0099] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A sense amplifier, characterized in that: The sense amplifier comprises: A sense amplifier circuit, comprising a first node, a second node, a third node and a fourth node, configured to perform signal amplification processing on the first node and the second node when the sense amplifier is in an amplification phase; an offset cancellation circuit, coupled to the first node and the second node, configured to perform an offset cancellation process on the sense amplifier when the sense amplifier is in an offset cancellation phase; a first control circuit coupled to the third node and configured to control a connection state between the third node and a first voltage node in response to a first control signal when the sense amplifier is in the offset cancellation phase, and to control a current in the offset cancellation phase using a current source in the first control circuit when the third node is coupled to the first voltage node; A second control circuit is coupled to the fourth node and is configured to control a connection state between the fourth node and a second voltage node in response to a second control signal when the sense amplifier is in the offset cancellation phase; wherein the voltage of the first voltage node is less than the voltage of the second voltage node.

2. The sense amplifier according to claim 1, wherein: The first control circuit includes a first switch tube and the current source coupled to each other, and is configured to couple the third node to the first voltage node and use the current source to control the current in the offset cancellation stage when the sense amplifier is in the offset cancellation stage according to the first switch tube being in the on state; And according to the first switch tube being in the off state, the third node is not coupled to the first voltage node.

3. The sense amplifier according to claim 1, wherein: The second control circuit includes a second switch tube, configured to couple the fourth node to the second voltage node according to the second switch tube being in a conducting state when the sense amplifier is in the offset cancellation phase; And according to the second switch tube being in the off state, the fourth node is not coupled to the second voltage node.

4. The sense amplifier according to any one of claims 1 to 3, characterized in that: The offset elimination phase includes a first sub-phase, a second sub-phase and a third sub-phase in sequence; In the first sub-phase, the first control circuit is configured not to couple the third node to the first voltage node, and the second control circuit is configured to couple the fourth node to the second voltage node; In the second sub-phase, the first control circuit is configured to couple the third node to the first voltage node, and the second control circuit is configured to couple the fourth node to the second voltage node; In the third sub-phase, the first control circuit is configured to couple the third node to the first voltage node, and the second control circuit is configured not to couple the fourth node to the second voltage node.

5. The sense amplifier according to claim 1, wherein: The sense amplifier further comprises: The third control circuit is coupled to the third node and is configured to control a connection state between the third node and the first voltage node in response to a third control signal when the sense amplifier is in a phase other than the offset cancellation phase.

6. The sense amplifier according to claim 1, wherein: The sensing amplifier circuit includes: a first transistor, a second transistor, a third transistor and a fourth transistor; The first terminal of the first transistor and the first terminal of the second transistor are both coupled to the fourth node; The first terminal of the third transistor and the first terminal of the fourth transistor are both coupled to the third node; The second terminal of the first transistor, the control terminal of the second transistor, the second terminal of the third transistor and the control terminal of the fourth transistor are all coupled to the first node; The control terminal of the first transistor, the second terminal of the second transistor, the control terminal of the third transistor and the second terminal of the fourth transistor are all coupled to the second node; The control terminal of the third transistor is also coupled to a complementary bit line, and the control terminal of the fourth transistor is also coupled to a bit line.

7. The sense amplifier according to claim 6, wherein: The offset cancellation circuit includes: a fifth transistor and a sixth transistor; A first terminal of the fifth transistor is coupled to the first node, and a first terminal of the sixth transistor is coupled to the second node; The second end of the fifth transistor is coupled to the control end of the third transistor, and the second end of the sixth transistor is coupled to the control end of the fourth transistor; The control end of the fifth transistor and the control end of the sixth transistor both receive a debiasing control signal.

8. The sense amplifier according to claim 1, wherein: The current source includes at least one of a basic current mirror structure, a Wilson current mirror structure, a basic cascode current mirror structure, a low-voltage cascode current mirror structure and a self-biased cascode current mirror structure.

9. A memory, characterized in that: The memory comprises a sense amplifier as claimed in any one of claims 1 to 8.

10. A method for operating a sense amplifier, characterized in that: The operating method is applied to the sense amplifier according to any one of claims 1 to 8; the offset cancellation phase sequentially includes a first sub-phase, a second sub-phase and a third sub-phase; the operating method includes: In the first sub-phase, the first control circuit does not couple the third node to the first voltage node, the second control circuit couples the fourth node to the second voltage node, and precharges the bit line and the complementary bit line coupled to the sense amplifier circuit; In the second sub-phase, the first control circuit couples the third node to the first voltage node, and the second control circuit couples the fourth node to the second voltage node, and amplifies the voltage difference between the bit line and the complementary bit line; In the third sub-phase, the first control circuit couples the third node to the first voltage node, and the second control circuit does not couple the fourth node to the second voltage node, and discharges the bit line and the complementary bit line.

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