Sensitive amplifier based on capacitor and flip point compensation, reading circuit and module

Abstract

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) circuit design, in particular to a sensitive amplifier, a reading circuit and a module based on capacitance and flip point compensation. The invention discloses a sensitive amplifier based on capacitors and flip point compensation. The sensitive amplifier comprises nine NMOS (N-channel Metal Oxide Semiconductor) tubes M1-M9, two PMOS (P-channel Metal Oxide Semiconductor) tubes P1-P2 and two capacitors C1-C2. According to the invention, the CSCSA is designed, and corresponding control logic is matched, so that a pre-charging stage, an offset elimination stage, a charge sharing stage, a pre-sensing stage and an induction amplification stage are designed when the DRAM storage unit is read, the potential of a bit line BL or BLB can be correctly changed, and the reading amplification function of the CSCSA is ensured. Compared with the traditional DRAM sensitive amplifier, the CSCSA provided by the invention has the advantages that the offset voltage index is greatly reduced and the sensing yield is improved under the condition that the quantity of elements is not greatly increased.

Description

Technical Field

[0001] The present invention relates to the technical field of DRAM circuit design, and more specifically, to: 1. a DRAM sense amplifier (CSCSA for short) based on capacitance and flip point compensation; 2. a read circuit constructed based on the CSCSA; 3. a sense amplifier module designed based on the CSCSA. Background Art

[0002] DRAM (Dynamic RAM) is a dynamic random access memory that uses a transistor plus a capacitor to store one bit of data, and requires periodic power replenishment to maintain the stored data.

[0003] With the continuous advancement of semiconductor manufacturing technology, DRAM production process nodes are also constantly upgraded. Therefore, the process size of DRAM is gradually reduced, which makes the amount of charge that DRAM storage cells can store less and less. The voltage difference generated during reading is gradually reduced, making it more difficult for DRAM sensitive amplifiers to read valid signals.

[0004] At the same time, as the process size decreases, the mismatch between transistors becomes more serious, which increases the offset voltage generated by the DRAM sense amplifier and aggravates the errors that occur when the DRAM sense amplifier is read.

[0005] Therefore, how to reduce the offset voltage of the DRAM sense amplifier is an important research direction. At the same time, it is also necessary to ensure that the components contained in the improved DRAM sense amplifier are not too many, so as to ensure that the circuit occupies an excessive area. Summary of the invention

[0006] Based on this, it is necessary to provide a sensitive amplifier, a reading circuit, and a module based on capacitance and flip point compensation to address the problem of large offset voltage of existing traditional DRAM sensitive amplifiers.

[0007] The present invention is implemented by the following technical solutions:

[0008] In a first aspect, the present invention provides a DRAM sense amplifier based on capacitance and flip point compensation, comprising: 9 NMOS tubes M1-M9, 2 PMOS tubes P1-P2, and 2 capacitors C1-C2.

[0009] The source of P1 is connected to the control signal SAP2;

[0010] The source of P2 is connected to the control signal SAP1;

[0011] The source of M1 is connected to the control signal SAN2, the gate is connected to the gate of P1, and the drain is connected to the drain of P1;

[0012] The source of M2 is connected to the control signal SAN1, the gate is connected to the gate of P1, and the drain is connected to the drain of P2;

[0013] The source of M3 is connected to the drain of M1, the gate is connected to the control signal OC, and the drain is connected to the gate of M1;

[0014] The source of M4 is connected to the drain of M2, the gate is connected to OC, and the drain is connected to the gate of M2;

[0015] The source of M5 is connected to the drain of M1, the gate is connected to the control signal ISO, and the drain is connected to the bit line BL;

[0016] The source of M6 is connected to the drain of M2, the gate is connected to ISO, and the drain is connected to the bit line BLB;

[0017] The source of M7 is connected to BL, the gate is connected to the control signal PRE, and the drain is connected to BLB;

[0018] The source of M8 is connected to BL, the gate is connected to PRE, and the drain is connected to the control signal Vref;

[0019] The source of M9 is connected to BLB, the gate is connected to PRE, and the drain is connected to the control signal Vref;

[0020] The first end of C1 is connected to BL, and the second end is connected to the gate of P2;

[0021] A first end of C2 is connected to BLB, and a second end of C2 is connected to the gate of P1.

[0022] Among them, P1 and M1 constitute inverter one, P2 and M2 constitute inverter two, inverter one and inverter two are cross-coupled through C1 and C2 to form a latch structure.

[0023] The implementation of the DRAM sense amplifier based on capacitance and flip point compensation is a method or process according to an embodiment of the present disclosure.

[0024] In a second aspect, the present invention discloses a reading circuit, comprising: a DRAM storage unit 1, a DRAM storage unit 2, and a DRAM sensitive amplifier based on capacitance and flip point compensation as disclosed in the first aspect.

[0025] DRAM storage cell 1 is used to store 0 or 1. DRAM storage cell 2 is used to store 0 or 1.

[0026] A DRAM sense amplifier based on capacitance and flip point compensation is used to read DRAM storage cell one or DRAM storage cell two.

[0027] The implementation of such a read circuit is in accordance with the method or process of an embodiment of the present disclosure.

[0028] In a third aspect, the present invention discloses a sense amplifier module, which adopts the circuit layout of the DRAM sense amplifier based on capacitance and flip point compensation as disclosed in the first aspect.

[0029] The implementation of such a sense amplifier module is based on a method or process of an embodiment of the present disclosure.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] 1. The present invention designs a DRAM sensitive amplifier based on capacitor and flip point compensation, and cooperates with corresponding control logic to design the following stages when reading the DRAM storage unit: pre-charge stage, offset elimination stage, charge sharing stage, pre-sense stage, and induction amplification stage. In the offset calibration stage, the offset is reduced by storing the flip voltage of the inverter and the voltage difference of the bit line in the capacitor; through the cooperation of the pre-sense stage and the induction amplification stage, the bit line potential can be correctly changed and pulled to the full swing, thereby ensuring the CSCSA read amplification function.

[0032] 2. Compared with the traditional DRAM sense amplifier, the CSCSA provided by the present invention achieves a significant reduction in the offset voltage index and improves the sensing yield without a large increase in the number of components. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0034] Figure 1 A circuit diagram of the CSCSA disclosed in Embodiment 1 of the present invention;

[0035] Figure 2 Based on Figure 1 Circuit diagram of the reading circuit constructed by CSCSA in;

[0036] Figure 3 for Figure 2 A timing operation diagram of a reading circuit;

[0037] Figure 4 Based on Figure 1 Pinout diagram of the CSCSA-designed sense amplifier module;

[0038] Figure 5 A circuit diagram of a read circuit based on an existing conventional DRAM sense amplifier (BLSA) is disclosed for Embodiment 2 of the present invention;

[0039] Figure 6 for Figure 5 A timing operation diagram of a reading circuit;

[0040] Figure 7 for Figure 5 The offset voltage distribution diagram of BLSA in the figure;

[0041] Figure 8 for Figure 1 Figure 2. Distribution of offset voltage of CSCSA in Figure 2. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time. When a component is considered to be "fixed to" another component, it may be directly fixed on the other component or there may be a central component at the same time.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more of the related listed items.

[0045] Example 1

[0046] First, see Figure 1 , is a circuit structure diagram of a DRAM sense amplifier (CSCSA) based on capacitance and flip point compensation provided in the first embodiment.

[0047] For CSCSA, it includes: 9 NMOS tubes M1-M9, 2 PMOS tubes P1-P2, and 2 capacitors C1-C2.

[0048] like Figure 1 As shown, the connection relationship of each component is as follows:

[0049] The source of P1 is connected to the control signal SAP2;

[0050] The source of P2 is connected to the control signal SAP1;

[0051] The source of M1 is connected to the control signal SAN2, the gate is connected to the gate of P1, and the drain is connected to the drain of P1;

[0052] The source of M2 is connected to the control signal SAN1, the gate is connected to the gate of P1, and the drain is connected to the drain of P2;

[0053] The source of M3 is connected to the drain of M1, the gate is connected to the control signal OC, and the drain is connected to the gate of M1;

[0054] The source of M4 is connected to the drain of M2, the gate is connected to OC, and the drain is connected to the gate of M2;

[0055] The source of M5 is connected to the drain of M1, the gate is connected to the control signal ISO, and the drain is connected to the bit line BL;

[0056] The source of M6 is connected to the drain of M2, the gate is connected to ISO, and the drain is connected to the bit line BLB;

[0057] The source of M7 is connected to BL, the gate is connected to the control signal PRE, and the drain is connected to BLB;

[0058] The source of M8 is connected to BL, the gate is connected to PRE, and the drain is connected to the control signal Vref;

[0059] The source of M9 is connected to BLB, the gate is connected to PRE, and the drain is connected to the control signal Vref;

[0060] The first end of C1 is connected to BL, and the second end is connected to the gate of P2;

[0061] A first end of C2 is connected to BLB, and a second end of C2 is connected to the gate of P1.

[0062] Among them, P1 and M1 constitute inverter one, P2 and M2 constitute inverter two, inverter one and inverter two are cross-coupled through C1 and C2 to form a latch structure.

[0063] For the convenience of subsequent explanation, the input and output of inverter 1 and inverter 2 can be represented by nodes:

[0064] The input of inverter 1 is node G1 (i.e., the gate of P1, the gate of M1, the drain of M3, and the second end of C2 are connected to node G1), and the output is node B1 (i.e., the drain of P1, the drain of M1, the source of M3, and the source of M5 are connected to node B1);

[0065] The input of inverter 2 is node G2 (i.e., the gate of P2, the gate of M2, the drain of M4, and the second end of C1 are connected to node G2), and the output is node B2 (i.e., the drain of P2, the drain of M2, the source of M4, and the source of M6 are connected to node B2).

[0066] Secondly, see Figure 2 Based on the above CSCSA, a read circuit is constructed, namely, a CSCSA use circuit. The read circuit includes: CSCSA, DRAM storage unit 1, and DRAM storage unit 2.

[0067] DRAM storage unit 1 is used to store 0 or 1. DRAM storage unit 2 is used to store 0 or 1. CSCSA is used to read DRAM storage unit 1 or DRAM storage unit 2.

[0068] DRAM storage unit 1 and DRAM storage unit 2 may adopt a common 1T1C structure.

[0069] See also Figure 2 DRAM storage unit 1 includes: 1 NMOS tube NM1 and 1 capacitor Cc1. The drain of NM1 is connected to BL, and the gate is connected to the word line WL1; the first end of Cc1 is connected to the source of NM1, and the second end is connected to VSS. DRAM storage unit 2 includes: 1 NMOS tube NM2 and 1 capacitor Cc2. The drain of NM2 is connected to BLB, and the gate is connected to the word line WL2; the second end of Cc2 is connected to the source of NM2, and the second end is connected to VSS.

[0070] It should be noted that WL1 and WL2 cannot be turned on at the same time to prevent damage to the data in the DRAM storage unit.

[0071] The above disclosed reading circuit is used to perform data reading operation, and its working sequence includes: pre-charge (PC) stage, offset cancellation (OC) stage, charge sharing (CS) stage, pre-sense (PS) stage, and sense amplification (MS) stage.

[0072] The following is a brief description of each stage:

[0073] 1) In the pre-charge stage:

[0074] PRE, OC, and ISO are set to high level (M3, M4, M5, M6, M7, M8, and M9 are turned on), SAP1, SAN1, SAP2, and SAN2 are set to VDD / 2 (inverter 1 and inverter 2 are not working), Vref is set to VDD / 2, and BL and BLB are pre-charged to VDD / 2 (Vref charges BL through M9, Vref charges BLB through M8, and BL and BLB are short-circuited through M7 to keep them at VDD / 2).

[0075] 2) During the offset calibration phase:

[0076] PRE and ISO are set to low potential (M5, M6, M7, M8, and M9 are disconnected), OC maintains high potential (M3 and M4 are turned on), SAP1 and SAP2 are set to high level, SAN1 and SAN2 are set to low level (inverter one and inverter two are working, G1 is short-circuited with B1 through M3, and G2 is short-circuited with B2 through M4, so that the voltage of G1 is the flip point voltage of inverter one, and the voltage of G2 is the flip point voltage of inverter two), the voltage difference between the input end (G1) of inverter one and BLB is stored in C2, and the voltage difference between the input end (G2) of inverter two and BL is stored in C1, thereby reducing the offset.

[0077] 3) In the charge sharing stage:

[0078] PRE and ISO are kept at low level (M5, M6, M7, M8, and M9 are disconnected), OC is set to low level (M3 and M4 are disconnected), SAP1, SAN1, SAP2, and SAN2 are set to VDD / 2 (inverter 1 and inverter 2 do not work);

[0079] 301, if DRAM storage unit 1 is to be read, WL1 is set to a high level (NM1 is turned on), and Cc1 and BL share charges (Cc1 is turned on through NM1 and BL).

[0080] 302, if DRAM storage unit 2 is to be read, WL2 is set to a high level (NM2 is turned on), and Cc2 and BLB share charges (Cc2 is turned on through NM2 and BLB).

[0081] 4) In the pre-sensory stage:

[0082] 401, if you want to read DRAM storage unit 1, WL1 is high in the charge sharing stage, then in the pre-sense stage, WL1 maintains a high level (NM1 is turned on), PRE maintains a low level (M7, M8, M9 are turned off), OC maintains a low level (M3, M4 are turned off), ISO is set to a high level (M5, M6 are turned on), SAN1 is set to a low level, SAP1 is set to a high level, SAN2, SAP2 maintain VDD / 2, so:

[0083] Inverter 1 works and the voltage difference between its input terminal (G1) and output terminal (B1) is enlarged; since B1 is connected to BL through M5, the voltage difference between the input terminal (G1) of inverter 1 and BL is increased.

[0084] Although the inverter 2 is not working, B2 and BLB are connected through M6 so that the two have the same level.

[0085] 402, if DRAM storage unit 2 is to be read, WL2 is at a high level in the charge sharing stage, then in the pre-sense stage, WL2 maintains a high level (NM2 is turned on), PRE maintains a low level (M7, M8, M9 are turned off), OC maintains a low level (M3, M4 are turned off), ISO is set to a high level (M5, M6 are turned on), SAN2 is set to a low level, SAP2 is set to a high level, SAN1, SAP1 maintain VDD / 2, so:

[0086] The second inverter works and the voltage difference between its input terminal (G2) and output terminal (B2) is enlarged; since B2 is connected to BLB through M6, the voltage difference between the input terminal (G2) of the second inverter and BLB is increased.

[0087] Although the inverter 2 is not working, B1 and BL are connected through M5 so that the two have the same level.

[0088] 5) In the induction amplification stage:

[0089] In general, in the sensing and amplification stage, WL1 and WL2 maintain the same state as in the pre-sensing stage, PRE maintains a low level (M7, M8, and M9 are disconnected), OC maintains a low level (M3 and M4 are disconnected), ISO maintains a high level (M5 and M6 are turned on), SAN1 and SAN2 are set to a low level, and SAP1 and SAP2 are set to a high level (inverter 1 and inverter 2 are working);

[0090] 501, if DRAM storage unit 1 is to be read, and DRAM storage unit 1 stores 1, then in the sensing and amplification stage, WL1 maintains a high level (NM1 is turned on), and the cross-coupled inverter 1 and inverter 2 increase the voltage difference (inverter 1 increases the voltage difference between G1 and B1, and inverter 2 increases the voltage difference between G2 and B2). Then, based on the pre-sense stage, the BL voltage is quickly pulled to VDD and the BLB voltage is quickly reduced to 0, so the storage data of DRAM storage unit 1 is obtained by reading the BL potential.

[0091] 502, if DRAM storage unit 1 is to be read, and DRAM storage unit 1 stores 0, then in the sensing and amplification stage, WL1 maintains a high level (NM1 is turned on), and the cross-coupled inverter 1 and inverter 2 increase the voltage difference (inverter 1 increases the voltage difference between G1 and B1, and inverter 2 increases the voltage difference between G2 and B2). Then, based on the pre-sense stage, the BL voltage is quickly reduced to 0 and the BLB voltage is quickly pulled to VDD, so the storage data of DRAM storage unit 1 is obtained by reading the BL potential.

[0092] 503, if DRAM storage unit 2 is to be read, and DRAM storage unit 2 stores 1, then in the sensing and amplification stage, WL2 maintains a high level (NM2 is turned on), and the cross-coupled inverters 1 and 2 increase the voltage difference (inverter 1 increases the voltage difference between G1 and B1, and inverter 2 increases the voltage difference between G2 and B2). Then, based on the pre-sense stage, the BLB voltage is quickly pulled to VDD and the BL voltage is quickly reduced to 0. Then, the storage data of DRAM storage unit 2 is obtained by reading the BLB potential.

[0093] 504, if DRAM storage unit 2 is to be read, and DRAM storage unit 2 stores 0, then in the sensing and amplification stage, WL2 maintains a high level (NM2 is turned on), and the cross-coupled inverters 1 and 2 increase the voltage difference (inverter 1 increases the voltage difference between G1 and B1, and inverter 2 increases the voltage difference between G2 and B2). Then, based on the pre-sense stage, the BLB voltage is quickly reduced to 0 and the BLB voltage is quickly pulled to VDD. Then, the storage data of DRAM storage unit 2 is obtained by reading the BLB potential.

[0094] In order to facilitate the understanding of the above stages, the timing change diagram of each signal at each stage is drawn by taking the reading of DRAM storage unit 1 as an example, as shown in FIG. Figure 3 shown.

[0095] In addition, this embodiment 1 simultaneously discloses a sense amplifier module, which adopts the circuit layout of the DRAM sense amplifier based on capacitance and flip point compensation disclosed above. The mode of packaging into a module is easier to promote and apply the above circuit.

[0096] like Figure 4 As shown, the sense amplifier module has 10 pins:

[0097] Among them, pin 1 is used to connect BL; pin 2 is used to connect BLB; pin 3 is used to connect Vref; pin 4 is used to connect PRE; pin 5 is used to connect SAP1; pin 6 is used to connect SAP2; pin 7 is used to connect SAN1; pin 8 is used to connect SAN2; pin 9 is used to connect ISO; pin 10 is used for OC.

[0098] Example 2

[0099] This embodiment 2 is intended to verify the performance effect of the DRAM sense amplifier based on capacitance and flip point compensation proposed in embodiment 1:

[0100] This embodiment 2 introduces a read circuit constructed by an existing traditional DRAM sense amplifier (BLSA), and performs simulation comparison with the read circuit constructed based on CSCSA proposed in embodiment 1.

[0101] First, the read circuit built based on BLSA is Figure 5 As shown, it includes: BLSA, DRAM storage unit three, and DRAM storage unit four.

[0102] Among them, BLSA includes: 5 NMOS transistors NM1~NM5 and 2 PMOS transistors PM1~PM2. The sources of PM1 and PM2 are connected to the control signal SAP; the sources of NM1 and NM2 are connected to the control signal SAN; the drain of PM1 is connected to the drain of NM1, and the gate is connected to the gate of NM1; the drain of PM2 is connected to the drain of NM2, the gate of PM1 and the bit line BL', and the gate is connected to the gate of NM2, the drain of PM1, and the bit line BLB'; the source of NM3 is connected to BLB', the drain is connected to BL', and the gate is connected to the control signal BLEQ'; the source of NM4 is connected to the source of NM3, the drain is connected to the input signal VEQ', and the gate is connected to the gate of NM3; the source of NM5 is connected to the drain of NM3, the drain is connected to the drain of NM4, and the gate is connected to the gate of NM4.

[0103] Among them, PM1 and NM1 constitute inverter three, PM2 and NM2 constitute inverter four, inverter three and inverter four realize cross coupling and form a latch structure.

[0104] The DRAM storage unit 3 includes: an NMOS transistor NM7 and a capacitor CM1. The drain of NM7 is connected to BL', and the gate is connected to the word line WL3; the first end of CM1 is connected to the source of NM7, and the second end is connected to VSS.

[0105] DRAM storage unit 4 includes: an NMOS transistor NM6 and a capacitor CM2. The drain of NM7 is connected to BLB', and the gate is connected to the word line WL4; the first end of CM2 is connected to the source of NM6, and the second end is connected to VSS.

[0106] For the reading circuit constructed based on BLSA of the above structure, the working sequence of the data reading operation includes: a pre-charge (PC) phase, a charge sharing (CS) phase, and a main sensing (MS) phase.

[0107] 1) In the pre-charge stage:

[0108] BLEQ' is set to high level (NM3, NM4, and NM5 are turned on), VEQ' is set to VDD / 2, SAP and SAN are set to VDD / 2 (inverter three and inverter four do not work), and BL' and BLB' are precharged to VDD / 2 (VEQ' charges BL' through NM5, VEQ' charges BLB' through NM4, and BL' and BLB' are turned on through NM3).

[0109] 2) In the charge sharing phase:

[0110] BLEQ' is set to low level (NM3, NM4, NM5 are disconnected), SAP and SAN are kept at VDD / 2 (inverter three and inverter four do not work);

[0111] If DRAM storage unit 3 is to be read, WL3 is set to a high level (NM7 is turned on), and CM1 and BL' share charges (CM1 is connected to BL' through NM7).

[0112] If DRAM storage unit 4 is to be read, WL4 is set to a high level (NM6 is turned on), and CM2 and BLB' share charges (CM2 is connected to BLB' through NM6).

[0113] 3) In the induction amplification stage:

[0114] In general, in the sensing amplification stage, WL3 and WL4 maintain the same state as in the charge sharing stage, BLEQ' remains low (NM3, NM4, and NM5 are disconnected), SAN is set to a low level, and SAP is set to a high level (inverter three and inverter four are working);

[0115] 301, if DRAM storage unit 3 is to be read, and DRAM storage unit 1 stores 0, then in the sensing and amplification stage, WL3 maintains a high level (NM7 is turned on), and the cross-coupled inverters 3 and 4 quickly increase the voltage difference, so that the BL' voltage drops to 0, and the BLB' voltage is pulled to VDD, then the storage data of DRAM storage unit 3 is obtained by reading the BL' potential.

[0116] 302, if DRAM storage unit three is to be read, and DRAM storage unit one stores 1, then in the sensing and amplification stage, WL3 maintains a high level (NM7 is turned on), and the cross-coupled inverter three and inverter four quickly increase the voltage difference, so that the BLB' voltage drops to 0, and the BL' voltage is pulled to VDD, then the storage data of DRAM storage unit three is obtained by reading the BL' potential.

[0117] 303, if DRAM storage unit 4 is to be read, and DRAM storage unit 4 stores 0, then in the sensing and amplification stage, WL4 maintains a high level (NM6 is turned on), and the cross-coupled inverters 3 and 4 quickly increase the voltage difference, so that the BLB' voltage drops to 0, and the BL' voltage is pulled to VDD, then the storage data of DRAM storage unit 4 is obtained by reading the BLB' potential.

[0118] 304, if DRAM storage unit 4 is to be read, and DRAM storage unit 4 stores 1, then in the sensing and amplification stage, WL4 maintains a high level (NM6 is turned on), and the cross-coupled inverters 3 and 4 quickly increase the voltage difference, so that the BL' voltage drops to 0, and the BLB' voltage is pulled to VDD, then the storage data of DRAM storage unit 4 is obtained by reading the BLB' potential.

[0119] In order to facilitate the understanding of the above stages, the timing change diagram of each signal at each stage is drawn by taking the reading of DRAM storage unit 3 as an example, as shown in FIG. Figure 6 shown.

[0120] Next, simulations are performed on the read circuit constructed based on CSCSA of Example 1 and the read circuit constructed based on BLSA described above.

[0121] The simulation conditions are as follows: based on 28nm CMOS process, the aspect ratio of PMOS tube is 300:30, and the aspect ratio of NMOS tube is 100:30; the capacitance value of C1 and C2 is 4fF; VDD is 0.9V; PRE, ISO, and OC are 1.35V when they are high level and 0V when they are low level; Vref is 0.45V.

[0122] 1. Perform 500 Monte Carlo simulations at room temperature to obtain the offset voltage distribution at different process angles. The results are shown in Figure 7 , Figure 8 .

[0123] Figure 7 , Figure 8 The offset voltage is a normal distribution curve, and the standard deviation is taken as the offset voltage. It can be seen that the offset voltage of CSCSA (2.169mV) is much lower than the offset voltage of BLSA (18.01mV).

[0124] 2. Perform 500 Monte Carlo simulations at 0.9V voltage and room temperature to examine the sensing yield.

[0125] The simulation results show that the proposed CSCSA sensing yield can reach 100%, while the BLSA sensing yield can only reach 83.5%.

[0126] It can be seen that CSCSA can improve the sensing yield when the circuit is working.

[0127] In summary, the CSCSA proposed in Example 1 has a significant performance advantage: with a small increase in the number of components, the offset voltage index is greatly reduced and the sensing yield is improved.

[0128] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0129] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A DRAM sense amplifier based on capacitance and flip point compensation, characterized in that: include: 9 NMOS tubes M1~M9, 2 PMOS tubes P1~P2, 2 capacitors C1~C2; The source of P1 is connected to the control signal SAP2; The source of P2 is connected to the control signal SAP1; The source of M1 is connected to the control signal SAN2, the gate is connected to the gate of P1, and the drain is connected to the drain of P1; The source of M2 is connected to the control signal SAN1, the gate is connected to the gate of P1, and the drain is connected to the drain of P2; The source of M3 is connected to the drain of M1, the gate is connected to the control signal OC, and the drain is connected to the gate of M1; The source of M4 is connected to the drain of M2, the gate is connected to OC, and the drain is connected to the gate of M2; The source of M5 is connected to the drain of M1, the gate is connected to the control signal ISO, and the drain is connected to the bit line BL; The source of M6 is connected to the drain of M2, the gate is connected to ISO, and the drain is connected to the bit line BLB; The source of M7 is connected to BL, the gate is connected to the control signal PRE, and the drain is connected to BLB; The source of M8 is connected to BL, the gate is connected to PRE, and the drain is connected to the control signal Vref; The source of M9 is connected to BLB, the gate is connected to PRE, and the drain is connected to the control signal Vref; The first end of C1 is connected to BL, and the second end is connected to the gate of P2; A first end of C2 is connected to BLB, and a second end of C2 is connected to the gate of P1. Among them, P1 and M1 constitute inverter one, P2 and M2 constitute inverter two, inverter one and inverter two are cross-coupled through C1 and C2 to form a latch structure.

2. A reading circuit, characterized in that: include: DRAM storage unit 1, which is used to store 0 or 1; DRAM storage unit 2, which is used to store 0 or 1; as well as The DRAM sense amplifier based on capacitance and flip point compensation as claimed in claim 1 is used to read DRAM storage cell one or DRAM storage cell two.

3. The reading circuit according to claim 2, characterized in that: The DRAM storage unit 1 includes: an NMOS tube NM1 and a capacitor Cc1; The drain of NM1 is connected to BL, and the gate is connected to word line WL1; A first end of Cc1 is connected to the source of NM1, and a second end is connected to VSS; The DRAM storage unit 2 includes: an NMOS tube NM2 and a capacitor Cc2; The drain of NM2 is connected to BLB, and the gate is connected to word line WL2; A second end of Cc2 is connected to the source of NM2, and a second end is connected to VSS; Among them, WL1 and WL2 are not turned on at the same time.

4. The reading circuit according to claim 3, characterized in that: The working sequence of the reading circuit includes: pre-charging stage, offset elimination stage, charge sharing stage, pre-sensing stage, and sensing amplification stage.

5. The reading circuit according to claim 4, characterized in that: In the precharge stage, PRE, OC, and ISO are set to high levels, SAP1, SAN1, SAP2, and SAN2 are set to VDD / 2, Vref is set to VDD / 2, and BL and BLB are precharged to VDD / 2.

6. The reading circuit according to claim 5, characterized in that: In the offset elimination stage, PRE and ISO are set to low potential, OC maintains high potential, SAP1 and SAP2 are set to high level, SAN1 and SAN2 are set to low level, the voltage difference between the input end of inverter one and BLB is stored in C2, and the voltage difference between the input end of inverter two and BL is stored in C1.

7. The read circuit according to claim 6, characterized in that: In the charge sharing stage, PRE and ISO are kept at low level, OC is set to low level, and SAN1, SAN2, SAP1, and SAP2 are set to VDD / 2; If WL1 is set to high level, Cc1 and BL share charge; If WL2 is set to a high level, Cc2 and BLB share charges.

8. The reading circuit according to claim 7, characterized in that: If WL1 is high in the charge sharing stage, then in the pre-sense stage, WL1 remains high, PRE remains low, OC remains low, ISO is set to high, SAN1 is set to low, SAP1 is set to high, SAN2 and SAP2 remain at VDD / 2, increasing the voltage difference between the input terminal of inverter 1 and BL; If WL2 is high in the charge sharing stage, then in the pre-sense stage, WL2 remains high, PRE remains low, OC remains low, ISO is set to a high level, SAN2 is set to a low level, SAP2 is set to a high level, SAN1 and SAP1 remain at VDD / 2, increasing the voltage difference between the input terminal of the inverter 2 and BLB.

9. The reading circuit according to claim 8, characterized in that: In the sensing and amplification stage, WL1 and WL2 maintain the same state as in the pre-sensing stage, PRE maintains a low level, OC maintains a low level, ISO maintains a high level, SAN1 and SAN2 are set to a low level, and SAP1 and SAP2 are set to a high level; If the DRAM storage unit 1 stores 1 and the WL1 sensing amplification stage is high, the BL voltage is pulled to VDD and the BLB voltage drops to 0; If DRAM storage cell 1 stores 0 and WL1 is high during the sensing and amplification phase, the BL voltage drops to 0 and the BLB voltage is pulled to VDD; If DRAM storage cell 2 stores 1 and WL2 is high in the sensing and amplification stage, the BLB voltage is pulled to VDD and the BL voltage drops to 0; If DRAM storage cell 2 stores 0 and WL2 is at a high level during the sensing and amplification phase, the BLB voltage drops to 0 and the BL voltage is pulled to VDD.

10. A sensitive amplifier module, characterized in that: A circuit layout of a DRAM sense amplifier based on capacitance and flip point compensation as claimed in claim 1 is adopted.

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