Sensitivity amplifier, read circuit, module based on capacitance and turnover point compensation

Abstract

The present application relates to the technical field of DRAM circuit design, and particularly relates to a sensitive amplifier, a reading circuit and a module based on capacitance and turnover point compensation. The present application discloses a sensitive amplifier based on capacitance and turnover point compensation, comprising: 9 NMOS tubes M1-M9, 2 PMOS tubes P1-P2, and 2 capacitors C1-C2. The present application designs a CSCSA and cooperates with corresponding control logic, so that when reading a DRAM storage unit, the present application designs a pre-charge stage, an offset elimination stage, a charge sharing stage, a pre-sense stage and a sense amplification stage, so that the potential of a bit line BL or BLB can be correctly changed, and the reading amplification function of the CSCSA is ensured. Compared with the traditional DRAM sensitive amplifier, the CSCSA provided by the present application can greatly reduce the offset voltage index and improve the sensing yield under the condition that the number of components is not greatly increased.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of DRAM circuit design, and more particularly, to: 1. a DRAM sensitive amplifier based on capacitor and flip point compensation (referred to as CSCSA); 2. a reading circuit based on the CSCSA; and 3. a sensitive amplifier module designed based on the CSCSA. BACKGROUND

[0002] DRAM (Dynamic RAM) is a dynamic random access memory, which stores one bit (1 bit) of data with one transistor plus one capacitor, and needs to be periodically replenished with power to maintain the data.

[0003] With the continuous progress of semiconductor manufacturing process, the production process node of DRAM is also constantly upgraded, so the process size of DRAM is gradually reduced, which makes the amount of charge that can be stored by the DRAM storage unit less and less, and the voltage difference generated during reading gradually decreases, making it more difficult for the DRAM sensitive amplifier to read the effective signal.

[0004] At the same time, with the reduction of process size, the mismatch between transistors becomes more and more serious, which increases the offset voltage generated by the DRAM sensitive amplifier, and aggravates the error condition of the DRAM sensitive amplifier during reading.

[0005] Therefore, how to reduce the offset voltage of the DRAM sensitive amplifier is an important research direction, and at the same time, it is also necessary to make the improved DRAM sensitive amplifier contain fewer elements, so as to ensure that the circuit occupies a small area. SUMMARY

[0006] Therefore, it is necessary to provide a sensitive amplifier, a reading circuit, and a module based on capacitor and flip point compensation to solve the problem of large offset voltage of the conventional DRAM sensitive amplifier.

[0007] The present application adopts the following technical solutions:

[0008] In a first aspect, the present application provides a DRAM sensitive amplifier based on capacitor and flip point compensation, which includes 9 NMOS tubes M1-M9, 2 PMOS tubes P1-P2, and 2 capacitors C1-C2.

[0009] The source of P1 is connected to the control signal SAP2.

[0010] The source of P2 is connected to the control signal SAP1.

[0011] The source of M1 is connected to the control signal SAN2, the gate is connected to the gate of P1, and the drain is connected to the drain of P1.

[0012] The source of M2 is connected with a control signal SAN1, the gate is connected with P1, and the drain is connected with P2;

[0013] The source of M3 is connected with the drain of M1, the gate is connected with a control signal OC, and the drain is connected with the gate of M1;

[0014] The source of M4 is connected with the drain of M2, the gate is connected with OC, and the drain is connected with the gate of M2;

[0015] The source of M5 is connected with the drain of M1, the gate is connected with a control signal ISO, and the drain is connected with a bit line BL;

[0016] The source of M6 is connected with the drain of M2, the gate is connected with ISO, and the drain is connected with the bit line BLB;

[0017] The source of M7 is connected with BL, the gate is connected with a control signal PRE, and the drain is connected with BLB;

[0018] The source of M8 is connected with BL, the gate is connected with PRE, and the drain is connected with a control signal Vref;

[0019] The source of M9 is connected with BLB, the gate is connected with PRE, and the drain is connected with the control signal Vref;

[0020] The first end of C1 is connected with BL, and the second end is connected with the gate of P2;

[0021] The first end of C2 is connected with BLB, and the second end is connected with the gate of P1.

[0022] Wherein, P1 and M1 constitute an inverter one, P2 and M2 constitute an inverter two, the inverter one and the inverter two are cross-coupled through C1 and C2, and form a latch structure.

[0023] The implementation of the DRAM sensitive amplifier based on the capacitor and the flip point compensation according to the method or process of the embodiment of the present disclosure.

[0024] In the second aspect, the present disclosure discloses a reading circuit, comprising: a DRAM storage unit one, a DRAM storage unit two, and a DRAM sensitive amplifier based on the capacitor and the flip point compensation according to the first aspect.

[0025] The DRAM storage unit one is used for storing 0 or 1. The DRAM storage unit two is used for storing 0 or 1.

[0026] The DRAM sensitive amplifier based on the capacitor and the flip point compensation is used for reading the DRAM storage unit one or the DRAM storage unit two.

[0027] The implementation of the reading circuit according to the method or process of the embodiment of the present disclosure.

[0028] Thirdly, the present invention discloses a sensitive amplifier module that adopts the circuit layout of a DRAM sensitive amplifier based on capacitance and flip-point compensation as disclosed in the first aspect.

[0029] The implementation of this sensitive amplifier module is based on the method or process of an embodiment of this disclosure.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] 1. This invention designs a DRAM sensitive amplifier based on capacitor and flip-point compensation, and with corresponding control logic, it incorporates the following stages during DRAM memory cell reading: pre-charge stage, offset cancellation stage, charge sharing stage, pre-sensing stage, and inductive amplification stage. Specifically, in the offset calibration stage, the offset is reduced by storing the difference between the inverter's flip-point voltage and the bit line voltage in a capacitor. Through the coordination of the pre-sensing stage and the inductive amplification stage, the bit line potential can be correctly varied and pulled to its full swing, ensuring the CSCSA read amplification function.

[0032] 2. Compared with traditional DRAM sensitive amplifiers, the CSCSA provided by this invention achieves a significant reduction in offset voltage and an improvement in sensing yield with only a small increase in the number of components. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a circuit diagram of the CSCSA disclosed in Embodiment 1 of the present invention;

[0035] Figure 2 For based on Figure 1 Circuit diagram of the read circuit constructed by CSCSA;

[0036] Figure 3 for Figure 2 Timing diagram of the read circuit;

[0037] Figure 4 For based on Figure 1 Pinout diagram of the sensitive amplifier module designed by CSCSA;

[0038] Figure 5 The present invention discloses a circuit diagram of a readout circuit based on a conventional DRAM sensitive amplifier (BLSA) in Embodiment 2 of the present invention;

[0039] Figure 6 For Figure 5 the timing operation diagram of the reading circuit;

[0040] Figure 7 For Figure 5 the distribution diagram of the offset voltage of BLSA in the embodiment 1;

[0041] Figure 8 For Figure 1 the distribution diagram of the offset voltage of CSCSA in the embodiment 1. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0043] It should be noted that when a component is referred to as being "mounted on" another component, it can be directly on the other component or there can be a middle component. When a component is referred to as being "disposed on" another component, it can be directly disposed on the other component or there can be a middle component. When a component is referred to as being "fixed on" another component, it can be directly fixed on the other component or there can be a middle component.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0045] Embodiment 1

[0046] First, referring to Figure 1 , a circuit structure diagram of a DRAM sense amplifier (CSCSA) based on capacitance and turnover point compensation provided by the embodiment 1 is shown.

[0047] For the CSCSA, it includes 9 NMOS tubes M1-M9, 2 PMOS tubes P1-P2, and 2 capacitors C1-C2.

[0048] As shown in Figure 1 , the connection relationship of each element is as follows:

[0049] The source of P1 is connected with a control signal SAP2;

[0050] a source connection control signal SAP1 of P2;

[0051] a source connection control signal SAN2 of M1, a gate connected to the gate of P1, a drain connected to the drain of P1;

[0052] a source connection control signal SAN1 of M2, a gate connected to the gate of P1, a drain connected to the drain of P2;

[0053] a source connected to the drain of M1, a gate connected to a control signal OC, a drain connected to the gate of M1 of M3;

[0054] a source connected to the drain of M2, a gate connected to OC, a drain connected to the gate of M2 of M4;

[0055] a source connected to the drain of M1, a gate connected to a control signal ISO, a drain connected to the bit line BL of M5;

[0056] a source connected to the drain of M2, a gate connected to ISO, a drain connected to the bit line BLB of M6;

[0057] a source connected to BL, a gate connected to a control signal PRE, a drain connected to BLB of M7;

[0058] a source connected to BL, a gate connected to PRE, a drain connected to a control signal Vref of M8;

[0059] a source connected to BLB, a gate connected to PRE, a drain connected to a control signal Vref of M9;

[0060] a first end connected to BL, a second end connected to the gate of P2 of C1;

[0061] a first end connected to BLB, a second end connected to the gate of P1 of C2.

[0062] Wherein, P1, M1 constitute an inverter one, P2, M2 constitute an inverter two, the inverter one and the inverter two are cross coupled through C1, C2, and form a latch structure.

[0063] For the convenience of subsequent description, the input and output of the inverter one and the inverter two can be represented by nodes:

[0064] The input of the inverter one is node G1 (i.e. the gate of P1, the gate of M1, the drain of M3, the second end of C2 connected to node G1), and the output is node B1 (i.e. the drain of P1, the drain of M1, the source of M3, the source of M5 connected to node B1);

[0065] The input of the inverter two is node G2 (i.e. the gate of P2, the gate of M2, the drain of M4, the second end of C1 is connected to node G2), and the output is node B2 (i.e. the drain of P2, the drain of M2, the source of M4, the source of M6 is connected to node B2).

[0066] Secondly, referring to Figure 2 , a read circuit is constructed based on the above-mentioned CSCSA, i.e. the use circuit of the CSCSA. The read circuit comprises: the CSCSA, a DRAM storage unit one, a DRAM storage unit two.

[0067] The DRAM storage unit one is used for storing 0 or 1. The DRAM storage unit two is used for storing 0 or 1. The CSCSA is used for reading the DRAM storage unit one or the DRAM storage unit two.

[0068] The DRAM storage unit one and the DRAM storage unit two can adopt a common 1T1C structure.

[0069] Referring to Figure 2 , the DRAM storage unit one comprises: 1 NMOS tube NM1, 1 capacitor Cc1. The drain of NM1 is connected to BL, and the gate is connected to the word line WL1; the first end of Cc1 is connected to the source of NM1, and the second end is connected to VSS. The DRAM storage unit two comprises: 1 NMOS tube NM2, 1 capacitor Cc2. The drain of NM2 is connected to BLB, and the gate is connected to the word line WL2; the second end of Cc2 is connected to the source of NM2, and the second end is connected to VSS.

[0070] It should be noted that WL1 and WL2 cannot be opened at the same time to prevent damage to the data in the DRAM storage unit.

[0071] The read data operation is performed using the above-mentioned disclosed read circuit, and the working timing comprises: a pre-charge (PC) stage, an offset cancellation (OC) stage, a charge sharing (CS) stage, a pre-sense (PS) stage, and a sense amplification (MS) stage.

[0072] The principle of each stage is described as follows:

[0073] 1) In the pre-charge stage:

[0074] PRE, OC, ISO are placed at high level (M3, M4, M5, M6, M7, M8, M9 are turned on), SAP1, SAN1, SAP2, SAN2 are placed at VDD / 2 (the inverter one and the inverter two do not work), Vref is placed at VDD / 2, BL, BLB are pre-charged to VDD / 2 (Vref charges BL through M9, Vref charges BLB through M8, BL and BLB are shorted through M7 to keep at VDD / 2).

[0075] 2) In the misalignment calibration phase:

[0076] PRE, ISO are set to low (M5, M6, M7, M8, M9 are off), OC is kept high (M3, M4 are on), SAP1, SAP2 are set to high, SAN1, SAN2 are set to low (inverter one, inverter two are working, G1 is shorted to B1 through M3, G2 is shorted to B2 through M4, so that the voltage of G1 is the turning point voltage of inverter one, and the voltage of G2 is the turning point voltage of inverter two), the voltage difference between the input end (G1) of inverter one and BLB is stored in C2, and the voltage difference between the input end (G2) of inverter two and BL is stored in C1, thereby reducing misalignment.

[0077] 3) In the charge sharing phase:

[0078] PRE, ISO are kept low (M5, M6, M7, M8, M9 are off), OC is set to low (M3, M4 are off), SAP1, SAN1, SAP2, SAN2 are set to VDD / 2 (inverter one, inverter two are not working);

[0079] 301, if DRAM storage unit one is to be read, WL1 is set to high (NM1 is on), Cc1 performs charge sharing with BL (Cc1 is conducted to BL through NM1).

[0080] 302, if DRAM storage unit two is to be read, WL2 is set to high (NM2 is on), Cc2 performs charge sharing with BLB (Cc2 is conducted to BLB through NM2).

[0081] 4) In the pre-sensing phase:

[0082] 401, if DRAM storage unit one is to be read, WL1 is high in the charge sharing phase, in the pre-sensing phase, WL1 is kept high (NM1 is on), PRE is kept low (M7, M8, M9 are off), OC is kept low (M3, M4 are off), ISO is set to high (M5, M6 are on), SAN1 is set to low, SAP1 is set to high, SAN2, SAP2 are kept VDD / 2, so that:

[0083] inverter one works and the voltage difference between its input end (G1) and output end (B1) is enlarged; since B1 is connected to BL through M5, the voltage difference between the input end (G1) of inverter one and BL is increased.

[0084] Inverter two does not work, but B2 is connected to BLB through M6, so that the levels of B2 and BLB are the same.

[0085] 402, if the DRAM storage unit two is to be read, WL2 is high in the charge sharing stage, then in the pre-sensing stage, WL2 keeps high (NM2 is on), PRE keeps low (M7, M8, M9 are off), OC keeps low (M3, M4 are off), ISO is set to high (M5, M6 are on), SAN2 is set to low, SAP2 is set to high, SAN1, SAP1 keep VDD / 2, so that:

[0086] Inverter two works and enlarges the voltage difference between its input (G2) and output (B2); since B2 is connected to BLB through M6, the voltage difference between the input (G2) of inverter two and BLB is enlarged.

[0087] Inverter two does not work, but B1 is connected to BL through M5, so that the levels of B1 and BL are the same.

[0088] 5) In the sense amplification stage:

[0089] In general, in the sense amplification stage, WL1, WL2 keep the same state as in the pre-sensing stage, PRE keeps low (M7, M8, M9 are off), OC keeps low (M3, M4 are off), ISO keeps high (M5, M6 are on), SAN1, SAN2 are set to low, SAP1, SAP2 are set to high (inverter one and inverter two work);

[0090] 501, if the DRAM storage unit one is to be read and the DRAM storage unit one stores 1, in the sense amplification stage, WL1 keeps high (NM1 is on), the cross-coupled inverter one and inverter two enlarge the voltage difference (inverter one enlarges the voltage difference between G1 and B1, and inverter two enlarges the voltage difference between G2 and B2), so that on the basis of the pre-sensing stage, the voltage of BL is quickly pulled to VDD and the voltage of BLB is quickly lowered to 0, then the BL potential is read to obtain the storage data of the DRAM storage unit one.

[0091] 502, if the DRAM storage unit one is to be read and the DRAM storage unit one stores 0, in the sense amplification stage, WL1 keeps high (NM1 is on), the cross-coupled inverter one and inverter two enlarge the voltage difference (inverter one enlarges the voltage difference between G1 and B1, and inverter two enlarges the voltage difference between G2 and B2), so that on the basis of the pre-sensing stage, the voltage of BL is quickly lowered to 0 and the voltage of BLB is quickly pulled to VDD, then the BL potential is read to obtain the storage data of the DRAM storage unit one.

[0092] 503, if the DRAM storage unit two is to be read and the DRAM storage unit two stores 1, then in the sensing amplification stage, WL2 remains high (NM2 is turned on), the cross-coupled inverter one and inverter two pull the voltage difference (the inverter one pulls the voltage difference of G1 and B1, and the inverter two pulls the voltage difference of G2 and B2), so that the BLB voltage is quickly pulled to VDD and the BL voltage is quickly reduced to 0 on the basis of the pre-sensing stage, and then the BLB potential is read to obtain the storage data of the DRAM storage unit two.

[0093] 504, if the DRAM storage unit two is to be read and the DRAM storage unit two stores 0, then in the sensing amplification stage, WL2 remains high (NM2 is turned on), the cross-coupled inverter one and inverter two pull the voltage difference (the inverter one pulls the voltage difference of G1 and B1, and the inverter two pulls the voltage difference of G2 and B2), so that the BLB voltage is quickly pulled to VDD and the BLB voltage is quickly reduced to 0 on the basis of the pre-sensing stage, and then the BLB potential is read to obtain the storage data of the DRAM storage unit two.

[0094] In order to facilitate the understanding of the above stages, the timing change diagram of each signal in each stage is drawn by taking the reading of the DRAM storage unit one as an example, as shown in Figure 3 .

[0095] In addition, the embodiment 1 synchronously discloses a sensitive amplifier module which adopts the circuit layout of the DRAM sensitive amplifier based on the capacitance and turnover point compensation disclosed above. The mode of being packaged into a module is more conducive to the popularization and application of the above circuit.

[0096] As shown in Figure 4 , the sensitive amplifier module has 10 pins:

[0097] Among them, pin one is used for connecting BL; pin two is used for connecting BLB; pin three is used for connecting Vref; pin four is used for connecting PRE; pin five is used for connecting SAP1; pin six is used for connecting SAP2; pin seven is used for connecting SAN1; pin eight is used for connecting SAN2; pin nine is used for connecting ISO; and pin ten is used for OC.

[0098] Embodiment 2

[0099] The embodiment 2 aims to verify the performance effect of the DRAM sensitive amplifier based on the capacitance and turnover point compensation proposed in the embodiment 1:

[0100] The embodiment 2 introduces a reading circuit constructed by the existing conventional DRAM sensitive amplifier (BLSA), and compares it with the reading circuit constructed by the CSCSA proposed in the embodiment 1.

[0101] Firstly, the reading circuit constructed based on BLSAFigure 5 As shown, it comprises: BLSA, DRAM storage unit three, DRAM storage unit four.

[0102] Wherein, the BLSA comprises: 5 NMOS tubes NM1-NM5, 2 PMOS tubes PM1-PM2. The source of PM1, PM2 is connected with control signal SAP; the source of NM1, NM2 is connected with control signal SAN; the drain of PM1 is connected with the drain of NM1, and the gate is connected with the gate of NM1; the drain of PM2 is connected with the drain of NM2, the gate of PM1 and the bit line BLB', the gate is connected with the gate of NM2, the drain of PM1 and the bit line BLB'; the source of NM3 is connected with BLB', the drain is connected with BL', and the gate is connected with control signal BLEQ'; the source of NM4 is connected with the source of NM3, the drain is connected with input signal VEQ', and the gate is connected with the gate of NM3; the source of NM5 is connected with the drain of NM3, the drain is connected with the drain of NM4, and the gate is connected with the gate of NM4.

[0103] Wherein, PM1, NM1 constitute inverter three, PM2, NM2 constitute inverter four, inverter three, inverter four realize cross coupling, and form a latch structure.

[0104] DRAM storage unit three comprises: 1 NMOS tube NM7, 1 capacitor CM1. The drain of NM7 is connected with BL', and the gate is connected with word line WL3; the first end of CM1 is connected with the source of NM7, and the second end is connected with VSS.

[0105] DRAM storage unit four comprises: 1 NMOS tube NM6, 1 capacitor CM2. The drain of NM7 is connected with BLB', and the gate is connected with word line WL4; the first end of CM2 is connected with the source of NM6, and the second end is connected with VSS.

[0106] For the read circuit based on BLSA constructed by the above structure, the working time sequence of reading data operation comprises: precharge (PC) stage, charge sharing (CS) stage, main induction (MS) stage.

[0107] 1) In the precharge stage:

[0108] BLEQ' is set to high level (NM3, NM4, NM5 are turned on), VEQ' is set to VDD / 2, SAP, SAN are set to VDD / 2 (inverter three, inverter four do not work), BL', BLB' are precharged to VDD / 2 (VEQ' charges BL' through NM5, VEQ' charges BLB' through NM4, BL', BLB' are connected through NM3).

[0109] 2) In the charge sharing stage:

[0110] BLEQ' is low (NM3, NM4, NM5 off), SAP, SAN are VDD / 2 (inverters three, four are not working);

[0111] To read DRAM cell three, WL3 is high (NM7 on), CM1 shares charge with BL' (CM1 is connected to BL' through NM7).

[0112] To read DRAM cell four, WL4 is high (NM6 on), CM2 shares charge with BLB' (CM2 is connected to BLB' through NM6).

[0113] 3) In the sensing stage:

[0114] In general, in the sensing stage, WL3, WL4 keep the same as in the charge sharing stage, BLEQ' is low (NM3, NM4, NM5 off), SAN is low, SAP is high (inverters three, four are working).

[0115] 301, To read DRAM cell three, and DRAM cell one is 0, in the sensing stage, WL3 is high (NM7 on), the cross-coupled inverters three, four quickly pull the voltage difference, so that the BL' voltage drops to 0, the BLB' voltage is pulled to VDD, then the BL' potential is read to get the storage data of DRAM cell three.

[0116] 302, To read DRAM cell three, and DRAM cell one is 1, in the sensing stage, WL3 is high (NM7 on), the cross-coupled inverters three, four quickly pull the voltage difference, so that the BLB' voltage drops to 0, the BL' voltage is pulled to VDD, then the BL' potential is read to get the storage data of DRAM cell three.

[0117] 303, To read DRAM cell four, and DRAM cell four is 0, in the sensing stage, WL4 is high (NM6 on), the cross-coupled inverters three, four quickly pull the voltage difference, so that the BLB' voltage drops to 0, the BL' voltage is pulled to VDD, then the BLB' potential is read to get the storage data of DRAM cell four.

[0118] 304, if the DRAM storage unit four is to be read and the DRAM storage unit four stores 1, then in the sensing amplification stage, WL4 keeps high (NM6 is turned on), the cross-coupled inverter three and inverter four quickly pull the voltage difference, so that the BL' voltage drops to 0, and the BLB' voltage is pulled to VDD, and then the BLB' potential is read to obtain the storage data of the DRAM storage unit four.

[0119] In order to facilitate the understanding of the above stages, the timing changes of each signal in each stage are plotted when reading the DRAM storage unit three, as shown in Figure 6 .

[0120] Secondly, the read circuit based on CSCSA constructed in embodiment 1 and the read circuit based on BLSA constructed above are simulated.

[0121] The simulation conditions are as follows: based on 28nm CMOS process, the length-width ratio of PMOS is 300:30, the length-width ratio of NMOS is 100:30; the capacitance value of C1 and C2 is 4fF; VDD is 0.9V; PRE, ISO and OC are 1.35V in high level and 0V in low level; Vref is 0.45V.

[0122] 1. 500 times of Monte Carlo simulation are performed at room temperature to obtain the distribution of the offset voltage under different process angles, and the results are shown in Figure 7 , Figure 8 .

[0123] Figure 7 , Figure 8 are normal distribution curves of the offset voltage, and the standard deviation is taken as the offset voltage. It can be seen that the offset voltage (2.169mV) of CSCSA is much lower than the offset voltage (18.01mV) of BLSA,

[0124] 2. 500 times of Monte Carlo simulation are performed at 0.9V voltage and room temperature to investigate the sensing yield.

[0125] The simulation results show that the sensing yield of the proposed CSCSA can reach 100%, while the sensing yield of BLSA can only reach 83.5%.

[0126] It can be seen that CSCSA can improve the sensing yield during the operation of the circuit.

[0127] It can be seen that CSCSA can improve the sensing yield during the operation of the circuit.

[0128] Any combination of the technical features in the above-described embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, as long as the combination of the technical features does not exist in contradiction, it shall be considered within the scope of the present disclosure.

[0129] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it shall not be understood as a limitation on the patent scope of the present application. It shall be pointed out that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these shall be within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A DRAM sense amplifier based on capacitance and turnover point compensation, characterized by, Comprise: 9 NMOS tubes M1~M9, 2 PMOS tubes P1~P2, 2 capacitors C1~C2; The source of P1 is connected with control signal SAP2; The source of P2 is connected with control signal SAP1; The source of M1 is connected with control signal SAN2, the gate is connected with the gate of P1, and the drain is connected with the drain of P1; The source of M2 is connected with control signal SAN1, the gate is connected with the gate of P1, and the drain is connected with the drain of P2; The source of M3 is connected with the drain of M1, the gate is connected with control signal OC, and the drain is connected with the gate of M1; The source of M4 is connected with the drain of M2, the gate is connected with OC, and the drain is connected with the gate of M2; The source of M5 is connected with the drain of M1, the gate is connected with control signal ISO, and the drain is connected with bit line BL; The source of M6 is connected with the drain of M2, the gate is connected with ISO, and the drain is connected with bit line BLB; The source of M7 is connected with BL, the gate is connected with control signal PRE, and the drain is connected with BLB; The source of M8 is connected with BLB, the gate is connected with PRE, and the drain is connected with control signal Vref; The source of M9 is connected with BL, the gate is connected with PRE, and the drain is connected with control signal Vref; The first end of C1 is directly connected with BL, and the second end is connected with the gate of P2; The first end of C2 is directly connected with BLB, and the second end is connected with the gate of P1; Wherein, P1 and M1 constitute inverter one, P2 and M2 constitute inverter two, inverter one and inverter two are cross-coupled through C1 and C2, and form a latch structure.

2. A reading circuit, characterized by Comprise: DRAM storage unit one for storing 0 or 1; DRAM storage unit two for storing 0 or 1; And The DRAM sensitive amplifier based on capacitance and flip point compensation as claimed in claim 1 is used to read DRAM storage unit one or DRAM storage unit two.

3. The read circuit of claim 2, wherein, The DRAM storage unit one comprises: 1 NMOS tube NM1, 1 capacitor Cc1; The drain of NM1 is connected with BL, and the gate is connected with word line WL1; The first end of Cc1 is connected with the source of NM1, and the second end is connected with VSS; The DRAM storage unit two comprises: 1 NMOS tube NM2, 1 capacitor Cc2; The drain of NM2 is connected with BLB, and the gate is connected with word line WL2; The second end of Cc2 is connected with the source of NM2, and the second end is connected with VSS; Wherein, WL1 and WL2 are not opened at the same time.

4. The read circuit of claim 3, wherein, The working timing of the reading circuit comprises: pre-charging stage, offset elimination stage, charge sharing stage, pre-sensing stage, and sensing amplification stage.

5. The read circuit of claim 4, wherein, In the pre-charging stage, PRE, OC, and ISO are set to high level, SAP1, SAN1, SAP2, and SAN2 are set to VDD / 2, Vref is set to VDD / 2, and BL and BLB are pre-charged to VDD / 2.

6. The read circuit of claim 5, wherein, In the offset elimination stage, PRE and ISO are set to low potential, OC remains high potential, SAP1 and SAP2 are set to high level, SAN1 and SAN2 are set to low level, the voltage difference between the input end of inverter one and BLB is stored in C2, and the voltage difference between the input end of inverter two and BL is stored in C1.

7. The read circuit of claim 6, wherein, In the charge sharing phase, PRE, ISO remain low, OC is set to low, SAN1, SAN2, SAP1, SAP2 are set to VDD / 2; If WL1 is set to high, Cc1 shares charge with BL; If WL2 is set to high, Cc2 shares charge with BLB.

8. The read circuit of claim 7, wherein, If WL1 is high in the charge sharing phase, in the pre-sensing phase, WL1 remains high, PRE remains low, OC remains low, ISO is set to high, SAN1 is set to low, SAP1 is set to high, SAN2, SAP2 remain VDD / 2, increasing the voltage difference between the input of inverter one and BL; If WL2 is high in the charge sharing phase, in the pre-sensing phase, WL2 remains high, PRE remains low, OC remains low, ISO is set to high, SAN2 is set to low, SAP2 is set to high, SAN1, SAP1 remain VDD / 2, increasing the voltage difference between the input of inverter two and BLB.

9. The read circuit of claim 8, wherein, In the sensing amplification phase, WL1, WL2 remain the same as in the pre-sensing phase, PRE remains low, OC remains low, ISO remains high, SAN1, SAN2 are set to low, SAP1, SAP2 are set to high; If DRAM storage unit one stores 1 and WL1 is high in the sensing amplification phase, the voltage of BL is pulled to VDD, and the voltage of BLB is lowered to 0; If DRAM storage unit one stores 0 and WL1 is high in the sensing amplification phase, the voltage of BL is lowered to 0, and the voltage of BLB is pulled to VDD; If DRAM storage unit two stores 1 and WL2 is high in the sensing amplification phase, the voltage of BLB is pulled to VDD, and the voltage of BL is lowered to 0; If DRAM storage unit two stores 0 and WL2 is high in the sensing amplification phase, the voltage of BLB is lowered to 0, and the voltage of BL is pulled to VDD.

10. A sensitive amplifier module characterized by, The circuit layout of the DRAM sensitive amplifier based on capacitance and flip point compensation as claimed in claim 1 is adopted.

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