Ultra-wideband high-linearity phased array switch

Abstract

The invention discloses an ultra-wideband high-linearity phased array switch, which comprises three ports, namely a transmitting end TX port, an antenna end ANT port and a receiving end RX port, and is characterized in that when a transmitting branch is switched on, a signal is transmitted from the TX port to the ANT port; when the receiving branch is conducted, a signal is transmitted from the ANT port to the RX port; the transmitting branch comprises a matching inductor L2, a transistor M5, a transistor M6, a transistor M1, a transistor M2 and a matching inductor L1, the receiving branch comprises a matching inductor L1, a transistor M3, a transistor M4, a transistor M7, a transistor M8 and a matching inductor L3, the proposed switch is designed by adopting a classic series-parallel structure, a deep N-well NMOS (N-channel Metal Oxide Semiconductor) transistor is used, and the matching inductor L1, the transistor M5, the transistor M6, the transistor M1, the transistor M2 and the matching inductor L3 are matched. The isolation degree of the transistor of the turn-off branch is improved by adopting a negative body bias technology, and meanwhile, the power processing capacity of the turn-off transistor is improved by adopting a negative voltage bias technology and a transistor stacking technology together.

Description

Technical Field

[0001] The present invention relates to the technical field of phased array switches, and in particular to an ultra-wideband high-linearity phased array switch. Background Art

[0002] RF switch design is divided into mechanical (MEMS) switch design and solid-state switch design. Compared with mechanical switches, solid-state switches have faster switching speeds, higher reliability and smaller area. Solid-state switch circuits were first constructed with PIN diodes, which can exhibit low insertion loss, high power handling capability and high operating frequency, but have large DC power consumption. High electron mobility switches based on GaAs technology can change the working state by changing the gate control voltage, without consuming DC power, but with poor integration. With the continuous reduction of silicon-based semiconductor process size, the continuous reduction of power supply voltage, and the requirements of switch design for improving integration and reducing costs, CMOS switches have become the mainstream process for phased array switch design. At present, common switch topologies based on CMOS technology include traditional symmetrical structure, asymmetrical structure, differential structure and distributed structure. Among them, differential structure often brings large insertion loss, and distributed structure has poor integration, which is not suitable for phased array systems. The power handling capabilities of the transmitting branch and the receiving branch of the asymmetrical structure are very different, which determines that it is only suitable for transceiver front-end systems.

[0003] The current high-performance phased array switch design still faces certain challenges because it often requires low insertion loss, high isolation between the transmit path and the receive path, and high power handling capability of the transmit path. Traditional symmetrical structures include classic series-parallel structures, λ / 4 transmission line switches, and transmission line switches based on LC components. The classic series-parallel structure has a certain trade-off between insertion loss and isolation due to the influence of the on-resistance and off-capacitance of the transistor. The resonant switch structure often uses the resonance of the series inductor and the capacitor of the off transistor to eliminate the trade-off between insertion loss and isolation, but the introduction of the resonant inductor also limits the operating bandwidth of the switch, and the power handling capability is low and the linearity is poor. Although the switch based on the transmission line can significantly reduce the area, it also faces the problem of limited power handling capability. Transistor stacking technology is a commonly used technology to improve power handling capability, but as the number of transistor stacks increases, it will bring additional insertion loss. In addition, the current switch design is also based on the complementary structure of NMOS transistors and PMOS transistors to improve the power handling capability of the switch, but it also brings additional insertion loss. Summary of the invention

[0004] The technical problem to be solved by the present invention is to alleviate the problem of large loss in the CMOS process itself and to improve the power handling capability of the ultra-wideband switch while avoiding the deterioration of insertion loss. In order to solve the above problems, an ultra-wideband high-linearity phased array switch is provided.

[0005] The object of the present invention is achieved in the following manner: An ultra-wideband high-linearity phased array switch, comprising three ports, namely a transmitting end TX port, an antenna end ANT port and a receiving end RX port. When the transmitting branch is turned on, the signal is transmitted from the TX port to the ANT port; when the receiving branch is turned on, the signal is transmitted from the ANT port to the RX port; the transmitting branch comprises a matching inductor L2, a transistor M5, a transistor M6, a transistor M1, a transistor M2 and a matching inductor L1, one end of the matching inductor L2 is connected to the TX port, and the other end is respectively connected to the drain of the transistor M1 and the drain of the transistor M5. The source of the transistor M1 is connected to the drain of the transistor M2, and the source of the transistor M2 is connected to the ANT port through the matching inductor L1; the source of the transistor M5 is connected to the drain of the transistor M6, and the source of the transistor M6 is grounded; the gates of the transistors M1 and M2 are connected to the control level Vctrl through the large resistors RG1 and RG2 respectively; the gates of the transistors M5 and M6 are connected to the control level -Vctrl through the large resistors RG5 and RG6 respectively; the body terminals of the transistors M1 and M2 are connected to the control level Vctrl through the large resistors RG1 and RG2 respectively. Resistors RB1 and RB2 are connected to the control level VB1, and the body ends of transistors M5 and M6 are connected to the control level VB2 through large resistors RB5 and RB6. The receiving branch includes a matching inductor L1, a transistor M3, a transistor M4, transistors M7, M8 and a matching inductor L3. The drain of the transistor M3 is connected to the matching inductor L1, the source of the transistor M3 is connected to the drain of the transistor M4, and the source of M4 is connected to the RX port through the matching inductor L3; the source of M4 is connected to the drain of the transistor M7, and the transistor M7 The source of the transistor M7 is connected to the drain of the transistor M8, and the source of the transistor M8 is grounded; the gates of the transistor M7 and the transistor M8 are connected to the control level Vctrl through the large resistors RG7 and RG8 respectively; the gates of the transistor M3 and the transistor M4 are connected to the control level -Vctrl through the large resistors RG3 and RG4 respectively; the body ends of the transistor M3 and the transistor M4 are connected to the control level VB2 through the large resistors RB3 and RB2, and the body ends of the transistor M7 and the transistor M8 are connected to the control level VB1 through the large resistors RB7 and RB8 respectively.

[0006] A feedback capacitor C is connected in series between the gate and drain of the transistors M1, M2, M3, M4, M5, M6, M7 and M8. fi(i=1,2,3…8).

[0007] The transistor uses a deep N-well NMOS transistor to build a circuit. The deep N-well technology is achieved by adding a Deep N-Well layer between the P-well and the P-substrate; the P-well and the Deep N-Well layer are independently powered.

[0008] Beneficial effects of the present invention: The switch proposed by the present invention is designed with a classic series-parallel structure, uses NMOS transistors with deep N wells, uses negative body bias technology for transistors of the turn-off branch to improve isolation, and uses negative voltage bias technology and transistor stacking technology to jointly improve the power handling capacity of the turn-off transistor. Inductors are added to the three ports to form an LC resonant network with the turn-off parasitic capacitance of the parallel transistors for impedance matching, thereby realizing ultra-wideband operation of the switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is the overall architecture of ultra-wideband phased array switch.

[0010] Figure 2 It is a transistor stack circuit in the off state.

[0011] Figure 3 is the equivalent schematic of a stacked transistor with a feed-forward capacitor.

[0012] Figure 4 This is the schematic diagram of negative voltage bias.

[0013] Figure 5 This is the insertion loss simulation and test result diagram.

[0014] Figure 6 This is a diagram of isolation simulation and test results.

[0015] Figure 7 This is a graph of return loss simulation and test results.

[0016] Figure 8 These are the simulation and test results of the 1dB compression point at 10GHz. DETAILED DESCRIPTION

[0017] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0018] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same technical meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0019] like Figure 1As shown, the present invention discloses an ultra-wideband high-linearity phased array switch, which is implemented based on a series-parallel structure and uses transistor stacking technology and negative voltage bias technology to improve power handling capability. It includes three ports, namely a transmitting end TX port, an antenna end ANT port and a receiving end RX port. When the transmitting branch is turned on, the signal is transmitted from the TX port to the ANT port; when the receiving branch is turned on, the signal is transmitted from the ANT port to the RX port; the transmitting branch includes a matching inductor L2, a transistor M5, a transistor M6, a transistor M1, a transistor M2 and a matching inductor L1. One end of the matching inductor L2 is connected to the TX port, and the other end is respectively connected to the drain of the transistor M1 and the drain of the transistor M5. The source of the transistor M1 The drain of transistor M2 is connected, and the source of transistor M2 is connected to the ANT port through the matching inductor L1; the source of transistor M5 is connected to the drain of transistor M6, and the source of transistor M6 is grounded; the gates of transistor M1 and transistor M2 are connected to the control level Vctrl through large resistors RG1 and RG2 respectively; the gates of transistor M5 and transistor M6 are connected to the control level -Vctrl through large resistors RG5 and RG6 respectively; the body ends of transistor M1 and transistor M2 are connected to the control level -Vctrl through large resistors RB1 and RB2 The body ends of the transistors M5 and M6 are connected to the control level VB1, and are connected to the control level VB2 through large resistors RB5 and RB6; the receiving branch includes a matching inductor L1, a transistor M3, a transistor M4, a transistor M7, a transistor M8 and a matching inductor L3; the drain of the transistor M3 is connected to the matching inductor L1, the source of the transistor M3 is connected to the drain of the transistor M4, and the source of the M4 is connected to the RX port through the matching inductor L3; the source of the M4 is connected to the drain of the transistor M7, and the source of the transistor M7 is connected to the transistor M8. The drain of the body tube M8 is connected, and the source of the transistor M8 is grounded; the gates of the transistors M7 and M8 are connected to the control level Vctrl through large resistors RG7 and RG8 respectively; the gates of the transistors M3 and M4 are connected to the control level -Vctrl through large resistors RG3 and RG4 respectively; the body ends of the transistors M3 and M4 are connected to the control level VB2 through large resistors RB3 and RB2, and the body ends of the transistors M7 and M8 are connected to the control level VB1 through large resistors RB7 and RB8 respectively. Different from the classic series-parallel structure, the transistors in the transmitting branch and the receiving branch both adopt a stacked structure of two transistors to divide the input signal evenly and improve the power handling capacity of the switch. However, due to the parasitic effects of the CMOS process, the signal will not be divided into voltages after passing through the stacked transistors. Usually, the transistors close to the signal source end will bear a voltage higher than the average divided voltage, while the transistors close to the load end will bear a voltage lower than the average divided voltage. Therefore, the feedback capacitor Cf is used to improve the uneven voltage division. A feedback capacitor C is connected between the gate and drain of the transistors M1, M2, M3, M4, M5, M6, M7 and M8. fi( i=1,2,3…8) to achieve uniform signal voltage division.

[0020] The transistor uses a deep N-well NMOS transistor to build a circuit. The deep N-well technology is achieved by adding a Deep N-Well layer between the P-well and the P-substrate; the P-well and the Deep N-Well layer are independently powered (VB, VDNW).

[0021] The selection of the switch conduction branch is controlled by the bias voltage. In this switch, the transistor is turned off by connecting the gate to a negative voltage, which complements the transistor stacking technology and further improves the switch power handling capability. When the transmitting branch (TX-ANT) is turned on, transistors M1 and M2 are in the on state, and the gate is connected through a large resistor R G Connected to high level, transistors M5 and M6 are in the off state, the gate is connected to negative voltage, transistors M3 and M4 are in the off state to prevent signal leakage from the RX port to a certain extent, the gate is connected to negative voltage through a large resistor RG, and the parallel transistor M4 is in the on state to introduce a small amount of leakage signal into the substrate, further improving the switch isolation, and the gate is connected to a high level through a large resistor RG. When the receiving branch (ANT-RX) is turned on, transistors M3 and M4 are in the on state, and the gate is connected to a high level through a large resistor RG. Transistors M7 and M8 are in the off state, and the gate is connected to negative voltage through a large resistor RG. Transistors M1 and M2 are in the off state to prevent signal leakage from the RX port to a certain extent, so the gate is connected to a large resistor R G Connected to negative voltage, transistors M5 and M6 are in the on state to introduce a small amount of leakage signal into the substrate, further improving the switch isolation, so connected to a high level.

[0022] Figure 2 is a transistor stack circuit in the off state (a) ideal case, (b) non-ideal case, such as Figure 2 The principle of transistor stacking technology is shown in the figure. The number of transistor stacks is finally determined to be two based on simulation and calculation, corresponding to Figure 1 In the overall architecture diagram of ultra-wideband, M1, M2; M3, M4; M5, M6; M7, M8 are stacked.

[0023] like Figure 3 As shown, the principle of using feedback capacitors corresponds to Figure 1 C in the overall architecture diagram of China Super Broadband fi (i=1,2,3…8); like Figure 4 As shown, corresponding to Figure 1 Ultra-wideband overall architecture diagram, when VctrlWhen it is high level (1.8 V), transistors M1, M2, M7 and M8 are turned on, M3, M4, M5 and M6 are turned off, and the off voltage is -1.8V, and the switch is in TX (TX to ANT) transmitting state; when Vctrl When it is low level (-1.8V), transistors, M3, M4, M5 and M6 are turned on, M1, M2, M7 and M8 are turned off, and the switch is in the RX (ANT to RX) receiving state.

[0024] The transmitter TX port, antenna ANT port and receiver RX port all use inductors for impedance matching (L1, L2 and L3). After simulation, it is determined that the inductance values ​​of the three inductors are all 214pH.

[0025] Figure 5 — Figure 7 The simulation and test results of the S parameters of the switch in the transmitting and receiving states are shown. Figure 5-Figure 8 Figure (a) is the transmitting mode, and (b) is the receiving mode. In the DC-20GHz frequency band, the test shows that the insertion loss of the transmitting branch is <2.28dB, the isolation is greater than 19.7dB, the TX port return loss is >15dB, and the ANT port input return loss is >14dB; the insertion loss of the receiving branch is less than 2.43dB, the isolation is >19.4dB, the ANT port return loss is >13dB, and the RX port input return loss is greater than 14dB. Figure 8 shows the simulation and test results of the power handling capability of the switch in the transmitting and receiving states. The test results show that at the center frequency of 10GHz, the IP1dB in the transmitting mode is 30.3dBm, and the IP1dB in the receiving mode is 28.8dBm.

[0026] The switching transistor size and bias voltage in the present invention are determined by: The overall switch design is based on the 180nm CMOS process node. The total gate width of M1, M2, M5, and M6 is 176um, and the total gate width of M3, M4, M7, and M8 is 64um. The gate bias resistor and the body bias resistor are both 15kΩ, and the bias voltage is selected as the maximum withstand voltage of the transistor, 1.8V.

[0027] The number of stacked transistors in the present invention is determined by: When the transistor is turned off, VG = -1.8V. If the switch is to be able to handle watt-level power, the number of transistor stacks is calculated according to the formula as follows: The calculation satisfies the return loss of less than 15dB and the system impedance Z0 = 50Ω. Combining the simulation and calculation results, the three-transistor stack structure has the largest power handling capacity but brings a large insertion loss, so the two-transistor stack switch structure is selected.

[0028] Port impedance matching in the present invention: All three ports use inductors for impedance matching (L1, L2, and L3). After simulation, it is determined that the inductance values ​​of the three inductors are all 214pH.

[0029] The switch structure proposed in the present invention is designed based on a series-parallel structure, which optimizes the isolation performance compared with the traditional series switch structure. In addition, the negative body bias technology is used for the turn-off transistor to optimize the isolation. Although the series-parallel switch optimizes the isolation, it also leads to a certain trade-off relationship between insertion loss and isolation, so the transistor size should be reasonably selected.

[0030] The circuit is constructed using deep N-well NMOS transistors. The deep N-well technology isolates the body of the traditional CMOS transistor from the substrate by adding a DeepN-Well layer between the P-well and the P-substrate, alleviating the defects of the traditional bulk silicon CMOS process, such as low substrate impedance and easy signal leakage. At the same time, the P-well and Deep N-Well layers are independently powered (V B , V DNW ).

[0031] The size of the transistor is reasonably selected based on the simulation results of the switch insertion loss and isolation, and the off capacitance of the transistor is cleverly used to perform impedance matching at the three ports to achieve ultra-wideband operation of the switch.

[0032] The circuit is built using deep N-well NMOS transistors and negative gate bias technology is used to supplement transistor stacking technology, which improves the switching power handling capability while avoiding the deterioration of insertion loss caused by excessive number of transistor stacks. At the same time, feedback capacitors are used to adjust the voltage division on the stacked transistors to make the transistor voltage division more uniform.

[0033] The above is only a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, several changes and improvements can be made without departing from the overall concept of the present invention, which should also be regarded as the scope of protection of the present invention.

Claims

1. An ultra-wideband high linearity phased array switch, characterized in that: The invention comprises three ports, namely, a transmitting end TX port, an antenna end ANT port and a receiving end RX port. When the transmitting branch is turned on, the signal is transmitted from the TX port to the ANT port; when the receiving branch is turned on, the signal is transmitted from the ANT port to the RX port; the transmitting branch comprises a matching inductor L2, a transistor M5, a transistor M6, a transistor M1, a transistor M2 and a matching inductor L1; one end of the matching inductor L2 is connected to the TX port, and the other end is respectively connected to the drain of the transistor M1 and the drain of the transistor M5; the source of the transistor M1 is connected to the drain of the transistor M2, and the source of the transistor M2 is connected to the ANT port through the matching inductor L1; the source of the transistor M5 is connected to the drain of the transistor M6, and the source of the transistor M6 is grounded; the gates of the transistor M1 and the transistor M2 are respectively connected to the control level Vctrl through large resistors RG1 and RG2; the gates of the transistor M5 and the transistor M6 are respectively connected to the control level Vctrl through large resistors RG5 and RG6 Control level -Vctrl; the body ends of the transistors M1 and M2 are connected to the control level VB1 through large resistors RB1 and RB2, and the body ends of the transistors M5 and M6 are connected to the control level VB2 through large resistors RB5 and RB6. The receiving branch includes a matching inductor L1, a transistor M3, a transistor M4, a transistor M7, a transistor M8 and a matching inductor L3. The drain of the transistor M3 is connected to the matching inductor L1, the source of the transistor M3 is connected to the drain of the transistor M4, and the source of the M4 is connected to the RX port through the matching inductor L3; the source of the M4 is connected to the drain of the transistor M7, the source of the transistor M7 is connected to the drain of the transistor M8, and the source of the transistor M8 is grounded; the gates of the transistors M7 and M8 are connected to the control level Vctrl through large resistors RG7 and RG8 respectively; the gates of the transistors M3 and M4 are connected to the control level -Vctrl through large resistors RG3 and RG4 respectively; The body ends of the transistors M3 and M4 are connected to the control level VB2 through the large resistors RB3 and RB2, and the body ends of the transistors M7 and M8 are connected to the control level VB1 through the large resistors RB7 and RB8, respectively.

2. The ultra-wideband high linearity phased array switch according to claim 1, characterized in that: A feedback capacitor C is connected in series between the gate and drain of the transistors M1, M2, M3, M4, M5, M6, M7 and M8. fi( i=1,2,3…8).

3. The ultra-wideband high linearity phased array switch according to claim 1, characterized in that: The transistor uses a deep N-well NMOS transistor to build a circuit. The deep N-well technology is achieved by adding a Deep N-Well layer between the P-well and the P-substrate; the P-well and the Deep N-Well layer are independently powered.

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