Method for manufacturing chip structure and chip structure

Abstract

A method of manufacturing a chip structure is provided. The method includes attaching a chip to a chip carrier using a chip attachment layer, where the chip attachment layer includes a metal having a first melting point, where the chip includes a solder layer, and the chip carrier includes a further solder layer, where the solder layer includes a metal having a second melting point. The solder layer and / or the further solder layer comprises a respective solder material having a second melting point lower than the first melting point; and forming an intermetallic phase between the solder material and the metal of the die attach layer by melting the solder material having the second melting point.

Description

Technical Field

[0001] Various embodiments generally relate to a method of manufacturing a chip structure and a chip structure. Background Art

[0002] Chip structures comprising a chip soldered to a carrier often suffer from reliability issues regarding the solder connections, which may mean that the solder connections may at least partially break, eg due to stress and / or thermal cycling.Alternatively or additionally, the (thermal and / or electrical) conductivity may be low. Summary of the invention

[0003] A method for manufacturing a chip structure is provided. The method comprises: attaching a chip to a chip carrier using a chip attach layer, wherein the chip attach layer comprises a metal having a first melting point, wherein the chip comprises a solder layer and the chip carrier comprises an additional solder layer, the solder layer and the additional solder layer comprising respective solder materials having a second melting point lower than the first melting point; and forming an intermetallic phase between the solder material and the metal of the chip attach layer by melting the solder material. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] In the drawings, the same reference numerals generally refer to the same parts in different views. The drawings are not necessarily drawn to scale, but emphasis is generally placed on illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:

[0005] Figure 1 shows a method of manufacturing a chip structure according to various embodiments, and shows a schematic cross-sectional view of a resulting chip structure according to various embodiments;

[0006] Figure 2 shows the distribution of six different elements on a cross section of a chip structure according to various embodiments obtained via a scanning electron microscope;

[0007] Figure 3 Shows Figure 2 Electron microscope image of a cross section of the chip structure;

[0008] Figure 4 shows the distribution of six different elements on a cross section of another chip structure according to various embodiments obtained via a scanning electron microscope;

[0009] Figure 5 Shows Figure 4 Another chip structure extends beyond Figure 4 Electron microscope image of a cross section in the region of the portion shown;

[0010] Figure 6shows the distribution of six different elements on a cross section of yet another chip structure according to various embodiments obtained via a scanning electron microscope;

[0011] Figure 7 an electron microscope image showing a cross section of another chip structure according to various embodiments; and

[0012] Figure 8 A flow chart of a method of manufacturing a chip structure according to various embodiments is shown. DETAILED DESCRIPTION

[0013] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced.

[0014] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0015] The term "over" as used in relation to a deposited material formed "over" a side or surface may be used herein to mean that the deposited material may be formed "directly" on the referenced side or surface, e.g., in direct contact with the referenced side or surface. The term "over" as used in relation to a deposited material formed "over" a side or surface may be used herein to mean that the deposited material may be formed "indirectly" on the side or surface, wherein one or more additional layers are disposed between the side or surface and the deposited material.

[0016] In various embodiments, thermally induced intermetallic reactions are used to form reliable connections between a chip (also referred to as a “die”) and a chip carrier.

[0017] Thermally induced intermetallic reactions may occur between a solder material as one of the reaction partners arranged on the chip and / or chip carrier, respectively, and a metal of a chip attach layer arranged between (the solder material of) the chip and (the solder material of) the chip carrier.

[0018] In various embodiments, the metal on top of one or both connection surfaces may melt during the die attach curing process (which means that the curing temperature of the die attach process may be higher than the melting temperature of the top metal layer).

[0019] For die attach, a paste including a metal particle filler in a paste or film (which may additionally include an organic portion such as a resin, a solvent / liquid, and / or additives such as flux, surfactants, and activating substances) may be used.

[0020] The molten metal from the connection surface may combine with the metal particle filler of the die attach paste to form an intermetallic component, such as an intermetallic phase, in the connection layer.

[0021] Thus, enhanced heat dissipation can be achieved and higher reliability can be achieved. This may be particularly useful for new wide bandgap semiconductors (e.g., GaN, SiC, etc.) which may require high thermal / electrical conductivity chip interconnect structures for proper heat dissipation and overall green lead-free strategy.

[0022] Lead-free and highly conductive die attach systems enable higher voltage and power supply in dedicated systems, which can shrink devices with less material while achieving the same or even better electrical performance. Therefore, materials for both front-end and back-end production can be saved.

[0023] In various embodiments, an interconnect structure is provided by a thin (e.g., tens to hundreds of nanometers to several microns) coating of Sn, Bi and / or Zn (more generally, metals with low melting temperatures, such as In 157°C, Sn 232°C, Bi 271°C, and / or Zn 419.5°C) on the chip carrier and / or the back side of the chip (its last layer) and a paste containing metal particles (e.g., Ag and / or Cu), the paste further including an organic part (resin, liquid / solvent and / or other), forming a highly conductive intermetallic compound (IMC) contact structure by reaction of the metal particles contained in the paste with the low temperature melting coating of at least one connection surface (e.g., with the chip and / or chip carrier).

[0024] In various embodiments, a (lead-free) highly conductive and reliable (due to reduced stress transfer) chip attach interconnect system can be provided by lead-free die attach (DA) materials and associated and mating connection surfaces (e.g., a solder layer on the chip and / or an additional solder layer on the chip carrier).

[0025] High thermal conductivity can be ensured by a highly filled paste or film that can be used for die attach material, where "highly filled" refers to a high content of metal particles, the metal particles including or consisting of silver and / or copper. The high content of metal particles can be in the range of about 65 wt % to about 99 wt %.

[0026] Figure 1 A method of manufacturing a chip structure 100 according to various embodiments is shown, and a schematic cross-sectional view of a resulting chip structure 100 according to various embodiments is shown.

[0027] A chip 102 having a solder layer 104 may be provided.

[0028] The chip may be or include any type of semiconductor chip having integrated circuits. However, the high thermal and electrical conductivity that may be obtained in the chip structure 100 to be formed may be particularly beneficial for power chips, such as power chips including wide bandgap semiconductors (eg, GaN, SiC, and others).

[0029] Furthermore, a chip carrier 110 may be provided having a further solder layer 106. The chip carrier 110 may be or include any suitable type of chip carrier 110, such as a lead frame (eg a copper lead frame).

[0030] A chip attach layer 108 may be provided. The chip attach layer 108 may include a metal having a first melting point. The metal may be provided, for example, as metal particles included (e.g., dispersed) in the chip attach layer 108. The chip attach layer 108 may be provided, for example, as a (dispensable) paste or as a (solid but flexible) film. The metal may, for example, include or consist of silver and / or copper, for example, substantially pure silver, pure copper, a mixture of silver and copper, and / or an alloy of silver and / or copper. In addition to the metal, the chip attach layer 108 may, for example, include an organic portion (e.g., a resin, a solvent / liquid) and / or an additive (e.g., a flux, a surfactant, and an activating substance).

[0031] At least one of the solder layer 104 and the further solder layer 106 may include or consist of a solder material having a second melting point lower than the first melting point. The solder material having the second melting point may, for example, be or include a metal having a low melting point, such as indium (In), tin (Sn), bismuth (Bi) and / or zinc (Zn), a mixture or alloy thereof. Exemplary alloys are Sn5Sb and SnAg.

[0032] like Figure 1 As shown, chip 102 may be arranged on chip carrier 110 , wherein solder layer 104 and further solder layer 106 face each other.

[0033] Chip attach layer 108 may be disposed between chip 102 and chip carrier 110 . Figure 1 The chip attach layer 108 is shown disposed on the chip carrier 110 , but the chip attach layer 108 may generally be disposed on the chip 102 instead, or on both the chip 102 and the chip carrier 110 .

[0034] In various embodiments, an intermetallic phase between the solder material having the second melting temperature (which may originate from the solder layer 104 on the chip 102 and / or from another solder layer 106 on the chip carrier 110 ) and the metal of the chip attach layer 108 may be formed by melting the solder material having the second melting point.

[0035] In other words, the solder layer 104 and / or the further solder layer 106 (at least one of which includes or consists of a solder having a second melting point) is melted by heating the solder layer 104 and / or the further solder layer 106 and the chip attach layer 108 (typically, the entire arrangement structure is heated in a furnace as a unit) to the second melting point or above the second melting point.

[0036] The melted solder material may react with the (unmelted) metal of the die attach layer 108 to form an intermetallic compound IMC, also referred to as an intermetallic phase.

[0037] The solder material may diffuse into the die attach layer 108 to react with the metal in the die attach layer 108. Depending on whether only one of the solder layer 104 and the further solder layer 106 includes the solder material having the second melting point or both include the solder material having the second melting point, the solder material may diffuse into the die attach layer 108 from the chip side or the chip carrier side or from both sides.

[0038] In various embodiments, the terms “solder layer” and “further solder layer” may refer to suitability of the solder layer 104 and the further solder layer 106 , respectively, for forming a solder connection, eg, suitability for soldering something on the solder layer 104 and the further solder layer 106 .

[0039] At least one (optionally both) of the solder layer 104 and the further solder layer 106 may include a solder material having a second melting point and thus configured to contribute a reaction partner for forming an intermetallic compound when heated to or above the second temperature.

[0040] In various embodiments, both the solder layer 104 and the further solder layer 106 may include a solder material having a second melting point. The solder layer 104 and the further solder layer 106 may include or consist of the same solder material (thus, the second melting points of both may be the same), or the solder material included in or forming the solder layer 104 may be different from the solder material included in or forming the further solder layer 106 (thus, the second melting point of (the solder material of) the solder layer 104 may be different from the second melting point of (the solder material of) the further solder layer 106).

[0041] In various embodiments, more than one solder material (ie, with possibly different melting points) may be included in the solder layer 104 and / or more than one solder material may be included in the further solder layer 106 .

[0042] Depending on the specific circumstances of the solder layer 104, the further solder layer 106 and the chip attach layer 108, the source of the solder material in the solder layer 104 and / or the further solder layer 106 may be determined based on a gradient of solder material above the chip attach layer 108, remnants of solder material in the solder layer 104 and / or the further solder layer 106, porosity of the chip attach layer 108 (e.g., intermetallic compounds) and / or other diagnostics.

[0043] In various embodiments, the intermetallic compound may form a porous structure. The porous structure may relieve stress on the chip 102 , thereby increasing the reliability of the chip structure 100 .

[0044] In various embodiments, if the solder material containing layers of the solder layer 104 and the further solder layer 106 are formed to have a suitable thickness, a fine porous structure extending through the entire die attach layer 108 may be obtained.

[0045] “Suitable thickness” according to various embodiments may mean that the layer is thick enough to provide a sufficient amount of solder material for reacting with the metal of the chip attach layer 108 during its passage through the entire chip attach layer 108 (or at least halfway through the chip attach layer 108 if solder material is provided from the chip side and from the chip carrier side), but on the other hand is thin enough to avoid that excess solder material reacts too quickly with the metal of the chip attach layer 108, thereby possibly causing the intermetallic compound to form a barrier, which may hinder further diffusion through the chip attach layer 108.

[0046] In various embodiments, a suitable thickness may be, for example, in the range of about 500 nm to about 5 μm, such as between about 1 μm and 3 μm.

[0047] In various embodiments, nickel may be avoided in the solder material-containing layers of the solder layer 104 and the further solder layer 106. In particular, in the case of the chip carrier 110, the chip carrier 110 may include or consist of copper, which may react with potential excess solder material (e.g., to form CuSn in the case of Sn as solder material), thereby possibly helping to avoid too fast formation of intermetallic compounds IMC. Such a reaction may be inhibited by a nickel layer, which may prevent (excess) solder material from reacting with the material of the chip carrier 110 (e.g., copper).

[0048] In various embodiments, the temperature for melting the solder material may be selected depending on the solder material present in the solder layer 104 and / or the further solder layer 106 .

[0049] For example, in the case of indium, the solder material may be heated to 157° C. or higher, in the case of tin, the solder material may be heated to 232° C. or higher, in the case of bismuth, the solder material may be heated to 271° C. or higher, and / or in the case of zinc, the solder material may be heated to 419.5° C. or higher. All of these temperatures may be below the melting temperature of the metals in the die attach layer 108 .

[0050] In case the die attach layer 108 has a maximum solidification temperature, the solder material may be selected accordingly.In various embodiments, the temperature for melting the solder material may be maintained at or below 270°C, for example.

[0051] A typical temperature for forming an intermetallic compound may be, for example, about 250° C., for example for a solder material comprising or consisting of tin, such as Sn 5 Sb or SnAg.

[0052] In the following, some results of exemplary embodiments are shown.

[0053] The following material / structure combinations were realized:

[0054]

[0055]

[0056] Figure 2 shows the distribution of six different elements (C, Cu, O, Ni, Ag, Sn) on a cross section of the chip structure 100 according to various embodiments obtained via a scanning electron microscope, Figure 3 Shows Figure 2 Electron microscope image of a cross section of the chip structure 100. To avoid crowding, Figure 2 The identification of the components of the chip structure 100 is omitted. Figure 3 or Figure 1 For reference only.

[0057] Figure 2 and Figure 3 The results for group #3 mean that a sintering paste containing a large amount of silver particles was used in the die attach layer 108 and a tin layer was accordingly arranged on the chip 102 as solder layer 104 and on the chip carrier 110 as further solder layer 106 .

[0058] exist Figure 2 , the bottom two profiles highlighted by boxes represent silver (Ag) and tin (Sn) forming intermetallic phases, respectively.

[0059] As can be seen from the above distribution diagram and Figure 3As can be seen in FIG. 1 , a very fine and uniform distribution of Sn is obtained from the connection surfaces (solder layer 104 and further solder layer 106) into the die attach layer 108. Fine pores (shown in black) are distributed throughout the die attach layer 108.

[0060] Regions containing carbon (C) and / or oxygen (O) may indicate where the organic portion of the die attach material (eg, paste or film) remains. These regions may show an inhomogeneous distribution of the intermetallic phase.

[0061] Figure 4 shows the distribution of six different elements on a cross section of another embodiment of the chip structure 100 obtained via a scanning electron microscope;

[0062] Figure 5 Shows Figure 4 The chip structure 100 extends over Figure 4 Electron microscope image of a cross section in the region of the shown section. To avoid crowding, Figure 4 The identification of the components of the chip structure 100 is omitted. Figure 5 or Figure 1 For reference only.

[0063] Figure 4 and Figure 5 The results for Group 5 are shown. In other words, both the solder layer 104 and the further solder layer 106 include tin but no nickel. Figure 4 (area highlighted by the box) and Figure 5 As can be seen in FIG. 1 , a very fine and uniform distribution of tin in the die attach layer 108 is obtained.

[0064] Since Ag is provided in the relatively thin solder layer 104 and the further solder layer 106 (the thickness of each solder layer is between about 1 μm and 3 μm) for interdiffusion into the Ag particles of the die attach layer 108 and forming an Ag-rich Ag x Sn y The Sn reservoir of the phase is very limited, so rapid interdiffusion of Sn into the underlying metal layer and vice versa may occur.

[0065] The Ag-Sn system may have a tin-rich eutectic (96.2at% tin, melting temperature 221°C). Similar to the case of Cu-Sn, intermetallic phases may be encountered on the tin-poor side. The eutectic phase (e-phase) with a stoichiometric ratio of Ag3Sn may show a narrow Hume-Rothery type homogeneity region like the Cu3Sn phase. The non-eutectic phase (z-phase), the ternary Ag-Cu-Sn system, may be stable over a wider concentration range. Its range on the side facing tin may depend largely on temperature. The two phases may melt peritectically at a temperature of 480°C or 724°C, respectively.

[0066] In the Cu-Sn-system and the Ag-Sn-system, Ag is insoluble in Sn, but conversely, up to 11.5 at % of Sn can be dissolved in solid silver.

[0067] Figure 6 shows the distribution of six different elements on a cross section of another embodiment of the chip structure 100 obtained via a scanning electron microscope, Figure 7 Electron microscope images of cross sections of chip structures from the same group but different samples are shown. Figure 6 The identification of the components of the chip structure 100 is omitted. Figure 7 or Figure 1 For reference only.

[0068] Figure 6 and Figure 7 The results are for group #7. In group #7, the solder layer 104 includes tin but no nickel, but the additional solder layer 106 includes tin and nickel.

[0069] As from Figure 6 (lower right figure) it can be seen that the distribution of tin in the die attach layer 108 is not as uniform as in the above-mentioned groups 3 and 5. However, the intermetallic phase is at least partially obtained throughout the die attach layer 108, thereby improving the reliability of the chip structure 100 relative to the prior art.

[0070] Figure 8 A flow chart of a method of manufacturing a chip structure (eg, the above-described chip structure 100 ) according to various embodiments is shown.

[0071] The method comprises: attaching a chip to a chip carrier using a chip attach layer, wherein the chip attach layer comprises a metal having a first melting point, wherein the chip comprises a solder layer and the chip carrier comprises an additional solder layer, the solder layer and / or the additional solder layer comprising a corresponding solder material having a second melting point lower than the first melting point (810); and forming an intermetallic phase (820) between the solder material and the metal of the chip attach layer by melting the solder material having the second melting point.

[0072] Various examples are described below:

[0073] Example 1 is a method for manufacturing a chip structure. The method includes: attaching a chip to a chip carrier using a chip attach layer, wherein the chip attach layer includes a metal having a first melting point, wherein the chip includes a solder layer, and the chip carrier includes an additional solder layer, and the solder layer and / or the additional solder layer include a corresponding solder material having a second melting point lower than the first melting point; and forming an intermetallic phase between the solder material and the metal of the chip attach layer by melting the solder material having the second melting point.

[0074] In Example 2, the subject matter of Example 1 can optionally include that the solder layer and / or the additional solder layer is free of nickel.

[0075] In Example 3, the subject matter of Example 1 or 2 can optionally include that the solder material includes or consists of tin.

[0076] In Example 4, the subject matter of any of Examples 1-3 can optionally include that the solder material includes or consists of indium.

[0077] In Example 5, the subject matter of any of Examples 1-4 can optionally further include forming an alloy between the metal of the die attach layer and the additional metal of the die and / or between the metal of the die attach layer and the additional metal of the carrier.

[0078] In Example 6, the subject matter of any of Examples 1-5 can optionally include that melting includes heating the solder layer to a temperature in a range of 150°C to 300°C.

[0079] In Example 7, the subject matter of any of Examples 1-6 can optionally include that melting includes heating the solder layer to a temperature in a range of 232°C to 270°C.

[0080] In Example 8, the subject matter of any of Examples 1-7 can optionally include that a thickness of the solder layer of the chip and / or a thickness of the further solder layer of the carrier is less than 5 μm.

[0081] In Example 9, the subject matter of any of Examples 1-8 can optionally include that the die attach layer is configured as a paste or a film.

[0082] In Example 10, the subject matter of any of Examples 1-9 can optionally include that after forming the intermetallic phase, the die attach layer includes a porous structure.

[0083] In Example 11, the subject matter of any of Examples 1-10 can optionally include: the intermetallic phase having a porous structure.

[0084] In Example 12, the subject matter of Example 10 or 11 can optionally include that the size of the pores of the porous structure is in a range from about 20 nm to about 100 nm.

[0085] In Example 13, the subject matter of any of Examples 1-12 can optionally include that the die attach layer includes an organic adhesive.

[0086] In Example 14, the subject matter of any one of Examples 1-13 can optionally include that after forming the intermetallic phase, the porous structure and the organic binder form a non-uniform distribution.

[0087] In Example 15, the subject matter of any one of Examples 1-14 may optionally include that the chip attach layer forms a form-fitting connection with the chip and the chip carrier, respectively.

[0088] In Example 16, the subject matter of any of Examples 1-15 can optionally include that the solder material and the further solder material are the same.

[0089] In Example 17, the subject matter of any of Examples 1-15 can optionally include that the solder material and the further solder material are different.

[0090] Example 18 is a chip structure. The chip structure may include a chip having a solder layer, a chip carrier having an additional solder layer, and a chip attach layer attaching the chip to the chip carrier, wherein the chip attach layer includes an intermetallic phase formed by melting a solder material having a lower melting point than the metal of the chip attach layer between a solder material from the solder layer and a metal of the chip attach layer and / or between a solder material from the additional solder layer and a metal of the chip attach layer.

[0091] In Example 19, the subject matter of Example 18 can optionally include that the solder layer and / or the additional solder layer is free of nickel.

[0092] In Example 20, the subject matter of Example 18 or 19 can optionally include that the solder material includes or consists of tin.

[0093] In Example 21, the subject matter of any of Examples 18-20 can optionally include that the solder material includes or consists of indium.

[0094] In Example 22, the subject matter of any of Examples 18-21 can optionally include that the chip attach layer further includes an alloy between the metal of the chip attach layer and another metal of the chip and / or between the metal of the chip attach layer and another metal of the carrier.

[0095] In Example 23, the subject matter of any of Examples 18-22 can optionally include that melting includes heating the solder layer to a temperature in a range of 150°C to 300°C.

[0096] In Example 24, the subject matter of any of Examples 18-23 can optionally include that melting includes heating the solder layer to a temperature in a range of 232°C to 270°C.

[0097] In Example 25, the subject matter of any of Examples 18-24 can optionally include that a thickness of the solder layer of the chip and / or a thickness of the further solder layer of the carrier is less than 5 μm.

[0098] In Example 26, the subject matter of any of Examples 18-25 can optionally include that a thickness of the solder layer of the chip and / or a thickness of the further solder layer of the carrier is less than 5 μm.

[0099] In Example 27, the subject matter of any of Examples 18-26 can optionally include that after forming the intermetallic phase, the die attach layer includes a porous structure.

[0100] In Example 28, the subject matter of any of Examples 18-27 can optionally include the intermetallic phase having a porous structure.

[0101] In Example 29, the subject matter of any of Examples 18-28 can optionally include that the die attach layer includes an organic adhesive.

[0102] In Example 30, the subject matter of any of Examples 18-29 can optionally include that after forming the intermetallic phase, the porous structure and the organic binder form a non-uniform distribution.

[0103] In Example 31, the subject matter of any of Examples 18-30 can optionally include that the solder material and the further solder material are the same.

[0104] In Example 32, the subject matter of any of Examples 18-31 can optionally include that the solder material and the further solder material are different.

[0105] In Example 33, the subject matter of any one of Examples 18-30 may optionally include: the chip being a power chip.

[0106] Although the present invention has been particularly shown and described with reference to specific embodiments, it will be appreciated by those skilled in the art that various changes may be made to the present invention in form and detail without departing from the spirit and scope of the present invention as defined by the appended claims. Therefore, the scope of the present invention is indicated by the appended claims, and therefore it is intended to cover all changes within the meaning and scope of the equivalents of the claims.

Claims

1. A method for manufacturing a chip structure, the method comprising: attaching the chip to a chip carrier using a chip attach layer, wherein the chip attach layer comprises a metal having a first melting point, the chip comprises a solder layer, and the chip carrier comprises a further solder layer, the solder layer and / or the further solder layer comprising a respective solder material having a second melting point lower than the first melting point; By melting the solder material having the second melting point, an intermetallic phase is formed between the solder material and the metal of the die attach layer.

2. The method according to claim 1, in, The solder layer and / or the further solder layer is / are nickel-free.

3. The method according to claim 1 or 2, in, The solder material includes or consists of tin.

4. The method according to any one of claims 1 to 3, in, The solder material includes or consists of indium.

5. The method according to any one of claims 1 to 4, wherein: The method further comprises: An alloy is formed between the metal of the die attach layer and the further metal of the chip and / or between the metal of the die attach layer and the further metal of the carrier.

6. The method according to any one of claims 1 to 5, in, The melting includes heating the solder layer to a temperature in the range of 150°C to 300°C.

7. The method according to any one of claims 1 to 6, in, The melting includes heating the solder layer to a temperature in a range of 232°C to less than 270°C.

8. The method according to any one of claims 1 to 7, in, The thickness of the solder layer of the chip and / or the thickness of the further solder layer of the carrier is less than 5 μm.

9. The method according to any one of claims 1 to 8, in, The die attach layer is configured as a paste or a film.

10. The method according to any one of claims 1 to 9, in, After forming the intermetallic phase, the die attach layer includes a porous structure.

11. The method according to any one of claims 1 to 10, in, The intermetallic phase has a porous structure.

12. The method according to claim 10 or 11, in, The size of the pores of the porous structure ranges from about 20 nm to about 100 nm.

13. The method according to any one of claims 1 to 12, in, The die attach layer includes an organic adhesive.

14. The method according to any one of claims 1 to 13, in, After the intermetallic phase is formed, the porous structure and the organic binder form an inhomogeneous distribution.

15. The method according to any one of claims 1 to 14, in, The chip attach layer accordingly forms a positive connection with the chip and the chip carrier.

16. A chip structure, comprising: a chip having a solder layer; a chip carrier having an additional solder layer; as well as a chip attach layer that attaches the chip to the chip carrier; The chip attachment layer includes an intermetallic phase, which is formed between the solder material originating from the solder layer and the metal of the chip attachment layer and / or between the solder material originating from the additional solder layer and the metal of the chip attachment layer by melting a solder material having a melting point lower than that of the metal of the chip attachment layer.

17. The chip structure according to claim 16, in, The solder layer and / or the further solder layer is / are nickel-free.

18. The chip structure according to claim 16 or 17, in, The solder material includes or consists of tin.

19. The chip structure according to any one of claims 16 to 18, in, The solder material includes or consists of indium.

20. The chip structure according to any one of claims 16 to 19, in, The die attach layer further comprises an alloy between the metal of the die attach layer and another metal of the die and / or between the metal of the die attach layer and another metal of the carrier.

21. The chip structure according to any one of claims 16 to 20, in, The melting includes heating the solder layer to a temperature in the range of 150°C to 300°C.

22. The chip structure according to any one of claims 16 to 21, in, The melting includes heating the solder layer to a temperature in a range of 232°C to 270°C.

23. The chip structure according to any one of claims 16 to 22, in, The thickness of the solder layer of the chip and / or the thickness of the further solder layer of the carrier is less than 5 μm.

24. The chip structure according to any one of claims 16 to 23, in, The thickness of the solder layer of the chip and / or the thickness of the further solder layer of the carrier is less than 5 μm.

25. The chip structure according to any one of claims 16 to 24, in, After forming the intermetallic phase, the die attach layer includes a porous structure.

26. The chip structure according to any one of claims 16 to 25, in, The intermetallic phase has a porous structure.

27. The chip structure according to any one of claims 16 to 26, in, The die attach layer includes an organic adhesive.

28. The chip structure according to any one of claims 16 to 27, in, After the intermetallic phase is formed, the porous structure and the organic binder form an inhomogeneous distribution.

29. The chip structure according to any one of claims 16 to 28, in, The solder material and the further solder material are the same.

30. The chip structure according to any one of claims 16 to 28, in, The solder material and the further solder material are different.

31. The chip structure according to any one of claims 16 to 30, in, The chip is a power chip.

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