Data processing method and device, electronic equipment and storage medium

Abstract

The invention provides a data processing method, and relates to the technical field of artificial intelligence, in particular to the technical fields of chips, general matrix multiplication, large models and the like. According to the specific implementation scheme, in the current simulated annealing period, candidate data block information of a calculation unit is determined according to evaluated data block information of the calculation unit; determining a candidate hardware performance evaluation result according to the candidate data block information; according to the candidate hardware performance evaluation result, the current hardware performance evaluation result and the current temperature information, to-be-evaluated data block information of the current simulated annealing period in a post-simulated annealing period is determined, and the data block information comprises first data scale information and second data scale information; the first data scale information is used for indicating the scale of to-be-processed data of the calculation unit, and the second data scale information is used for indicating the scale of to-be-processed data blocks of the calculation unit. The invention further provides a data processing device, equipment and a medium.

Description

Technical Field

[0001] The present disclosure relates to the field of artificial intelligence technology, and in particular to the technical fields of chips, general matrix multiplication (GEMM), and large models. More specifically, the present disclosure provides a data processing method, device, electronic device, and storage medium. Background Art

[0002] With the development of artificial intelligence technology, the application of deep learning models is increasing. The size (shape) of data used for deep learning model training or reasoning is also increasing, and the required computing resources and storage resources are also increasing. Summary of the invention

[0003] The present disclosure provides a data processing method, apparatus, device and storage medium.

[0004] According to one aspect of the present disclosure, a data processing method is provided, the method comprising: in a current simulated annealing cycle, in response to a current hardware performance evaluation result not satisfying a preset performance condition, determining candidate data block information of a computing unit according to the evaluated data block information of the computing unit; determining a candidate hardware performance evaluation result according to the candidate data block information; determining data block information to be evaluated in a subsequent simulated annealing cycle of the current simulated annealing cycle according to the candidate hardware performance evaluation result, the current hardware performance evaluation result and current temperature information, wherein the evaluated data block information of the current simulated annealing cycle and the data block information to be evaluated in the subsequent simulated annealing cycle are different data block information, respectively, the data block information comprises first data scale information and second data scale information, the first data scale information is used to indicate the scale of the data to be processed of the computing unit, the second data scale information is used to indicate the scale of the data blocks to be processed of the computing unit, and the data blocks to be processed are obtained by segmenting the data to be processed.

[0005] According to another aspect of the present disclosure, a data processing device is provided, the device comprising: a first determination module for determining candidate data block information of a computing unit according to the evaluated data block information of the computing unit in response to a current hardware performance evaluation result not satisfying a preset performance condition in a current simulated annealing cycle; a second determination module for determining a candidate hardware performance evaluation result according to the candidate data block information; a third determination module for determining data block information to be evaluated in a subsequent simulated annealing cycle of the current simulated annealing cycle according to the candidate hardware performance evaluation result, the current hardware performance evaluation result and current temperature information, wherein the evaluated data block information of the current simulated annealing cycle and the data block information to be evaluated in the subsequent simulated annealing cycle are different data block information, respectively, and the data block information comprises first data scale information and second data scale information, the first data scale information is used to indicate the scale of the data to be processed of the computing unit, and the second data scale information is used to indicate the scale of the data blocks to be processed of the computing unit, and the data blocks to be processed are obtained by segmenting the data to be processed.

[0006] According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method provided according to the present disclosure.

[0007] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided. The computer instructions are used to cause a computer to execute the method provided according to the present disclosure.

[0008] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the method provided according to the present disclosure is implemented.

[0009] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0011] Figure 1 is a flow chart of a data processing method according to an embodiment of the present disclosure;

[0012] Figure 2A is a schematic diagram of multiple original matrices according to an embodiment of the present disclosure;

[0013] Figure 2B is a schematic diagram of a submatrix to be processed according to an embodiment of the present disclosure;

[0014] Figure 3 is a schematic diagram of executing a matrix multiplication operation and a pass operation according to an embodiment of the present disclosure;

[0015] Figure 4 is a block diagram of a data processing apparatus according to an embodiment of the present disclosure; and

[0016] Figure 5 is a block diagram of an electronic device to which a data processing method can be applied according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0018] A large model can be a deep learning model with a large number of parameters. A large model can be a large language model (LLM), an image model, or an audio model. When using one or more artificial intelligence acceleration boards to implement the training and reasoning of a large language model, the matrix multiplication operations involved in the large language model take up a lot of computing time. When computing resources and storage resources are limited, the input matrix involved in the matrix multiplication operation can be divided into blocks to implement the matrix multiplication operation. The size of the submatrix obtained after the matrix is ​​divided into blocks can affect the computing efficiency and memory access efficiency.

[0019] In addition, when using one or more artificial intelligence acceleration boards to implement inference during training of large language models, the hardware resource utilization rate of the artificial intelligence acceleration board is not high. For example, the matrix multiplication operation involved in the large language model can occupy more than 40% of the total computing time. The communication time between multiple artificial intelligence acceleration boards accounts for about 10% of the total computing time. During the matrix multiplication operation, the communication bandwidth between multiple artificial intelligence acceleration boards is not fully utilized. During the communication process, the accumulation operation also fails to effectively use computing resources. The artificial intelligence acceleration board may include an artificial intelligence chip. The artificial intelligence chip may be various processing units such as a general-purpose graphics processing unit (GPGPU), a tensor processing unit (TPU), and a neural network processing unit (NPU). In addition, there may be multiple computing units on the artificial intelligence acceleration board, and the computing units may also communicate with each other.

[0020] Therefore, in order to fully utilize the computing resources of the artificial intelligence acceleration board, the present disclosure provides a data processing method, which will be described below.

[0021] Figure 1 is a flow chart of a data processing method according to an embodiment of the present disclosure.

[0022] like Figure 1 As shown, the method 100 may include operations S110 to S130.

[0023] In operation S110 , in the current simulated annealing cycle, in response to the current hardware performance evaluation result not satisfying a preset performance condition, candidate data partition information of the computing unit is determined according to the evaluated data partition information of the computing unit.

[0024] In the embodiment of the present disclosure, the computing unit may be a matrix computing unit. For example, the matrix computing unit may include a systolic array.

[0025] In the disclosed embodiment, the current hardware performance evaluation result can be determined based on the evaluated data block information of the current simulated annealing cycle. For example, the current hardware performance evaluation result can be determined based on the data block information to be evaluated of the current simulated annealing cycle. After the hardware performance evaluation result is determined, the data block information to be evaluated of the current simulated annealing cycle can be used as the evaluated data block information.

[0026] In the embodiment of the present disclosure, the hardware performance evaluation result may include memory access utilization. The preset performance condition may include: the memory access resource utilization is greater than or equal to a preset threshold.

[0027] In the embodiments of the present disclosure, the candidate data segmentation information may be determined in various ways. For example, one or more data segmentation information different from the evaluated data segmentation information may be randomly generated as one or more candidate data segmentation information.

[0028] In an embodiment of the present disclosure, the data block information may include first data scale information and second data scale information. The first data scale information may indicate the scale of the data to be processed of the computing unit. The second data scale information may indicate the scale of the data block to be processed of the computing unit. The data block to be processed may be obtained by dividing the data to be processed into blocks. For example, if the data to be processed is a matrix to be processed, the data block to be processed may be a sub-matrix to be processed. The first data scale information may indicate the number of rows and columns of the matrix to be processed. The data block to be processed may indicate the number of rows and columns of the sub-matrix to be processed.

[0029] In operation S120, candidate hardware performance evaluation results are determined according to the candidate data block information.

[0030] In the disclosed embodiment, the method of determining the candidate hardware performance evaluation result based on the candidate data block information of the current simulated annealing cycle may be the same as the method of determining the current hardware performance evaluation result based on the to-be-evaluated data block information of the current simulation cycle.

[0031] In operation S130, data block information to be evaluated in a subsequent simulated annealing cycle of the current simulated annealing cycle is determined according to the candidate hardware performance evaluation result, the current hardware performance evaluation result, and the current temperature information.

[0032] In the disclosed embodiment, the evaluated data block information of the current simulated annealing cycle and the to-be-evaluated data block information of the subsequent simulated annealing cycle are different data block information. The to-be-evaluated data block information of the subsequent simulated annealing cycle can be one of one or more candidate data block information.

[0033] In an embodiment of the present disclosure, a candidate hardware performance evaluation result or a current hardware performance evaluation result can be processed according to the current temperature information. For example, if the first candidate hardware performance evaluation result is processed using the current temperature information, a first processed hardware performance evaluation result can be obtained. If the first processed hardware performance evaluation result is greater than the current hardware performance evaluation result, the candidate data block information corresponding to the first candidate hardware evaluation result in one or more candidate data block information can be used as the data block information to be evaluated in the subsequent simulated annealing cycle. For another example, the current temperature information can be multiplied by the first candidate hardware performance evaluation result to process the first candidate hardware performance evaluation result.

[0034] In the embodiment of the present disclosure, the above operations S110 to S130 may be performed on the data block information to be evaluated in different simulated annealing cycles until the hardware performance evaluation result meets the preset performance condition.

[0035] Through the disclosed embodiment, the data block information includes the first data scale information and the second data scale information, which respectively indicate the scale of the data after block division at different levels in the calculation process. Therefore, based on the simulated annealing algorithm, the good data block information can be efficiently and accurately determined, which can fully improve the utilization rate of the computing resources and memory access resources of the computing unit, fully improve the computing efficiency, and reduce the total computing time.

[0036] It can be understood that the above describes the method of the present disclosure, and the data block information will be further described below.

[0037] Figure 2A is a schematic diagram of multiple original matrices according to an embodiment of the present disclosure.

[0038] In an embodiment of the present disclosure, an artificial intelligence acceleration board may include multiple computing units and multiple communication units. The multiple computing units may be located in the same die or in different dies, and the present disclosure does not limit this. The multiple communication units may also be located in the same die or in different dies, and the present disclosure does not limit this.

[0039] like Figure 2A As shown, the artificial intelligence computing board may include a first computing unit, a second computing unit, a third computing unit, and a fourth computing unit. The artificial intelligence computing board may perform a matrix multiplication operation based on the first original matrix A20 and the second original matrix B20 to obtain a result matrix C20. For example, the matrix multiplication operation may be performed by the following formula:

[0040] (Formula 1)

[0041] It can be the first original matrix. It can be the second original matrix. It can be the result matrix. M can be the number of rows of the first original matrix or the number of rows of the result matrix. K can be the number of columns of the first original matrix or the number of rows of the second original matrix. N can be the number of columns of the second original matrix or the number of columns of the result matrix.

[0042] like Figure 2AAs shown, in order to make full use of the computing resources of multiple computing units, the first original matrix A20 and the second original matrix B20 can be divided into blocks respectively to obtain the data to be processed of the computing unit. The data to be processed can be a matrix to be processed. For example, the first original matrix A20 is divided into blocks to obtain a first matrix to be processed A201 and a first matrix to be processed A202. The second original matrix B20 is divided into blocks to obtain a second matrix to be processed B201 and a second matrix to be processed B202. The multiple matrices to be processed of the first computing unit include: a first matrix to be processed A201 and a second matrix to be processed B201. The multiple matrices to be processed of the second computing unit include: a first matrix to be processed A201 and a second matrix to be processed B202. The multiple matrices to be processed of the third computing unit include: a first matrix to be processed A202 and a second matrix to be processed B201. The multiple matrices to be processed of the fourth computing unit include: a first matrix to be processed A202 and a second matrix to be processed B202. It can be understood that the first matrix A201 to be processed and the second matrix B201 to be processed are multiplied to obtain the third matrix C201 to be processed. The first matrix A201 to be processed and the second matrix B202 to be processed are multiplied to obtain the third matrix C202 to be processed. The first matrix A202 to be processed and the second matrix B201 to be processed are multiplied to obtain the third matrix C203 to be processed. The first matrix A202 to be processed and the second matrix B202 to be processed are multiplied to obtain the third matrix C204 to be processed.

[0043] It is understandable that the capacity and computing power of the cache unit of the computing unit are limited. In order to improve computing efficiency, the data to be processed may be divided into multiple data blocks to be processed. The data blocks to be processed may be sub-matrices to be processed.

[0044] Figure 2B is a schematic diagram of a sub-matrix to be processed according to an embodiment of the present disclosure.

[0045] like Figure 2BAs shown, the first matrix to be processed A201, the first matrix to be processed A202, the second matrix to be processed B201 and the second matrix to be processed B202 can be divided into blocks respectively to obtain the sub-matrices to be processed of the calculation unit. For example, the first matrix to be processed A201 is divided into blocks to obtain the first sub-matrix to be processed A2011 and the first sub-matrix to be processed A2012. The first matrix to be processed A202 is divided into blocks to obtain the first sub-matrix to be processed A2021 and the first sub-matrix to be processed A2022. The second matrix to be processed B201 is divided into blocks to obtain the second sub-matrix to be processed B2011 and the second sub-matrix to be processed B2012. The second matrix to be processed B202 is divided into blocks to obtain the second sub-matrix to be processed B2021 and the second sub-matrix to be processed B2022. The multiple sub-matrices to be processed of the first calculation unit include: the first sub-matrix to be processed A2011, the first sub-matrix to be processed A2012, the second sub-matrix to be processed B2011 and the second sub-matrix to be processed B2012. The multiple sub-matrices to be processed of the second calculation unit include: the first sub-matrix to be processed A2011, the first sub-matrix to be processed A2012, the second sub-matrix to be processed B2021 and the second sub-matrix to be processed B2022. The sub-matrix to be processed of the third calculation unit includes: the first sub-matrix to be processed A2021, the first sub-matrix to be processed A2022, the second sub-matrix to be processed B2011 and the second sub-matrix to be processed B2012. The sub-matrix to be processed of the fourth calculation unit includes: the first sub-matrix to be processed A2021, the first sub-matrix to be processed A2022, the second sub-matrix to be processed B2021 and the second sub-matrix to be processed B2022.

[0046] It can be understood that in order to obtain the third matrix to be processed C201 of the result matrix, the first sub-matrix to be processed A2011 and the second matrix to be processed B2011 can be multiplied to obtain the third sub-matrix to be processed C2011. The first sub-matrix to be processed A2011 and the second matrix to be processed B2012 can also be multiplied to obtain the third sub-matrix to be processed C2012. The first sub-matrix to be processed A2012 and the second matrix to be processed B2011 can be multiplied to obtain the third sub-matrix to be processed C2013. The first sub-matrix to be processed A2012 and the second matrix to be processed B2012 can be multiplied to obtain the third sub-matrix to be processed C2014. Thus, after obtaining the third sub-matrix to be processed C2011, the third sub-matrix to be processed C2012, the third sub-matrix to be processed C2013, and the third sub-matrix to be processed C2014, the third matrix to be processed C201 can be obtained. It can also be understood that the manner of obtaining the third matrix to be processed C202, the third matrix to be processed C203 and the third matrix to be processed C204 is the same as or similar to the manner of obtaining the third matrix to be processed C201, and the present disclosure will not elaborate on it here.

[0047] In addition, in order to further optimize memory access, third data scale information can be determined, and the third data scale information can indicate the scale of the sub-data of the data block to be processed. For example, if the data block to be processed is a sub-matrix to be processed, the sub-matrix to be processed is divided into blocks to obtain a sub-matrix after splitting. The sub-matrix after splitting can be the sub-data of the data block to be processed. Through the embodiment of the present disclosure, the data block to be processed is divided into blocks again, which can further optimize memory access, improve the efficiency of memory access resource utilization, and avoid repeated memory access. When determining the data block information based on the simulated annealing algorithm, more levels of data scale are introduced, which can further reduce the memory access resource overhead and also help improve computing efficiency.

[0048] It can be understood that the above splitting of the original matrix into two to-be-processed matrices and the splitting of the to-be-processed matrix into two to-be-processed sub-matrices is only an example to illustrate the to-be-processed data and the to-be-processed data blocks. Figure 2A and Figure 2B The scale of the matrix to be processed or the submatrix to be processed shown may not fully utilize the computing resources or memory access resources. In order to fully utilize the computing resources and memory access resources, the simulated annealing algorithm can be used to determine the data block information to determine the scale of the matrix to be processed and the submatrix to be processed, which will be explained below.

[0049] In some embodiments, the data block information may include the above-mentioned first data scale information, second data scale information and third data scale information, and may also include memory access parameter information. The memory access parameter may include one or more parameters of the memory access unit. The memory access unit may be a direct memory access (DMA) unit. For example, in the first simulated annealing cycle of multiple simulated annealing cycles, a data block information may be randomly generated or preset as the data block information to be evaluated for the first simulated annealing cycle. One or more hyperparameters of the simulated annealing algorithm may also be initialized. One or more hyperparameters may include a temperature value, a cooling rate and a maximum number of simulated annealing cycles. For another example, the data block information may be expressed as [larger_block, large_block, block, load_store_config]. Larger_block may be the first data scale information. Large_block may be the second data scale information. Block may be the third data scale information. Load_store_config may be memory access parameter information.

[0050] In some embodiments, the first data scale information may be the number of data to be processed. The second data scale information may be the number of data blocks to be processed. The third data scale information may be: the number of sub-data of the data block to be processed. For example, if the data to be processed is a matrix to be processed and the scale of the original matrix is ​​known, the scale of the matrix to be processed may be determined according to the number of matrices to be processed and the scale of the original matrix. The scale of the sub-matrix to be processed may be determined according to the number of data blocks to be processed and the scale of the original matrix. The scale of the sub-matrix to be processed may be determined according to the number of sub-data of the data block to be processed, the scale of the sub-matrix after splitting may be determined.

[0051] In some embodiments, the hardware performance evaluation result may be determined based on the data block information.

[0052] In an embodiment of the present disclosure, the hardware performance evaluation result may include at least one of a fusion performance evaluation result, a computing resource utilization rate, a memory access resource utilization rate, and a computing duration. The fusion performance evaluation result may be determined based on the computing resource utilization rate and the memory access resource utilization rate.

[0053] In the disclosed embodiment, the computing resource utilization rate can be determined based on the first data scale information, the second data scale information, the third data scale information and the number of computing units. The computing resource utilization rate can be determined by the following operations: multiplying the second data scale information and the third data scale information to obtain a first product result. Dividing the first intermediate parameter by the number of computing units obtains the computing resource utilization rate. The first intermediate parameter is the smaller value of the first product result and the first data scale information. Through the disclosed embodiment, the computing resource utilization rate can be determined based on the data block information to determine an objective function value of the simulated annealing algorithm, and the simulated annealing algorithm can be effectively applied to the data block of the computing unit to determine a data block method with higher computational efficiency.

[0054] In the embodiment of the present disclosure, the memory access resource utilization rate can be determined based on the memory access parameter information, the fourth data scale information and the memory access bandwidth. The fourth data scale information can indicate the scale of the data loaded by the memory access unit each time. The memory access resource utilization rate can be determined by the following operations: multiplying the memory access parameter information and the fourth data scale information to obtain the second intermediate parameter. Dividing the second intermediate parameter by the memory access bandwidth, the memory access utilization rate is obtained. Through the embodiment of the present disclosure, the memory access resource utilization rate can be determined based on the data block information to determine another objective function value of the simulated annealing algorithm, and the simulated annealing algorithm can be effectively applied to the data block of the computing unit to determine a data block method with higher memory access efficiency.

[0055] In the embodiment of the present disclosure, the fusion performance evaluation result may be obtained by weighted fusion of computing resource utilization and memory access resource utilization. For example, the fusion performance evaluation result f may be determined by the following formula:

[0056] (Formula 2)

[0057] w hw It can be the first weight used to calculate resource utilization. mem It can be a second weight for memory access resource utilization. It can be the computing resource utilization. total_core can be the number of computing units. It can be memory access resource utilization. total_mem_bandwidth can be memory access bandwidth. Blocksize can be fourth data scale information. The first weight is, for example, 0.5, and the second weight is, for example, 0.5.

[0058] Through the embodiments of the present disclosure, the overall utilization of hardware resources can be determined based on data partitioning information to determine another objective function value of the simulated annealing algorithm, and the simulated annealing algorithm can be effectively applied to the data partitioning of the computing unit to determine a data partitioning method with higher computing efficiency and higher memory access efficiency.

[0059] In the disclosed embodiment, the calculation duration may be determined based on historical data block information, or a matrix multiplication operation may be performed based on the data block information to determine the calculation duration. For example, a fitting function may be established based on historical data block information and calculation duration. Based on the fitting function, the calculation duration corresponding to the data block information to be evaluated in the simulated annealing cycle is determined.

[0060] It can be understood that the above describes the hardware performance evaluation results of the present disclosure, and the preset performance conditions of the present disclosure will be described below.

[0061] In some embodiments, the preset performance condition includes at least one of a plurality of preset performance sub-conditions.

[0062] In an embodiment of the present disclosure, the preset performance sub-condition may be: the first hardware performance evaluation change rate is less than or equal to a preset change rate threshold. The first hardware performance evaluation change rate is determined based on the current hardware performance evaluation result and the previous hardware performance evaluation result. The previous hardware performance evaluation result is a hardware performance evaluation result corresponding to the evaluated data block information of the previous simulated annealing cycle. For example, the current fusion performance evaluation result may be subtracted from the previous fusion performance evaluation result to obtain a first difference value. Next, the first difference value may be divided by the previous fusion performance evaluation result to obtain the first hardware performance evaluation change rate. The first hardware performance evaluation change rate ΔQ may be determined by the following formula:

[0063] (Formula 3)

[0064] f_x i The result can be used to evaluate the current fusion performance. i-1 The results can be evaluated for previous fusion performance. is a function for finding the absolute value.

[0065] In the embodiment of the present disclosure, the preset performance sub-condition may also be: the computing resource utilization is greater than or equal to the first preset utilization threshold.

[0066] In the embodiment of the present disclosure, the preset performance sub-condition may also be: the memory access resource utilization is greater than or equal to a second preset utilization threshold.

[0067] In the embodiment of the present disclosure, the preset performance sub-condition may also be: the calculation duration is less than or equal to a preset duration threshold.

[0068] It can be understood that the above describes the preset performance conditions of the present disclosure, and the operations performed in the simulated annealing cycle will be further described below.

[0069] In some embodiments, the temperature information includes a temperature parameter value. The current temperature information includes a current temperature parameter value.

[0070] In some embodiments, the current hardware performance evaluation result can be determined based on the data block information to be evaluated in the current simulated annealing cycle. After the current hardware performance evaluation result is determined, the data block information to be evaluated in the current simulated annealing cycle can be used as the evaluated data block information in the current simulated annealing cycle.

[0071] In some embodiments, in some implementations of the above operation S110, in response to the current hardware performance evaluation result not meeting the preset performance condition and determining that the current temperature parameter value is greater than or equal to the preset temperature parameter threshold, the candidate data block information is determined according to the evaluated data block information. For example, in the case where the current hardware performance evaluation result does not meet the preset performance condition, it can be determined whether the current temperature parameter value is greater than or equal to the preset temperature parameter threshold to determine whether to perform related operations in the subsequent simulated annealing cycle.

[0072] In an embodiment of the present disclosure, candidate data segmentation information can be determined based on a neighborhood search algorithm according to the evaluated data segmentation information. For example, the evaluated data segmentation information is in a solution space. A subspace of a specified shape (such as a circle) is determined in the solution space as a neighborhood. A candidate data segmentation information is determined in the neighborhood. For another example, in the current simulated annealing cycle, the candidate data segmentation information may be data segmentation information that is different from the evaluated data segmentation information. The above description of data segmentation information also applies to candidate data segmentation information and evaluated data segmentation information, and the present disclosure will not repeat them here. Through an embodiment of the present disclosure, based on a neighborhood search algorithm, candidate data segmentation information can be efficiently determined, and it can also be made so that: the hardware performance corresponding to the candidate data segmentation information is more likely to be better than the hardware performance corresponding to the evaluated data segmentation information.

[0073] It can be understood that some methods for determining candidate data block information are described above, and some methods for determining candidate hardware performance evaluation results will be described below.

[0074] In some embodiments, in some implementations of the above operation S120, the candidate hardware performance evaluation result can be determined based on the candidate data block information. For example, in the current simulated annealing cycle, the candidate hardware performance evaluation result and the current hardware performance evaluation result can be different hardware performance evaluation results. The above method for determining the hardware performance evaluation result is also applicable to determining the candidate hardware performance evaluation result. For example, the above formula 2 can be used to determine the fusion performance evaluation result, computing resource utilization, and memory access resource utilization included in the candidate hardware performance evaluation result.

[0075] It can be understood that some methods for determining the candidate hardware performance evaluation results are described above, and some methods for determining the data block information to be evaluated in the subsequent simulated annealing cycle will be described below.

[0076] In some embodiments, in some implementations of the above operation S130, the acceptability evaluation result of the candidate data block information is determined based on the candidate hardware performance evaluation result, the current hardware performance evaluation result, and the current temperature information. A second difference value between the candidate hardware performance evaluation result and the current hardware performance evaluation result can be determined. The acceptability evaluation result can be determined based on the second difference value and the current temperature information.

[0077] In the embodiment of the present disclosure, the third intermediate parameter can be obtained by dividing the second hardware performance evaluation change rate by the current temperature parameter value. The second hardware performance evaluation change rate can be determined based on the candidate hardware performance evaluation result and the current hardware performance evaluation result. Next, the third intermediate parameter can be processed using an exponential function to obtain an evaluation result of the acceptability of the candidate data block information.

[0078] For example, the second difference value may be the difference value between the candidate fusion performance evaluation result and the current fusion performance evaluation result. The second difference value may be divided by the current fusion performance evaluation result to obtain the second hardware performance evaluation change rate. The second hardware performance evaluation change rate ΔE may be determined by the following formula:

[0079] (Formula 4)

[0080] f_x i The result can be used to evaluate the current fusion performance. i+1 It can be the candidate fusion performance evaluation result. i can be an integer greater than or equal to 1. Next, the second hardware performance evaluation change rate is divided by the current temperature parameter value to obtain a third intermediate parameter. The third intermediate parameter can be converted to a negative number to obtain the converted third intermediate parameter. The acceptability evaluation result P of the candidate data block information can be determined using the following formula:

[0081] (Formula 5)

[0082] T i It can be the current temperature parameter value.

[0083] Next, it can be determined whether the acceptability evaluation result is greater than or equal to a preset acceptability threshold. Through the disclosed embodiment, the acceptability evaluation result of the candidate data block information is determined based on the current temperature information, the candidate hardware performance evaluation result and the current hardware performance evaluation result, and the better data block information can be determined more efficiently.

[0084] In some embodiments, in some implementations of the above operation S130, in response to determining that the acceptability evaluation result of the candidate data block information is greater than or equal to the preset acceptability threshold, the candidate data block information is used as the data block information to be evaluated in the subsequent simulated annealing cycle of the current simulated annealing cycle. For example, in the subsequent simulated annealing cycle, operations S110 to S130 may also be performed.

[0085] In some embodiments, in other implementations of the above operation S130, in response to determining that the acceptability evaluation result of the candidate data block information is less than a preset acceptability threshold, the process may return to operation S110 to redetermine the candidate data block information.

[0086] It can be understood that some ways of determining the data block information to be evaluated in the subsequent simulated annealing cycle are described above. In order to perform the simulated annealing algorithm, subsequent temperature information can also be determined.

[0087] In some embodiments, the above method may further include: determining a current cooling rate based on the current hardware performance evaluation result. Based on the current cooling rate and the current temperature information, the subsequent temperature information may be obtained. For example, taking the memory access resource utilization rate included in the current hardware performance evaluation result as an example, if the memory access resource utilization rate is high, a larger cooling rate may be determined to more quickly determine better data partitioning information. If the memory access resource utilization rate is low, a smaller cooling rate may be determined to determine a more efficient data partitioning method. For another example, the subsequent temperature information may include a subsequent temperature parameter value, and the subsequent temperature parameter value T may be determined by the following formula: i+1 :

[0088] (Formula 5)

[0089] α can be the current cooling rate.

[0090] Through the embodiments of the present disclosure, the current cooling rate is determined based on the hardware performance evaluation results, and the temperature information can be dynamically updated to achieve a balance between accuracy and efficiency.

[0091] It can be understood that the cooling rate can also be a constant hyperparameter to statically update the temperature information.

[0092] It can be understood that the above description uses the current hardware performance evaluation result not meeting the preset performance condition as an example to illustrate the present disclosure. The following description will use the current hardware performance evaluation result meeting the preset performance condition as an example.

[0093] In some embodiments, the method may further include: in the current simulated annealing cycle, in response to determining that the current hardware performance evaluation result meets a preset performance condition, processing the data to be processed using the computing unit and the memory access unit according to the evaluated data block information.

[0094] In the embodiment of the present disclosure, according to the data block information, the first to-be-processed data block and the second to-be-processed data block can be provided to the computing unit by using the memory access unit. The scale of at least one of the first to-be-processed data block and the second to-be-processed data block is consistent with the second data scale information of the evaluated data block information. For example, there may be multiple data to be processed. The data to be processed may be a matrix to be processed. The multiple matrices to be processed may include a first to-be-processed matrix and a second to-be-processed matrix. According to the scale indicated by the second data scale information, the first to-be-processed sub-matrix of the first to-be-processed matrix may be loaded, and the second to-be-processed sub-matrix of the second to-be-processed matrix may also be loaded, so that the computing unit performs a matrix multiplication operation. The following will be combined with Figure 3 Provide explanation.

[0095] Figure 3 Schematic diagram of the execution of matrix multiplication operation and pass operation according to one embodiment of the present disclosure.

[0096] In the embodiment of the present disclosure, a computing unit may be used to multiply the first data block to be processed and the second data block to be processed to obtain a third data block to be processed. The data block to be processed may be a sub-matrix to be processed.

[0097] like Figure 3 As shown, from time t301 to time t302, the first calculation unit can calculate the third sub-matrix to be processed C3011. It can be understood that the third sub-matrix to be processed C3011 can be obtained by multiplying the first sub-matrix to be processed A2011 and the second sub-matrix to be processed B2011. It can be understood that Figure 2B The size of the sub-matrices to be processed is shown only as an example. Figure 2B The calculation of the sub-matrix to be processed is only an example.

[0098] like Figure 3 As shown, from time t301 to time t302, the second calculation unit can calculate the third sub-matrix to be processed C3021. It can be understood that the third sub-matrix to be processed C3021 can be obtained by multiplying the first sub-matrix to be processed A2011 and the second sub-matrix to be processed B2021.

[0099] In the embodiment of the present disclosure, the computing unit may be used to provide the communication signal corresponding to the third data block to be processed to the communication unit. Figure 3 As shown, the first calculation unit can provide the communication signal corresponding to the third sub-matrix to be processed C3011 to the first communication unit. The second calculation unit can provide the communication signal corresponding to the third sub-matrix to be processed C3021 to the second communication unit.

[0100] In the embodiment of the present disclosure, in response to acquiring the communication signal, a communication operation is performed using the communication unit to provide the third to-be-processed data block to at least one communication unit. Figure 3 As shown, from time t302 to time t303, after the first communication unit obtains the communication signal, it can perform the communication operation com3011 to provide the third sub-matrix to be processed C3011 to the second communication unit. After the second communication unit obtains the communication signal, it can perform the communication operation com3021 to provide the third sub-matrix to be processed C3021 to the first communication unit.

[0101] In the embodiment of the present disclosure, while the communication unit performs the communication operation, the computing unit can continue to perform the matrix multiplication operation. Figure 3 As shown, from time t302 to time t303, the first calculation unit can calculate the third sub-matrix C3012 to be processed, and the second calculation unit can calculate the third sub-matrix C3022 to be processed. It can be understood that the third sub-matrix C3012 to be processed can be obtained by multiplying the first sub-matrix A2011 to be processed and the second sub-matrix B2012 to be processed. The third sub-matrix C3022 to be processed can be obtained by multiplying the first sub-matrix A2011 to be processed and the second sub-matrix B2022 to be processed. Through the embodiments of the present disclosure, the matrix multiplication operation and the communication operation can be performed synchronously, which can effectively reduce the overall calculation time and improve the calculation efficiency and communication efficiency.

[0102] In addition, after calculating the third sub-matrix C3012 to be processed, the first computing unit may provide the communication signal corresponding to the third sub-matrix C3012 to be processed to the first communication unit. After calculating the third sub-matrix C3022 to be processed, the second computing unit may provide the communication signal corresponding to the third sub-matrix C3022 to be processed to the second communication unit.

[0103] like Figure 3As shown, from time t303 to time t304, after the first communication unit obtains the communication signal, the communication operation com3012 can be performed to provide the third sub-matrix C3012 to be processed to the second communication unit. After the second communication unit obtains the communication signal, the communication operation com3022 can be performed to provide the third sub-matrix C3022 to be processed to the first communication unit. In addition, from time t303 to time t304, the first calculation unit can calculate the third sub-matrix C3013 to be processed, and the second calculation unit can calculate the third sub-matrix C3023 to be processed. It can be understood that the third sub-matrix C3013 to be processed can be obtained by multiplying the above-mentioned first sub-matrix A2012 to be processed and the above-mentioned second sub-matrix B2011 to be processed. The third sub-matrix C3023 to be processed can be obtained by multiplying the above-mentioned first sub-matrix A2012 to be processed and the above-mentioned second sub-matrix B2021 to be processed. It can also be understood that in the process of multiplying the first submatrix A2012 to be processed and the second submatrix B2011 to be processed, in order to improve the calculation efficiency and memory access efficiency, the first submatrix A2012 to be processed and the second submatrix B2011 to be processed are divided into blocks again according to the third scale information, and the scale of the submatrix after the splitting of the first submatrix A2012 to be processed and the scale of the submatrix after the splitting of the second submatrix B2011 to be processed can be consistent with the third scale information. Matrix multiplication calculation is performed based on the split submatrix to obtain the third submatrix C3023 to be processed.

[0104] In addition, after calculating the third sub-matrix C3013 to be processed, the first computing unit can provide the communication signal corresponding to the third sub-matrix C3013 to be processed to the first communication unit. After calculating the third sub-matrix C3023 to be processed, the second computing unit can provide the communication signal corresponding to the third sub-matrix C3023 to be processed to the second communication unit.

[0105] like Figure 3As shown, from time t304 to time t305, after the first communication unit obtains the communication signal, the communication operation com3013 can be performed to provide the third sub-matrix C3013 to be processed to the second communication unit. After the second communication unit obtains the communication signal, the communication operation com3023 can be performed to provide the third sub-matrix C3023 to be processed to the first communication unit. In addition, from time t303 to time t304, the first calculation unit can calculate the third sub-matrix C3014 to be processed, and the second calculation unit can calculate the third sub-matrix C3024 to be processed. It can be understood that the third sub-matrix C3014 to be processed can be obtained by multiplying the above-mentioned first sub-matrix A2012 to be processed and the above-mentioned second sub-matrix B2012 to be processed. The third sub-matrix C3024 to be processed can be obtained by multiplying the above-mentioned first sub-matrix A2012 to be processed and the above-mentioned second sub-matrix B2022 to be processed.

[0106] In addition, after calculating the third sub-matrix C3014 to be processed, the first computing unit may provide the communication signal corresponding to the third sub-matrix C3014 to be processed to the first communication unit. After calculating the third sub-matrix C3024 to be processed, the second computing unit may provide the communication signal corresponding to the third sub-matrix C3024 to be processed to the second communication unit.

[0107] From time t305 to time t306, after the first communication unit obtains the communication signal, it can perform the communication operation com3014 to provide the third sub-matrix to be processed C3014 to the second communication unit. After the second communication unit obtains the communication signal, it can perform the communication operation com3024 to provide the third sub-matrix to be processed C3024 to the first communication unit.

[0108] It can be understood that the method of the present disclosure is described above, and the device of the present disclosure will be described below.

[0109] Figure 4 is a block diagram of a data processing device according to an embodiment of the present disclosure.

[0110] like Figure 4 As shown, the apparatus 400 may include a first determination module 410 , a second determination module 420 , and a third determination module 430 .

[0111] The first determination module 410 is used to determine candidate data partition information of the computing unit according to the evaluated data partition information of the computing unit in the current simulated annealing cycle in response to the current hardware performance evaluation result not meeting the preset performance condition.

[0112] The second determination module 420 is used to determine the candidate hardware performance evaluation result according to the candidate data block information.

[0113] The third determination module 430 is used to determine the to-be-evaluated data block information of the subsequent simulated annealing cycle of the current simulated annealing cycle according to the candidate hardware performance evaluation result, the current hardware performance evaluation result and the current temperature information.

[0114] In the disclosed embodiment, the evaluated data block information of the current simulated annealing cycle and the data block information to be evaluated in the subsequent simulated annealing cycle are different data block information, respectively. The data block information includes first data scale information and second data scale information. The first data scale information is used to indicate the scale of the data to be processed of the computing unit, and the second data scale information is used to indicate the scale of the data block to be processed of the computing unit. The data block to be processed is obtained by dividing the data to be processed.

[0115] In some embodiments, the data block information further includes at least one of third data scale information and memory access parameter information, and the third data scale information is used to indicate the scale of sub-data of the data block to be processed.

[0116] In some embodiments, the current hardware performance evaluation result is a hardware performance evaluation result corresponding to the evaluated data block information of the current simulated annealing cycle, and the hardware performance evaluation result includes at least one of the fusion performance evaluation result, the computing resource utilization, the memory access resource utilization, and the computing duration, and the fusion performance evaluation result is determined based on the computing resource utilization and the memory access resource utilization. The preset performance condition includes at least one of a plurality of preset performance sub-conditions, and the plurality of preset performance sub-conditions include: the first hardware performance evaluation change rate is less than or equal to the preset change rate threshold. The first hardware performance evaluation change rate is determined based on the current hardware performance evaluation result and the previous hardware performance evaluation result. The previous hardware performance evaluation result is a hardware performance evaluation result corresponding to the evaluated data block information of the previous simulated annealing cycle. The computing resource utilization is greater than or equal to the first preset utilization threshold. The memory access resource utilization is greater than or equal to the second preset utilization threshold. The computing duration is less than or equal to the preset duration threshold.

[0117] In some embodiments, computing resource utilization is determined based on first data scale information, second data scale information, third data scale information and the number of computing units, and memory access resource utilization is determined based on memory access parameter information, fourth data scale information and memory access bandwidth, where the fourth data scale information is the scale of data loaded by the memory access unit.

[0118] In some embodiments, the computing resource utilization is determined by performing related operations according to the first data scale information, the second data scale information, the third data scale information and the number of computing units by the following submodules: a first multiplication submodule, for multiplying the second data scale information and the third data scale information to obtain a first product result. A first division submodule, for dividing the number of computing units by a first intermediate parameter to obtain the computing resource utilization. The first intermediate parameter is the smaller value of the first product result and the first data scale information.

[0119] In some embodiments, the memory access utilization is determined by the following submodules performing related operations according to the memory access parameter information, the fourth data scale information and the memory access bandwidth: a second multiplication submodule, used to multiply the memory access parameter information and the fourth data scale information to obtain a second intermediate parameter. A second division submodule, used to divide the second intermediate parameter by the memory access bandwidth to obtain the memory access utilization.

[0120] In some embodiments, the current temperature information includes a current temperature parameter value. The first determination module includes: a first determination submodule, configured to determine candidate data block information based on the evaluated data block information in response to the current hardware performance evaluation result not meeting the preset performance condition and determining that the current temperature parameter value is greater than or equal to the preset temperature parameter threshold.

[0121] In some embodiments, the first determination module further includes: a second determination submodule, configured to determine candidate data segment information based on a neighborhood search strategy according to the evaluated data segment information.

[0122] In some embodiments, the third determination module includes: a third determination submodule, configured to determine the acceptability evaluation result of the candidate data block information according to the candidate hardware performance evaluation result, the current hardware performance evaluation result and the current temperature information; and a fourth determination submodule, configured to use the candidate data block information as the data block information to be evaluated in the subsequent simulated annealing cycle of the current simulated annealing cycle in response to determining that the acceptability evaluation result of the candidate data block information is greater than or equal to a preset acceptability threshold.

[0123] In some embodiments, the current temperature information includes a current temperature parameter value. The third determination submodule includes: a division unit, which is used to divide the second hardware performance evaluation change rate by the current temperature parameter value to obtain a third intermediate parameter. The second hardware performance evaluation change rate is determined based on the candidate hardware performance evaluation result and the current hardware performance evaluation result. An acquisition unit is used to process the third intermediate parameter using an exponential function to obtain an acceptability evaluation result of the candidate data block information.

[0124] In some embodiments, the apparatus further comprises: a fourth obtaining module, configured to determine the current cooling rate according to the current hardware performance evaluation result; and an obtaining module, configured to obtain subsequent temperature information according to the current cooling rate and the current temperature information.

[0125] In some embodiments, the above-mentioned device also includes: a data block transmission module, which is used to provide the first data block to be processed and the second data block to be processed to the computing unit in response to the current hardware performance evaluation result satisfying the preset performance condition in the current simulated annealing cycle, according to the evaluated data block information, using the memory access unit. The scale of at least one of the first data block to be processed and the second data block to be processed is consistent with the second data scale information of the evaluated data block information. A multiplication module, which is used to multiply the first data block to be processed and the second data block to be processed by the computing unit to obtain a third data block to be processed. A signal transmission module, which is used to provide a communication signal corresponding to the third data block to be processed to the communication unit by using the computing unit. An execution module, which is used to perform a communication operation by using the communication unit in response to obtaining the communication signal, so as to provide the third data block to be processed to at least one communication unit.

[0126] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0127] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0128] Figure 5 A schematic block diagram of an example electronic device 500 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0129] like Figure 5As shown, the device 500 includes a processing unit 501, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 502 or a computer program loaded from a storage unit 508 to a random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the device 500 can also be stored. The processing unit 501, the ROM 502, and the RAM 503 are connected to each other via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0130] A number of components in the device 500 are connected to the I / O interface 505, including: an input unit 506, such as a keyboard, a mouse, etc.; an output unit 507, such as various types of displays, speakers, etc.; a storage unit 508, such as a disk, an optical disk, etc.; and a communication unit 509, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 509 allows the device 500 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0131] The processing unit 501 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processing unit 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processing unit 501 performs the various methods and processes described above, such as a data processing method. For example, in some embodiments, the data processing method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 508. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 500 via the ROM 502 and / or the communication unit 509. When the computer program is loaded into the RAM 503 and executed by the processing unit 501, one or more steps of the data processing method described above may be performed. Alternatively, in other embodiments, the processing unit 501 may be configured to execute the data processing method in any other appropriate manner (eg, by means of firmware).

[0132] Various embodiments of the systems and techniques described above herein may be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard parts (ASSPs), system on chip systems (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0133] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0134] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. More specific examples of machine-readable storage media may include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories, read-only memories, erasable programmable read-only memories (EPROM) or flash memories, optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0135] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a cathode ray tube (CRT) display or a liquid crystal display (LCD)) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0136] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a Local Area Network (LAN), a Wide Area Network (WAN), and the Internet.

[0137] A computer system may include clients and servers. Clients and servers are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship to each other.

[0138] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0139] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A data processing method, comprising: In the current simulated annealing cycle, in response to the current hardware performance evaluation result not meeting the preset performance condition, determining the candidate data partition information of the computing unit according to the evaluated data partition information of the computing unit; Determine a candidate hardware performance evaluation result according to the candidate data block information; as well as Determine the data block information to be evaluated in the subsequent simulated annealing cycle of the current simulated annealing cycle according to the candidate hardware performance evaluation result, the current hardware performance evaluation result and the current temperature information, Among them, the evaluated data block information of the current simulated annealing cycle and the data block information to be evaluated in the subsequent simulated annealing cycle are different data block information, and the data block information includes first data scale information and second data scale information. The first data scale information is used to indicate the scale of the data to be processed by the computing unit, and the second data scale information is used to indicate the scale of the data block to be processed by the computing unit. The data block to be processed is obtained by blocking the data to be processed.

2. The method according to claim 1, wherein: The data block information further includes at least one of third data scale information and memory access parameter information, and the third data scale information is used to indicate the scale of the sub-data of the data block to be processed.

3. The method according to claim 2, wherein: The current hardware performance evaluation result is the hardware performance evaluation result corresponding to the evaluated data block information of the current simulated annealing cycle, The hardware performance evaluation result includes at least one of a fusion performance evaluation result, a computing resource utilization rate, a memory access resource utilization rate, and a computing duration, wherein the fusion performance evaluation result is determined based on the computing resource utilization rate and the memory access resource utilization rate. The preset performance condition includes at least one of a plurality of preset performance sub-conditions, and the plurality of preset performance sub-conditions include: a first hardware performance evaluation change rate that is less than or equal to a preset change rate threshold, wherein the first hardware performance evaluation change rate is determined based on the current hardware performance evaluation result and a previous hardware performance evaluation result, wherein the previous hardware performance evaluation result is a hardware performance evaluation result corresponding to the evaluated data block information of the previous simulated annealing cycle; The computing resource utilization is greater than or equal to a first preset utilization threshold; The memory access resource utilization is greater than or equal to a second preset utilization threshold; The calculated duration is less than or equal to a preset duration threshold.

4. The method according to claim 3, wherein: The computing resource utilization is determined based on the first data scale information, the second data scale information, the third data scale information and the number of the computing units, and the memory access resource utilization is determined based on the memory access parameter information, the fourth data scale information and the memory access bandwidth, and the fourth data scale information is the scale of data loaded by the memory access unit.

5. The method according to claim 4, wherein: The computing resource utilization is determined according to the first data scale information, the second data scale information, the third data scale information and the number of the computing units by the following operations: Multiplying the second data scale information and the third data scale information to obtain a first product result; The computing resource utilization is obtained by dividing a first intermediate parameter by the number of the computing units, wherein the first intermediate parameter is a smaller value between the first product result and the first data scale information.

6. The method according to claim 4, wherein: The memory access utilization rate is determined according to the memory access parameter information, the fourth data size information and the memory access bandwidth by the following operations: Multiplying the memory access parameter information and the fourth data size information to obtain a second intermediate parameter; The memory access utilization rate is obtained by dividing the second intermediate parameter by the memory access bandwidth.

7. The method according to claim 1, wherein: The current temperature information includes the current temperature parameter value, In response to the current hardware performance evaluation result not meeting the preset performance condition, determining the candidate data partition information of the computing unit according to the evaluated data partition information of the computing unit includes: In response to the current hardware performance evaluation result not satisfying a preset performance condition and determining that the current temperature parameter value is greater than or equal to a preset temperature parameter threshold, the candidate data block information is determined according to the evaluated data block information.

8. The method according to claim 1, wherein: Determining the candidate data block information according to the evaluated data block information of the computing unit includes: According to the evaluated data block information, the candidate data block information is determined based on a neighborhood search strategy.

9. The method according to claim 1, wherein: The determining of the data block information to be evaluated in the subsequent simulated annealing cycle of the current simulated annealing cycle includes: Determining an acceptability evaluation result of the candidate data block information according to the candidate hardware performance evaluation result, the current hardware performance evaluation result and the current temperature information; and In response to determining that the acceptability evaluation result of the candidate data block information is greater than or equal to a preset acceptability threshold, the candidate data block information is used as the data block information to be evaluated in a subsequent simulated annealing cycle of the current simulated annealing cycle.

10. The method according to claim 9, wherein: The current temperature information includes the current temperature parameter value, Determining the acceptability evaluation result of the candidate data block information according to the candidate hardware performance evaluation result, the current hardware performance evaluation result and the current temperature information includes: Dividing the second hardware performance evaluation change rate by the current temperature parameter value to obtain a third intermediate parameter, wherein the second hardware performance evaluation change rate is determined according to the candidate hardware performance evaluation result and the current hardware performance evaluation result; The third intermediate parameter is processed by using an exponential function to obtain an acceptability evaluation result of the candidate data block information.

11. The method according to claim 1, further comprising: Determining a current cooling rate according to the current hardware performance evaluation result; The subsequent temperature information is obtained according to the current cooling rate and the current temperature information.

12. The method according to claim 1, further comprising: In the current simulated annealing cycle, in response to the current hardware performance evaluation result satisfying the preset performance condition, according to the evaluated data block information, a first to-be-processed data block and a second to-be-processed data block are provided to the computing unit using a memory access unit, wherein the size of at least one of the first to-be-processed data block and the second to-be-processed data block is consistent with the second data size information of the evaluated data block information, multiplying the first to-be-processed data block and the second to-be-processed data block by the calculation unit to obtain a third to-be-processed data block; Using the computing unit, providing a communication signal corresponding to the third data block to be processed to a communication unit; In response to acquiring the communication signal, a communication operation is performed using the communication unit to provide the third to-be-processed data block to at least one of the communication units.

13. A data processing device, comprising: A first determination module is used to determine candidate data block information of the computing unit according to the evaluated data block information of the computing unit in response to the current hardware performance evaluation result not meeting the preset performance condition in the current simulated annealing cycle; A second determination module is used to determine a candidate hardware performance evaluation result according to the candidate data block information; The third determining module is used to determine the data block information to be evaluated in the subsequent simulated annealing cycle of the current simulated annealing cycle according to the candidate hardware performance evaluation result, the current hardware performance evaluation result and the current temperature information, Among them, the evaluated data block information of the current simulated annealing cycle and the data block information to be evaluated in the subsequent simulated annealing cycle are different data block information, and the data block information includes first data scale information and second data scale information. The first data scale information is used to indicate the scale of the data to be processed by the computing unit, and the second data scale information is used to indicate the scale of the data block to be processed by the computing unit. The data block to be processed is obtained by blocking the data to be processed.

14. The device according to claim 13, wherein: The data block information further includes at least one of third data scale information and memory access parameter information, and the third data scale information is used to indicate the scale of the sub-data of the data block to be processed.

15. The device according to claim 14, wherein: The current hardware performance evaluation result is the hardware performance evaluation result corresponding to the evaluated data block information of the current simulated annealing cycle, The hardware performance evaluation result includes at least one of a fusion performance evaluation result, a computing resource utilization rate, a memory access resource utilization rate, and a computing duration, wherein the fusion performance evaluation result is determined based on the computing resource utilization rate and the memory access resource utilization rate. The preset performance condition includes at least one of a plurality of preset performance sub-conditions, and the plurality of preset performance sub-conditions include: a first hardware performance evaluation change rate that is less than or equal to a preset change rate threshold, wherein the first hardware performance evaluation change rate is determined based on the current hardware performance evaluation result and a previous hardware performance evaluation result, wherein the previous hardware performance evaluation result is a hardware performance evaluation result corresponding to the evaluated data block information of the previous simulated annealing cycle; The computing resource utilization is greater than or equal to a first preset utilization threshold; The memory access resource utilization is greater than or equal to a second preset utilization threshold; The calculated duration is less than or equal to a preset duration threshold.

16. The apparatus according to claim 13, further comprising: A fourth determination module, configured to determine a current cooling rate according to the current hardware performance evaluation result; The obtaining module is used to obtain subsequent temperature information according to the current cooling rate and the current temperature information.

17. The apparatus according to claim 13, further comprising: a data block transmission module, configured to provide, in the current simulated annealing cycle, in response to the current hardware performance evaluation result satisfying a preset performance condition, a first to-be-processed data block and a second to-be-processed data block to the computing unit using a memory access unit according to the evaluated data block information, wherein the size of at least one of the first to-be-processed data block and the second to-be-processed data block is consistent with the second data size information of the evaluated data block information, a multiplication module, configured to use the calculation unit to multiply the first to-be-processed data block and the second to-be-processed data block to obtain a third to-be-processed data block; a signal transmission module, configured to provide a communication signal corresponding to the third data block to be processed to a communication unit by using the calculation unit; An execution module is used for executing a communication operation using the communication unit in response to acquiring the communication signal, so as to provide the third data block to be processed to at least one of the communication units.

18. An electronic device, comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 12.

19. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 12.

20. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 12.

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