Bandwidth extension system

Abstract

The invention provides a bandwidth expansion system with a phase noise elimination function, which comprises a main signal source, an auxiliary signal source, a signal mixer connected to the output of the main signal source and the output of the auxiliary signal source, a frequency multiplier connected to the output of the signal mixer, and a reference signal source connected to the input of the main signal source, and a fractional divider connected between the primary signal source output and the secondary signal source input. According to the bandwidth expansion system provided by the invention, the overall fractional tuning bandwidth can be expanded from the main signal source, and the main signal source can be optimized for phase noise cancellation and low power consumption in a narrow tuning range. In addition, the phase correlation and phase noise cancellation technology provided by the invention can help to eliminate the phase noise of the main signal source, and improve the phase noise of the system when the required fractional bandwidth is improved.

Description

Technical Field

[0001] The present invention generally relates to bandwidth extension technology and more particularly to a bandwidth extension system with phase noise cancellation and frequency multiplication functions. Background Art

[0002] Broadband and low phase noise RF sources are essential for various applications such as submillimeter radar and ranging systems. There are two common methods to generate high-frequency signals using low-frequency reference signal sources (such as crystal oscillators). Figure 1A As shown in FIG. 1 , one method is based on a direct digital frequency synthesizer (DDFS) to achieve ideal phase accumulation through a digital accumulator, where the frequency control word (FCW) is set in the digital domain as the ratio between the desired signal frequency and the reference signal frequency. Then, a read-only-memory (ROM) and a high-speed digital-to-analog converter (DAC) with a low-pass filter (LPF) are used to encode the phase into a sinusoidal signal in the voltage domain. However, due to the limitation of the reference clock frequency, the output frequency of this method is usually only a few hundred million Hertz (Hz). Moreover, high-speed DACs usually consume a lot of power and introduce significant phase noise.

[0003] like Figure 1B As shown in Figure 1, another approach is to use a digitally-controlled-oscillator (DCO) or voltage-controlled-oscillator (VCO) that can operate in the millimeter-wave frequency band. The frequency drift of the open-loop DCO can be calibrated by a properly controlled negative feedback mechanism inside the phase-locked loop (PLL). However, in order to reduce phase noise, these VCOs or DCOs are usually built using narrow-band high-Q LC resonators. Alternatively, an analog PLL with a high-gain variable capacitor can be used to achieve a wide tuning range. However, in order to maintain a constant loop gain, the current of the charge pump or the gain of other components in the loop must be reduced proportionally, which inevitably deteriorates the noise performance of the phase-locked loop. Moreover, the high gain of the VCO also makes the synthesizer sensitive to noise coupled from the substrate and the supply voltage.

[0004] Some techniques use a DCO with a linear switched-capacitor array (SCA) instead of a high-gain variable capacitor, but are still limited by the trade-off between tuning range and tuning resolution. Some bandwidth extension techniques use a single narrow-bandwidth LC VCO to multiplex the output frequency to different frequency dividers and multipliers. By changing the relative polarity between the two coupled oscillators, the equivalent inductance and capacitance can be adjusted without tuning the SCA or variable capacitor. However, for radar applications, mode switching with port swapping cannot be used because it would cause frequency modulation discontinuities in continuous chirps. Therefore, there is still a significant trade-off between tuning bandwidth and phase noise. Summary of the invention

[0005] The object of the present invention is to provide a broadband low phase noise frequency generation system with a large bandwidth to obtain high ranging resolution and a large chirp rate, thereby obtaining a high signal-to-noise ratio, low phase noise to extend the detection range, improve accuracy, enhance target discrimination, and reduce the possibility of false alarms.

[0006] According to a first aspect of the present invention, a bandwidth extension system is provided, comprising: a main signal source configured to receive a first frequency control word and a first reference signal, and synthesize a signal having a center frequency f according to the first frequency control word and the first reference signal o and fractional bandwidth Δf / f o A secondary signal source, configured to receive a second frequency control word and a second reference signal, and synthesize a signal having a center frequency f according to the second frequency control word and the second reference signal o (1-1 / K) secondary signal, wherein K is a real number greater than 1; a signal mixer configured to mix the primary signal and the secondary signal to generate a signal having a center frequency f o / K and fractional bandwidth K·Δf / f o down-converted signal.

[0007] According to a second aspect of the present invention, a bandwidth extension system is provided, comprising: a main signal source, configured to receive a first frequency control word and a first reference signal, and synthesize a signal having a center frequency f according to the first frequency control word and the first reference signal o and fractional bandwidth Δf / f o A secondary signal source, configured to receive a second frequency control word and a second reference signal, and synthesize a signal having a center frequency f according to the second frequency control word and the second reference signal o (1-1 / K) secondary signal, wherein K is a real number greater than 1; a signal mixer configured to mix the primary signal and the secondary signal to generate a signal having a center frequency f o / K and fractional bandwidth K·Δf / fo A down-converted signal; a frequency multiplier configured to multiply the down-converted signal by a factor N to generate a signal having a center frequency N·f o / K and a frequency-multiplied signal with an absolute bandwidth N·Δf, where N is an integer greater than 1.

[0008] According to a third aspect of the present invention, a bandwidth extension system is provided, comprising: a main signal source, configured to receive a first frequency control word and a first reference signal, and synthesize a signal having a center frequency f according to the first frequency control word and the first reference signal o and fractional bandwidth Δf / f o A first frequency multiplier configured to multiply the main signal by a factor N1 to generate a frequency having a center frequency N1·f o and fractional bandwidth Δf / f o A first frequency multiplied signal, wherein N1 is an integer greater than 1; a secondary signal source, configured to receive a second frequency control word and a second reference signal, and synthesize a signal having a center frequency f according to the second frequency control word and the second reference signal o (1-1 / K) secondary signal, wherein K is a real number greater than 1; a second frequency multiplier, configured to multiply the secondary signal by a factor N2 to generate a secondary signal having a center frequency N2·f o A second frequency multiplied signal of (1-1 / K), wherein N2 is an integer greater than 1; a signal mixer configured to mix the first frequency multiplied signal and the second frequency multiplied signal to generate a second frequency multiplied signal having a center frequency f o ·(N1-N2+N2 / K) and a down-converted signal with an absolute bandwidth of N1·Δf.

[0009] The bandwidth extension system provided by the present invention can extend the overall fractional tuning bandwidth from the main signal source, and the main signal source can be optimized for phase noise cancellation and low power consumption within a narrow tuning range. In addition, the phase correlation and phase noise cancellation techniques provided by the present invention can help eliminate the phase noise of the main signal source and improve the system phase noise when the required fractional bandwidth is increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present invention will be described in more detail below and with reference to the accompanying drawings, in which:

[0011] Figure 1A and 1B Two prior techniques for generating high frequency signals using low frequency reference signal sources are shown;

[0012] Figure 2A A circuit block diagram of a bandwidth extension system according to an embodiment of the present invention is shown;

[0013] Figure 2BA circuit block diagram of a bandwidth extension system with a frequency doubling function according to another embodiment of the present invention is shown;

[0014] Figure 3A A circuit block diagram of a bandwidth extension system with a phase noise cancellation function according to another embodiment of the present invention is shown;

[0015] Figure 3B A circuit block diagram of a bandwidth extension system with phase noise cancellation and frequency multiplication functions according to another embodiment of the present invention is shown;

[0016] Figure 4A A circuit block diagram of a bandwidth extension system with a phase noise cancellation function according to another embodiment of the present invention is shown;

[0017] Figure 4B A circuit block diagram of a bandwidth extension system with phase noise cancellation and frequency multiplication functions according to another embodiment of the present invention is shown;

[0018] Figure 5 A circuit block diagram of a bandwidth extension system with a phase noise cancellation function according to another embodiment of the present invention is shown;

[0019] Figure 6 shows a circuit diagram of a fractional frequency divider according to an embodiment of the present invention;

[0020] Figure 7 shows a circuit diagram of an auxiliary signal source according to an embodiment of the present invention;

[0021] Figure 8 shows a schematic diagram of an example bandwidth extension system design fabricated in a 28nm CMOS process to demonstrate the effectiveness of bandwidth extension and phase noise cancellation;

[0022] Fig. 9 Shows the Figure 8 A photograph of a top view of the IC chip used to fabricate the example bandwidth extension system design;

[0023] Fig. 10A and 10B The V MAIN and V MIXER Chirp spectrogram;

[0024] Fig.11 shows the V of the bandwidth extension system with phase noise cancellation MPLL 、V APLL and V MIXER The measured phase noise spectrum of

[0025] Fig.12The V of the bandwidth extension system with and without phase noise cancellation is shown. MIXER Measured phase noise spectrum. DETAILED DESCRIPTION

[0026] The following is a detailed description of the preferred embodiment of the present invention. It will be apparent to those skilled in the art that modifications, including additions and / or substitutions, may be made to the described embodiments without departing from the scope and spirit of the present invention. Specific details may be omitted in order not to obscure the present invention; however, this article is written to enable those skilled in the art to implement the teachings herein without undue experimentation.

[0027] Figure 2A FIG. 1 is a circuit block diagram of a bandwidth extension system 100A according to an embodiment of the present invention. As shown in the figure, the bandwidth extension system 100A includes a main signal source 110 , a sub-signal source 120 , and a signal mixer 130 connected to the main signal source 110 and the sub-signal source 120 .

[0028] The main signal source 110 is configured to receive a first frequency control word FCW1 and a first reference signal V REF1 , and according to the first frequency control word FCW1 and the first reference signal V REF1 Synthesized main signal V MAIN . Main signal V MAIN With center frequency f o and fractional bandwidth Δf / f o The frequency control word FCW1 is used to set the ratio between the output frequency of the main signal source and the reference frequency (i.e. the main signal V MAIN and the first reference signal V REF1 ratio between the frequencies of

[0029] The auxiliary signal source 120 is configured to receive the second frequency control word FCW2 and the second reference signal V REF2 , and according to the second frequency control word FCW2 and the second reference signal V REF2 Synthesized secondary signal V AUX . Secondary signal V AUX With center frequency f o (1-1 / K), where K is a real number greater than 1. The frequency control word FCW2 is used to set the ratio between the output frequency of the auxiliary signal source and the reference frequency (i.e. the auxiliary signal V AUX and the second reference signal V REF2 ratio between the frequencies of

[0030] The signal mixer 130 is configured to mix the main signal V MAIN and the secondary signal V AUX To generate the down-converted signal V MIXER. Down-converted signal V MIXER With center frequency f o / K and fractional bandwidth K·Δf / f o .

[0031] The bandwidth extension system 100A may further include a first FCW generator (not shown) configured to provide a first frequency control word FCW1 to the main signal source 110 , and a second FCW generator (not shown) configured to provide a second frequency control word FCW2 to the slave signal source 120 .

[0032] The bandwidth extension system 100A may further include: a first reference signal source (not shown) connected to the main signal source 110, configured to provide a first reference signal V REF1 and a second reference signal source (not shown) connected to the auxiliary signal source 120, configured to provide a second reference signal V to the auxiliary signal source 120 REF2 .

[0033] Figure 2B FIG. 2 shows a circuit block diagram of a bandwidth extension system 100B with a frequency multiplication function according to another embodiment of the present invention. The bandwidth extension system 100B is similar to the bandwidth extension system 100A, except that the bandwidth extension system 100B further includes a frequency multiplier 140 connected to the signal mixer 130. The frequency multiplier 140 is configured to convert the down-converted signal V MIXER Multiply by factor N to generate frequency-doubled signal V FM , where N is an integer greater than 1. The frequency multiplied signal V FM With center frequency N·f o / K and absolute bandwidth N·Δf.

[0034] In the bandwidth extension system 100A / 100B, the main signal source 110 can be implemented in any one of the following ways, but not limited to, a main voltage controlled oscillator (VCO), a main phase locked loop (PLL) and a main direct digital frequency synthesizer (DDFS). The auxiliary signal source 120 can be implemented in any one of the following ways, but not limited to, an auxiliary VCO, an auxiliary PLL and an auxiliary DDFS.

[0035] In an example implementation of the bandwidth extension system 100A / 100B, the frequency control words FCW1 and FCW2 can be set to constants based on the respective selected frequency channels. The frequency control words FCW1 and FCW2 can be the same or different. The main signal source 110 can be configured to generate a single tone signal V with a limited tuning range. MAIN , so that the auxiliary signal source 120 can be configured to generate an auxiliary signal V having a tunable frequency to extend the overall tuning range AUX, so that the bandwidth extension system 100A / 100B can be used for generating non-modulated signals.

[0036] In another example implementation of the bandwidth extension system 100A / 100B, the first frequency control word FCW1 can be dynamically modulated over time, while the second frequency control word FCW2 can be set to a constant based on the selected frequency channel. The main signal source 110 can be configured to generate a frequency modulated continuous signal V with a narrow chirp range. MAIN The auxiliary signal source 120 can be configured to generate an auxiliary signal V of a single tone signal. AUX , so that the down-converted signal V generated by the signal mixer 130 MIXER The frequency modulated signal has an extended fractional bandwidth. Therefore, the bandwidth extension system 100A / 100B can be used to generate a frequency modulated signal.

[0037] Figure 3A A circuit block diagram of a bandwidth extension system 200A with a phase noise cancellation function according to another embodiment of the present invention is shown. As shown in the figure, the bandwidth extension system 200A is similar to the bandwidth extension system 100A, and includes a main signal source 210, an auxiliary signal source 220, and a signal mixer 230 connected to the main signal source 210 and the auxiliary signal source 220. The difference between the bandwidth extension system 200A and the bandwidth extension system 100A is that the bandwidth extension system 200A also includes a fractional frequency divider 250 connected between the main signal source 210 and the auxiliary signal source 220.

[0038] The main signal source 210 is configured to receive a first frequency control word FCW1 and a first reference signal V REF1 , and according to the first frequency control word FCW1 and the first reference signal V REF1 Synthesized main signal V MAIN . Main signal V MAIN With center frequency f o and fractional bandwidth Δf / f o .

[0039] The fractional frequency divider 250 is configured to receive the third frequency control word FCW3 and the main signal V MAIN , and demodulate the main signal V MAIN The chirp is generated with the main signal V MAIN Phase noise is related to the phase noise divided by the reference signal V FD .

[0040] The auxiliary signal source 220 is configured to receive the second frequency control word FCW2 and the frequency division reference signal V FD As the second reference signal V REF2 , and according to the second reference signal V REF2 Synthesized secondary signal V AUX. Secondary signal V AUX With the main signal V MAIN Phase noise is related to the center frequency f o (1-1 / K), where K is a real number greater than 1.

[0041] The signal mixer 230 is configured to mix the main signal V MAIN and the secondary signal V AUX To generate the down-converted signal V MIXER . Down-converted signal V MIXER With center frequency f o / K and fractional bandwidth K·Δf / f o .

[0042] The bandwidth extension system 200A may further include a first FCW generator (not shown) configured to provide a first frequency control word FCW1 to the main signal source 210, a second FCW generator (not shown) configured to provide a second frequency control word FCW2 to the secondary signal source 220, and a third FCW generator (not shown) configured to provide a third frequency control word FCW3 to the fractional divider 250.

[0043] The bandwidth extension system 200A may further include a first reference signal source (not shown) connected to the main signal source 210 and configured to provide a first reference signal V to the main signal source 210. REF1 .

[0044] Figure 3B FIG. 2 shows a circuit block diagram of a bandwidth extension system 200B with phase noise cancellation and frequency multiplication functions according to another embodiment of the present invention. The bandwidth extension system 200B is similar to the bandwidth extension system 200A, except that the bandwidth extension system 200B further includes a frequency multiplier 240 connected to the signal mixer 230. The frequency multiplier 240 is configured to multiply the down-converted signal by a factor N to generate a frequency multiplied signal V FM , where N is an integer greater than 1. The frequency multiplied signal V FM With center frequency N·f o / K and absolute bandwidth N·Δf.

[0045] In the bandwidth extension system 200A / 200B, the main signal source 210 can be implemented in any one of the following ways, but not limited to, a main phase-locked loop (PLL) and a main direct digital frequency synthesizer (DDFS). The auxiliary signal source 220 can be implemented in any one of the following ways, but not limited to, an auxiliary phase-locked loop (PLL) and an injection-locked clock multiplier.

[0046] In an example implementation of the bandwidth extension system 200A / 200B, each frequency control word FCW1, FCW2, and FCW3 can be set to a constant based on the respective selected frequency channel. The frequency control words FCW1, FCW2, and FCW3 can be the same or different. The main signal source 210 can be configured to generate a single tone signal V with a narrow tuning range. MAIN Then, the fractional divider 250 can be configured to demodulate the main signal V MAIN The chirp is generated by the main signal V MAIN Phase noise related divided reference signal V FD , the reference signal is the same as the main signal V MAIN The auxiliary signal source 220 is configured to receive the divided reference signal V FD As the second reference signal V REF2 , and generate the secondary signal V AUX , so that the second reference signal V REF2 and the secondary signal V AUX The frequency multiplication ratio can be adjusted to extend the overall tuning range. Thus, the bandwidth extension system 200A / 200B can be used for non-modulated signal generation with phase noise cancellation.

[0047] Figure 4A A circuit block diagram of a bandwidth extension system 300A with phase noise cancellation function according to another embodiment of the present invention is shown. As shown in the figure, the bandwidth extension system 300A is similar to the bandwidth extension system 200A, and includes a main signal source 310, a sub-signal source 320, and a signal mixer 330 connected to the main signal source 310 and the sub-signal source 320.

[0048] The bandwidth extension system 300A differs from the bandwidth extension system 200A in that the fractional frequency divider 350 is configured to receive the first frequency control word FCW1. The bandwidth extension system 300A may further include a first FCW generator (not shown) configured to provide the first frequency control word FCW1 to the main signal source 310 and the fractional frequency divider 350.

[0049] Figure 4B FIG. 3 is a circuit block diagram of a bandwidth extension system 300B with phase noise cancellation and frequency multiplication functions according to another embodiment of the present invention. The bandwidth extension system 300B is similar to the bandwidth extension system 300A, except that the bandwidth extension system 300B further includes a frequency multiplier 340 connected to the signal mixer 330.

[0050] In an example implementation of the bandwidth extension system 300A / 300B, the first frequency control word FCW1 can be dynamically modulated over time, while the second frequency control word FCW2 can be set to a constant based on the selected frequency channel. The main signal source 310 can be configured to generate a frequency modulated continuous signal V with a narrow chirp range. MAIN Then, the fractional divider 350 can be configured to convert the main signal V MAIN The frequency is divided into the main signal V MAIN Phase noise related divided reference signal V FD , the reference signal is the same as the main signal V MAIN The auxiliary signal source 320 is configured to receive the divided reference signal V FD As the second reference signal V REF2 , and generate the secondary signal V AUX , so that the down-converted signal V generated by the signal mixer 330 MIXER is a frequency modulated signal with an extended fractional bandwidth. Therefore, the bandwidth extension system 300A / 300B can be used for frequency modulated signal generation with phase noise cancellation.

[0051] Figure 5 A circuit block diagram of a bandwidth extension system 400 with a phase noise cancellation function according to another embodiment of the present invention is shown. As shown in the figure, the bandwidth extension system 400 includes a main signal source 410, a sub-signal source 420, a first frequency multiplier 440 connected to the main signal source 410, a second frequency multiplier 460 connected to the sub-signal source 420, and a signal mixer 430 connected to the first frequency multiplier 440 and the second frequency multiplier 460.

[0052] The main signal source 410 is configured to receive a first frequency control word FCW1 and a first reference signal V REF1 , and based on the first frequency control word FCW1 and the first reference signal V REF1 Synthesized main signal V MAIN . Main signal V MAIN With center frequency f o and fractional bandwidth Δf / f o .

[0053] The first frequency multiplier 440 is configured to convert the main signal V MAIN Multiply by factor N1 to generate a first frequency multiplied signal V FM1 , where N1 is an integer greater than 1. The first frequency multiplied signal V FM1 With center frequency N1·f o and fractional bandwidth Δf / f o .

[0054] The auxiliary signal source 420 is configured to receive the second frequency control word FCW2 and the second reference signal V REF2 , and based on the second frequency control word FCW2 and the second reference signal V REF2 Synthesized secondary signal V AUX . Secondary signal V AUX With center frequency f o (1-1 / K), where K is a real number greater than 1.

[0055] The second frequency multiplier 460 is configured to convert the auxiliary signal V AUX Multiply by factor N2 to generate a second frequency multiplied signal V FM2 , where N2 is an integer greater than 1. The second frequency multiplied signal V FM2 With center frequency N2·f o (1-1 / K).

[0056] The signal mixer 430 is configured to mix the first frequency-doubled signal V FM1 and the second frequency multiplied signal V FM2 To generate the down-converted signal V MIXER . Down-converted signal V MIXER With center frequency f o ·(N1-N2+N2 / K) and the absolute bandwidth N1·Δf.

[0057] In the bandwidth extension system 400, the main signal source 410 can be implemented in any one of the following ways, but not limited to, a main voltage controlled oscillator (VCO), a main phase locked loop (PLL), and a main direct digital frequency synthesizer (DDFS). The auxiliary signal source 420 can be implemented in any one of the following ways, but not limited to, an auxiliary VCO, an auxiliary PLL, and an auxiliary DDFS.

[0058] In an example implementation of the bandwidth extension system 400, each frequency control word FCW1 and FCW2 can be set to a constant based on the respective selected frequency channel. The frequency control words FCW1 and FCW2 can be the same or different. The main signal source 410 can be configured to generate a single tone signal V with a limited tuning range. MAIN , so that the secondary signal V AUX The frequency of can be tuned to extend the overall tuning range, and the bandwidth extension system 400 can be used for non-modulated signal generation.

[0059] Figure 6A circuit diagram of a fractional frequency divider 650 according to an embodiment of the present invention is shown. As shown, the fractional frequency divider 650 may include a multi-modulus divider (MMD) 651 and a chirp demodulator 653 to achieve fractional frequency division with ultra-low quantization noise. The chirp demodulator 653 may include a delta-sigma modulator (DSM) 654, a digital subtractor 655, a digital-to-time converter (DTC) 652, and a digital integrator 656.

[0060] The DSM 654 is configured to receive the FCW (FCW1 or FCW3) and generate the modulated signal V DSM (or control signal V CTRL1 ) to control the MMD. The MMD 651 is configured to be based on the control signal V CTRL1 The main signal V MAIN Divide the frequency to generate the divided signal V MMD The digital subtractor 655 is configured to convert the modulation signal V DSM Subtracted from FCW to generate a subtraction signal V SUB The digital integrator 656 is configured to SUB Integrate to generate the control signal V CTRL2 to DTC 652. DTC 652 is configured to CTRL2 The divided signal V MMD Converted into a divided reference signal V FD .

[0061] Figure 7 The circuit diagram of the auxiliary signal source 720 according to an embodiment of the present invention is shown. As shown in the figure, the auxiliary signal source 720 may include a sampling phase detector (SPD) 721, a low pass filter (LPF) 722, a VCO 723 and a multi-modulus divider (MMD) 724.

[0062] Figure 8 An example bandwidth extension system 800 is shown that is fabricated using a 28 nanometer CMOS process to demonstrate the effectiveness of bandwidth extension and phase noise cancellation. Fig. 9 A top view photograph of the manufactured IC chip is shown. The main signal source 810 uses a main PLL 810 configured to generate a main signal V in the frequency range of 12.5-16.7 GHz. MPLL The auxiliary signal source adopts the auxiliary PLL 820, which is configured to synthesize the auxiliary signal V with a frequency of 8.25 GHz. APLLThe signal mixer 830 is a double-balanced mixer configured to mix the main signal V MPLL and the secondary signal V APLL To generate a down-converted signal V in the frequency range of 4.25-8.45 GHz MIXER The frequency multiplier 840 is a phase-locked frequency multiplier configured to convert the down-converted signal V MIXER Multiply by the factor to generate a frequency doubled signal V in the frequency range of 12.75-25.35 GHz ILFM .

[0063] For comparison, the reference signal of the slave PLL 820 is multiplexed by the multiplexer 860 to the associated signal V of the fractional divider 850. FFD or another unassociated V REF2 between, corresponding to enabling and disabling phase noise cancellation, respectively.

[0064] Fig. 10A and 10B V MAIN and V MIXER It can be seen that even without the frequency multiplier 840, bandwidth extension and phase noise cancellation still effectively affect the output of the mixer.

[0065] Table 1 shows the signal V synthesized by a conventional PLL (without phase noise cancellation and frequency multiplication function). MPLL , the signal V synthesized by the bandwidth extension system with phase noise cancellation but without frequency multiplication function MIXER , and the signal V synthesized by the bandwidth extension system with phase noise cancellation and frequency multiplication function ILFM Bandwidth comparison.

[0066] Table 1: Signal synthesized by a conventional PLL (without phase noise cancellation and frequency multiplication) and a bandwidth extension system with phase noise cancellation but without frequency multiplication V MIXER , and the signal V synthesized by the bandwidth extension system with phase noise cancellation and frequency multiplication function ILFM .

[0067] Fig.11 shows the V of the bandwidth extension system with phase noise cancellation MPLL 、V APLL and V MIXER Measured phase noise spectrum. Fig.12 The V of the bandwidth extension system with and without phase noise cancellation is shown. MIXER Measured phase noise spectrum.

[0068] At 1MHz offset, the measured phase noise of the output signal of the bandwidth extension system with and without phase noise cancellation is -121.5 dBc / Hz and -113.2 dBc / Hz, respectively. The measured jitter of the output signal of the bandwidth extension system with and without phase noise cancellation is 88 femtoseconds and 226 femtoseconds, respectively.

[0069] According to the embodiments of the present disclosure, the functional units and modules of the apparatus, device, system, compound, material and / or method can be implemented using a computing device, a computer processor or an electronic circuit, including but not limited to an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a microcontroller and other programmable logic devices, configured or programmed according to the teachings of the present disclosure. Practitioners engaged in software or electronic arts can easily prepare computer instructions or software codes for running in a computing device, a computer processor or a programmable logic device according to the teachings of the present disclosure to implement the present invention.

[0070] All or part of the methods according to various embodiments may be executed on one or more computing devices including server computers, personal computers, notebook computers, mobile computing devices such as smart phones and tablet computers.

[0071] Embodiments may include computer storage media, volatile and non-volatile memory devices having stored therein computer instructions or software codes that may be used to program or configure a computing device, a computer processor, or an electronic circuit to perform any of the processes of the present invention. Storage media, volatile and non-volatile memory devices may include, but are not limited to, floppy disks, compact disks, Blu-ray disks, DVDs, CD-ROMs, optical magnetic disks, read-only memory (ROM), random access memory (RAM), flash memory storage devices, or any type of medium or device suitable for storing instructions, codes, and / or data.

[0072] According to various embodiments, each functional unit and module may also be implemented in a distributed computing environment and / or a cloud computing environment, where all or part of the machine instructions are distributedly executed by one or more processing devices connected via a communication network (such as a local area network, a wide area network, the Internet, and other forms of data transmission media).

[0073] Although the present disclosure has been described and illustrated with specific embodiments, these descriptions and illustrations are not restrictive. There may be other embodiments of the present disclosure that are not specifically described. The specific embodiments may be modified to adapt specific circumstances, materials, material compositions, methods or processes to the purposes and scope of the present disclosure. All these modifications fall within the scope of the appended claims. Due to manufacturing processes and tolerances, there may be differences between the actual device and the pictures of the present disclosure. The drawings are not necessarily drawn to scale. Although the methods disclosed herein are described in terms of specific operations performed in a specific order, it should be understood that these operations can be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless expressly stated herein, the order and grouping of operations do not limit the scope of protection.

Claims

1. A bandwidth extension system, comprising: A main signal source is configured to receive a first frequency control word and a first reference signal, and synthesize a signal having a center frequency f according to the first frequency control word and the first reference signal. o and fractional bandwidth Δf / f o The main signal of The auxiliary signal source is configured to receive a second frequency control word and a second reference signal, and synthesize a signal having a center frequency f according to the second frequency control word and the second reference signal. o A secondary signal of (1-1 / K), where K is a real number greater than 1; as well as A signal mixer is configured to mix the main signal and the auxiliary signal to generate a signal having a center frequency f o / K and fractional bandwidth K·Δf / f o down-converted signal.

2. The bandwidth extension system according to claim 1, characterized in that Further including: a first reference signal source connected to the main signal source and configured to provide a first reference signal to the main signal source; as well as The second reference signal source is connected to the slave signal source and configured to provide a second reference signal to the slave signal source.

3. The bandwidth extension system according to claim 2, characterized in that The main signal source is implemented by a main voltage controlled oscillator, a main phase locked loop or a main direct digital frequency synthesizer; and The auxiliary signal source is realized by an auxiliary voltage controlled oscillator, an auxiliary phase locked loop or an auxiliary direct digital frequency synthesizer.

4. The bandwidth extension system according to claim 1, characterized in that: further comprising a reference signal source and a fractional frequency divider; in The reference signal source is connected to the main signal source and is configured to provide a first reference signal to the main signal source; The fractional frequency divider is connected between the main signal source and the auxiliary signal source, and is used to receive the third frequency control word and the main signal, and demodulate the chirp of the main signal to generate a frequency-divided reference signal having a phase noise related to the phase noise of the main signal source; The auxiliary signal source is further configured to receive the divided reference signal from the fractional frequency divider as a second reference signal; and generate an auxiliary signal having a phase noise correlated with a phase noise of the main signal.

5. The bandwidth extension system according to claim 4, wherein: The fractional frequency divider comprises: a chirp demodulator configured to demodulate the third frequency control word to generate a first control signal and a second control signal; a multi-modulus frequency divider configured to receive a first control signal and a main signal, and divide the main signal based on the first control signal to generate a divided signal; The digital-to-time converter is configured to receive the second control signal and the frequency-divided signal, and convert the frequency-divided signal into a frequency-divided reference signal based on the second control signal.

6. The bandwidth extension system of claim 5, wherein the chirp demodulator comprises: a differential-integral modulator configured to receive a third frequency control word and generate a first control signal; a digital subtractor configured to subtract the first control signal from the third frequency control word to generate a subtraction signal; and The digital integrator is configured to integrate the subtraction signal to generate a second control signal.

7. The bandwidth extension system according to claim 6, wherein The main signal source is implemented by a main phase-locked loop or a main direct digital frequency synthesizer; and The auxiliary signal source is realized by using an auxiliary phase-locked loop or an injection-locked clock multiplier.

8. The bandwidth extension system according to any one of claims 1 to 7, wherein: The signal mixer is a double balanced mixer.

9. A bandwidth extension system, comprising: A main signal source is configured to receive a first frequency control word and a first reference signal, and synthesize a signal having a center frequency f according to the first frequency control word and the first reference signal. o and fractional bandwidth Δf / f o The main signal of The auxiliary signal source is configured to receive a second frequency control word and a second reference signal, and synthesize a signal having a center frequency f according to the second frequency control word and the second reference signal. o A secondary signal of (1-1 / K), where K is a real number greater than 1; A signal mixer is configured to mix the main signal and the auxiliary signal to generate a signal having a center frequency f o / K and fractional bandwidth K·Δf / f o A down-converted signal of A frequency multiplier configured to multiply the down-converted signal by a factor N to generate a frequency multiplier having a center frequency N·f o / K and a frequency-multiplied signal with an absolute bandwidth N·Δf, where N is an integer greater than 1.

10. The bandwidth extension system according to claim 9, characterized in that: Further including: a first reference signal source connected to the main signal source and configured to provide a first reference signal to the main signal source; as well as The second reference signal source is connected to the slave signal source and configured to provide a second reference signal to the slave signal source.

11. The bandwidth extension system according to claim 10, characterized in that The main signal source is implemented by a main voltage controlled oscillator, a main phase locked loop or a main direct digital frequency synthesizer; and The auxiliary signal source is realized by an auxiliary voltage controlled oscillator, an auxiliary phase locked loop or an auxiliary direct digital frequency synthesizer.

12. The bandwidth extension system according to claim 9, characterized in that: further comprising a reference signal source and a fractional frequency divider; in The reference signal source is connected to the main signal source and is configured to provide a first reference signal to the main signal source; The fractional frequency divider is connected between the main signal source and the auxiliary signal source, and is used to receive the third frequency control word and the main signal, and demodulate the chirp of the main signal to generate a frequency-divided reference signal having a phase noise related to the phase noise of the main signal source; The auxiliary signal source is further configured to receive the divided reference signal from the fractional frequency divider as a second reference signal; and generate an auxiliary signal having a phase noise correlated with a phase noise of the main signal.

13. The bandwidth extension system according to claim 12, wherein: The fractional frequency divider comprises: a chirp demodulator configured to demodulate the third frequency control word to generate a first control signal and a second control signal; a multi-modulus frequency divider configured to receive a first control signal and a main signal, and divide the main signal based on the first control signal to generate a divided signal; The digital-to-time converter is configured to receive the second control signal and the frequency-divided signal, and convert the frequency-divided signal into a frequency-divided reference signal based on the second control signal.

14. The bandwidth extension system of claim 13, wherein the chirp demodulator comprises: a differential-integral modulator configured to receive a third frequency control word and generate a first control signal; a digital subtractor configured to subtract the first control signal from the third frequency control word to generate a subtraction signal; and The digital integrator is configured to integrate the subtraction signal to generate a second control signal.

15. The bandwidth extension system according to claim 14, wherein The main signal source is implemented by a main phase-locked loop or a main direct digital frequency synthesizer; and The auxiliary signal source is realized by using an auxiliary phase-locked loop or an injection-locked clock multiplier.

16. The bandwidth extension system according to any one of claims 9 to 15, wherein: The signal mixer is a double balanced mixer.

17. The bandwidth extension system according to any one of claims 9 to 15, wherein the frequency multiplier is an injection locked frequency multiplier.

18. A bandwidth extension system, comprising: A main signal source is configured to receive a first frequency control word and a first reference signal, and synthesize a signal having a center frequency f according to the first frequency control word and the first reference signal. o and fractional bandwidth Δf / f o The main signal of The first frequency multiplier is configured to multiply the main signal by a factor N1 to generate a frequency multiplier having a center frequency N " ·f o and fractional bandwidth Δf / f o A first frequency multiplied signal of , wherein N1 is an integer greater than 1; The auxiliary signal source is configured to receive a second frequency control word and a second reference signal, and synthesize a signal having a center frequency f according to the second frequency control word and the second reference signal. o A secondary signal of (1-1 / K), where K is a real number greater than 1; The second frequency multiplier is configured to multiply the secondary signal by a factor N2 to generate a frequency multiplier having a center frequency N2·f o A second frequency multiplied signal of (1-1 / K), wherein N2 is an integer greater than 1; as well as A signal mixer is configured to mix the first frequency doubled signal and the second frequency doubled signal to generate a signal having a center frequency f o ·(N " -N2+N2 / K) and absolute bandwidth N " ·Δf down-converted signal.

19. The bandwidth extension system according to claim 18, characterized in that The main signal source is implemented by a main voltage controlled oscillator, a main phase locked loop or a main direct digital frequency synthesizer; and The auxiliary signal source is realized by an auxiliary voltage controlled oscillator, an auxiliary phase locked loop or an auxiliary direct digital frequency synthesizer.

20. The bandwidth extension system according to any one of claims 18 to 19, wherein: The signal mixer is a double balanced mixer.

21. The bandwidth extension system according to any one of claims 18 to 19, wherein the first and second frequency multipliers are both injection locked frequency multipliers.

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