Shield gate power device for improving EAS capability of device and manufacturing method

Abstract

The invention discloses a shield gate power device for improving the EAS capability of the device and a manufacturing method, and relates to the technical field of semiconductors. On the basis of an existing groove type structure, a deep contact hole is formed in an insulating medium layer, and the deep contact hole penetrates through the insulating medium layer and a first conduction type source region downwards to enter a second conduction type body region; an insulating filler and source electrode metal are sequentially arranged in the deep contact hole from bottom to top, the source electrode metal is in ohmic contact with the first conductive type source region and the second conductive type body region, and the insulating filler is in contact with the second conductive type body region; a silicon dioxide buried layer is arranged around the deep contact hole in the second conductive type body region, a first conductive type source region is arranged above the silicon dioxide buried layer, and the silicon dioxide buried layer is located in the second conductive type body region and does not make contact with the first conductive type epitaxial layer. According to the invention, the reliability of the SGT-MOSFET structure is improved, the EAS capability is improved, and the problems that the electrical parameter discreteness of an MOSFET device and the size of a source cell cannot be reduced are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a shielded gate power device for improving the EAS capability of the device and a manufacturing method thereof. Background Art

[0002] SGT-MOSFET (shielded gate trench MOSFET) is an innovative trench power MOSFET based on the improvement of traditional trench MOSFET (U-MOSFET). By applying the charge balance technology theory, SGT-MOSFET introduces additional polysilicon field plates into traditional power MOSFET for electric field modulation, thereby improving the device's withstand voltage and reducing the on-resistance.

[0003] Since SGT-MOSFET has low internal resistance and fast switching speed, it can greatly improve the efficiency of power supply system. Therefore, SGT-MOSFET is widely used in consumer electronics, industrial control and automotive electronics. However, in some special applications, such as hot-swap circuits, when SGT-MOSFET is turned on, the power supply system will suddenly have a high surge current. The surge current at this time can easily cause the SGT-MOSFET to burn out due to overcurrent, thereby reducing the reliability of the entire power supply system.

[0004] The device's surge resistance can be improved by increasing the chip area, but this approach will result in excessively high product costs and will not meet the requirements of product miniaturization.

[0005] The device EAS capability can also be optimized by digging deeper holes / increasing contact hole CD technology, but this method is also accompanied by the problem of device electrical parameter (VTH / RDSON) discreteness and the problem that the source cell size cannot be effectively reduced. Summary of the invention

[0006] The technical problem to be solved by the present invention is how to improve the reliability of the SGT-MOSFET structure, improve the EAS capability of the MOSFET, and at the same time improve the discreteness of the electrical parameters of the MOSFET device and the problem that the source cell size cannot be reduced.

[0007] In order to solve the above problems, the present invention proposes the following technical solutions:

[0008] In a first aspect, the present invention provides a shielded gate power device for improving the EAS capability of the device, comprising a first conductive type silicon substrate, a first conductive type epitaxial layer, a second conductive type body region, a first conductive type source region, an insulating dielectric layer and a source metal arranged in sequence from bottom to top, the first conductive type silicon substrate is connected to a drain potential, the source metal is connected to a source potential, deep trenches parallel to each other are arranged in the first conductive type source region, the deep trenches penetrate downwardly through the first conductive type source region and enter the second conductive type body region, shielded gate polysilicon connected to the source potential and gate polysilicon connected to the gate potential are arranged in the deep trenches, the gate polysilicon is located at the top of the deep trenches, gate oxide layers are arranged between the gate polysilicon and the first conductive type source region, the second conductive type body region and the first conductive type epitaxial layer respectively, and a field oxide layer is arranged between the shielded gate polysilicon and the first conductive type epitaxial layer;

[0009] A deep contact hole is provided in the insulating dielectric layer, and the deep contact hole penetrates downward through the insulating dielectric layer and the first conductive type source region into the second conductive type body region; an insulating filler and a source metal are sequentially provided in the deep contact hole from bottom to top, the source metal is in ohmic contact with the first conductive type source region and the second conductive type body region respectively, and the insulating filler is in contact with the second conductive type body region;

[0010] A silicon dioxide buried layer is arranged around the deep contact hole in the second conductive type body region, a first conductive type source region is located above the silicon dioxide buried layer, and the silicon dioxide buried layer is located in the second conductive type body region and does not contact the first conductive type epitaxial layer.

[0011] A further technical solution is that part of the second conductivity type body region between the silicon dioxide buried layer and the deep contact hole is a P+ region.

[0012] A further technical solution is that the P+ region is in contact with a first conductive type source region.

[0013] A further technical solution is that the P+ region is in contact with the insulating filler and the source metal.

[0014] A further technical solution is that the distance between the silicon dioxide buried layer and the gate oxide layer is to

[0015] A further technical solution is that the distance between the lower surface and the upper surface of the insulating filler ranges from 0.1 microns to 4 microns.

[0016] A further technical solution is that the gate oxide layer, field oxide layer, insulating dielectric layer and insulating filler are all made of silicon dioxide or silicon nitride.

[0017] A further technical solution is that when the shielded gate power device is an N-type device, the first conductivity type is N-type and the second conductivity type is P-type; or, when the shielded gate power device is a P-type device, the first conductivity type is P-type and the second conductivity type is N-type.

[0018] The present invention also provides a method for manufacturing a shielded gate power device for improving the EAS capability of the device, comprising the following steps:

[0019] Step 1: providing a first conductive type silicon substrate, and growing a first conductive type epitaxial layer on the first conductive type silicon substrate to form a wafer;

[0020] Step 2: selectively etching a deep trench on the upper surface of the first conductive type epitaxial layer, and then forming a field oxide layer on the surface of the first conductive type epitaxial layer and the sidewalls and bottom of the deep trench;

[0021] Step 3: depositing conductive polysilicon on the surface of the field oxide layer, wherein the conductive polysilicon fills the deep trench;

[0022] Step 4: etching the conductive polysilicon above the upper surface of the first conductive type epitaxial layer, leaving only the conductive polysilicon in the deep trench, to form shielding gate polysilicon;

[0023] Step 5: etching the field oxide layer in the deep trench near the top of the deep trench;

[0024] Step 6: forming a gate oxide layer on the sidewalls of the top of the deep trench and the upper surface of the first conductive type epitaxial layer;

[0025] Step 7: depositing conductive polysilicon on the surface of the gate oxide layer, and then etching away the conductive polysilicon above the upper surface of the first conductive type epitaxial layer to form gate polysilicon at the top of the deep trench;

[0026] Step eight: implanting second conductivity type impurities into the upper surface of the first conductivity type epitaxial layer and annealing to form a second conductivity type body region on the upper surface of the first conductivity type epitaxial layer;

[0027] Step nine: selectively implanting oxygen ions at a preset position on the upper surface of the second conductive type body region, where the oxygen ions react with silicon to form a buried silicon dioxide layer;

[0028] Step 10: Then, the first conductivity type impurities are injected and activated to form a first conductivity type source region on the upper surface of the second conductivity type body region and the silicon dioxide buried layer;

[0029] Step 11: depositing an insulating dielectric on the first conductive type source region and the deep trench to form an insulating dielectric layer;

[0030] Step 12: selectively etching the insulating dielectric layer to form a through hole, wherein the through hole penetrates the insulating dielectric layer and the first conductive type source region and enters the second conductive type body region, and then injecting second conductive type impurities into the through hole, and after activation, forming a second conductive type source region at the interface between the through hole and the second conductive type body region;

[0031] Step 13: depositing insulating fillers and metals into the through holes on the insulating dielectric layer in sequence, and forming source metals on the insulating dielectric layer.

[0032] A further technical solution is that in step nine, the width of the generated buried silicon dioxide layer does not exceed 1 / 4 of the width of the deep trench.

[0033] Compared with the prior art, the technical effects achieved by the present invention include:

[0034] The shielded gate power device for improving the EAS capability of the device provided by the present invention has, on the one hand, a deep contact hole in the insulating dielectric layer, and insulating fillers and source metals are sequentially arranged in the deep contact hole from bottom to top, and the source metals are respectively in ohmic contact with the first conductive type source region and the second conductive type body region, which helps to improve the EAS capability of the device. In addition, the insulating filler is in contact with the second conductive type body region; it can effectively improve the electric field withstand voltage strength between the bottom of the P+ region and the first conductive epitaxial layer, thereby achieving the improvement of the device withstand voltage capability; on the other hand, a silicon dioxide buried layer is arranged around the deep contact hole in the second conductive type body region, and the deep buried layer SiO2 film effectively blocks the influence of the P+ injected impurity concentration on the channel impurity distribution, ensures the consistency of the VTH / RDSON parameters, and more accurately controls the impurity concentration in the deep trench region.

[0035] It is further explained that the shielded gate power device for improving the EAS capability of the device provided by the present invention is configured to penetrate downwardly through the first conductive type source region and the second conductive type body region, enter the first conductive type epitaxial layer to form a CMOS capacitor, thereby being connected in series with the equivalent resistance of the first conductive type epitaxial layer, forming an RC absorption loop between the source and the drain, absorbing the voltage oscillation dv / dt and current oscillation di / dt between the drain and source of the device, effectively reducing the switching oscillation of the device, improving the voltage oscillation dv / dt tolerance, and reducing the EMI electromagnetic radiation noise in the switching circuit; at the same time, a P+ region is formed between the silicon dioxide buried layer and the deep contact hole in the deep trench structure without additionally increasing the on-resistance of the device; the configuration of the silicon dioxide buried layer can effectively shield the gate signal of the polysilicon gate and reduce the Miller capacitance Cgd.

[0036] The shielded gate power device with improved device EAS capability provided by the present invention has a new SGT MOSFET structure, while improving the device EAS capability, ensuring the consistency of product electrical parameters, and being able to improve the product withstand voltage effect without increasing the chip device size and appropriately reduce the contact hole opening size to increase the source cell density. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0038] Figure 1 A schematic cross-sectional structure diagram of a shielded gate power device provided in an embodiment of the present invention.

[0039] Reference numerals

[0040] A first conductive type silicon substrate 10, a first conductive type epitaxial layer 20, a second conductive type body region 30, a first conductive type source region 40, an insulating dielectric layer 50, a source metal 60, an insulating filler 1, a silicon dioxide buried layer 2, a gate polysilicon 3, and a shielding gate polysilicon 4. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Similar component numbers in the drawings represent similar components. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0043] It should also be understood that the terms used in this description of the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present invention. As used in the description of the embodiments of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms of "a", "an" and "the" are intended to include plural forms.

[0044] In the present invention, N-type refers to an impurity semiconductor in which impurities of group V elements such as phosphorus are doped into silicon crystals, making the concentration of free electrons much greater than the concentration of holes, and P-type refers to an impurity semiconductor in which impurities of group III elements such as boron are doped into silicon crystals, making the concentration of holes much greater than the concentration of free electrons.

[0045] It should be noted that when the shielded gate power device is an N-type device, the first conductivity type is N-type and the second conductivity type is P-type; when the shielded gate power device is a P-type device, the first conductivity type is P-type and the second conductivity type is N-type.

[0046] The shielded gate power devices in the following embodiments are all N-type devices, that is, the first conductivity type is N-type and the second conductivity type is P-type. The present invention is also applicable to P-type devices.

[0047] See also Figure 1 , which is a schematic diagram of the cross-sectional structure of the shielded gate power device provided by an embodiment of the present invention. As can be seen from the figure, the shielded gate power device for improving the EAS capability of the device provided by an embodiment of the present invention includes a first conductive type silicon substrate 10, a first conductive type epitaxial layer 20, a second conductive type body region 30, a first conductive type source region 40, an insulating dielectric layer 50 and a source metal 60 arranged in sequence from bottom to top, the first conductive type silicon substrate 10 is connected to the drain potential, the source metal 60 is connected to the source potential, and deep trenches parallel to each other are arranged in the first conductive type source region 40, and the deep trenches penetrate downwardly through the first conductive type source region 40 and enter the second conductive type body region 30.

[0048] A shielding gate polysilicon 4 connected to the source potential and a gate polysilicon 3 connected to the gate potential are arranged in the deep trench, the gate polysilicon 3 is located at the top of the deep trench, a gate oxide layer is arranged between the gate polysilicon 3 and the first conductive type source region 40, the second conductive type body region 30 and the first conductive type epitaxial layer 20, respectively, and a field oxide layer is arranged between the shielding gate polysilicon 4 and the first conductive type epitaxial layer 20;

[0049] A deep contact hole is provided in the insulating dielectric layer 50, and the deep contact hole penetrates downwardly through the insulating dielectric layer 50 and the first conductive type source region 40 into the second conductive type body region 30; an insulating filler 1 and a source metal 60 are sequentially arranged in the deep contact hole from bottom to top, and the source metal 60 is in ohmic contact with the first conductive type source region 40 and the second conductive type body region 30 respectively, and the insulating filler 1 is in contact with the second conductive type body region 30.

[0050] In this embodiment, a silicon dioxide buried layer 2 is provided in the second conductive type body region 30 surrounding the deep contact hole, and a first conductive type source region 40 is located above the silicon dioxide buried layer 2. The silicon dioxide buried layer 2 is located in the second conductive type body region 30 and does not contact the first conductive type epitaxial layer 20.

[0051] When the present embodiment is turned on, the gate polysilicon 3 is connected to a high potential, and an electron accumulation layer appears on the interface between the second conductive type body region 30 (P type) and the gate oxide layer. The current enters the electron accumulation layer from the first conductive type epitaxial layer 20 (N type), and then enters the first conductive type source region 40 (N type). Therefore, the silicon dioxide buried layer 2 will not affect the conduction path of the current and will not increase the on-resistance.

[0052] In this embodiment, part of the second conductivity type body region 30 between the silicon dioxide buried layer 2 and the deep contact hole is a P+ region. It can be understood that the P+ region is a P+ implantation region.

[0053] In this embodiment, the P+ region is in contact with the first conductivity type source region 40 .

[0054] In this embodiment, the P+ region is in contact with the insulating filler 1 and the source metal 60 .

[0055] In some embodiments, the distance between the silicon dioxide buried layer 2 and the gate oxide layer is to In this embodiment, the distance between the silicon dioxide buried layer 2 and the gate oxide layer is

[0056] In some embodiments, the distance between the lower surface and the upper surface of the insulating filler 1 ranges from 0.1 micrometers to 4 micrometers. In this embodiment, the distance between the lower surface and the upper surface of the insulating filler 1 is 0.3 micrometers.

[0057] In this embodiment, the gate oxide layer, the field oxide layer, the insulating dielectric layer 50 and the insulating filler 1 are all made of silicon dioxide.

[0058] In some embodiments, the width w of the buried silicon dioxide layer 2 does not exceed 1 / 4 of the width of the deep trench to ensure the short-circuit area between the source metal and the P+ region.

[0059] The shielded gate power device for improving the EAS capability of the device provided by the embodiment of the present invention, on the one hand, is provided with a deep contact hole in the insulating dielectric layer, and the deep contact hole is sequentially provided with an insulating filler and a source metal from bottom to top, and the source metal is in ohmic contact with the first conductive type source region and the second conductive type body region, respectively, which helps to improve the EAS capability of the device. In addition, the insulating filler is in contact with the second conductive type body region; it can effectively improve the electric field withstand voltage strength between the bottom of the P+ region and the first conductive epitaxial layer, thereby achieving the improvement of the device withstand voltage capability; on the other hand, a silicon dioxide buried layer is provided around the deep contact hole in the second conductive type body region, and the deep buried layer SiO2 film effectively blocks the influence of the P+ injected impurity concentration on the channel impurity distribution, ensures the consistency of the VTH / RDSON parameters, and more accurately controls the impurity concentration in the deep trench region.

[0060] It is further explained that the shielded gate power device for improving the EAS capability of the device provided by the embodiment of the present invention, by setting a deep trench to penetrate downwardly through the first conductive type source region and the second conductive type body region, and enter the first conductive type epitaxial layer to form a CMOS capacitor, thereby being connected in series with the equivalent resistance of the first conductive type epitaxial layer, forming an RC absorption loop between the source and the drain, absorbing the voltage oscillation dv / dt and current oscillation di / dt between the drain and source of the device, effectively reducing the switching oscillation of the device, improving the voltage oscillation dv / dt tolerance, and reducing the EMI electromagnetic radiation noise in the switching circuit; at the same time, a P+ region is formed between the silicon dioxide buried layer and the deep contact hole in the deep trench structure without additionally increasing the on-resistance of the device; the setting of the silicon dioxide buried layer can effectively shield the gate signal of the polysilicon gate and reduce the Miller capacitance Cgd.

[0061] The shielded gate power device with improved device EAS capability provided by the embodiment of the present invention has a new SGT MOSFET structure, while improving the device EAS capability, ensuring the consistency of product electrical parameters, and being able to improve the product withstand voltage effect without increasing the chip device size and appropriately reduce the contact hole opening size to increase the source cell density.

[0062] The embodiment of the present invention also provides a method for manufacturing a shielded gate power device for improving the EAS capability of the device, comprising the following steps:

[0063] Step 1: providing a first conductive type silicon substrate 10, and growing a first conductive type epitaxial layer 20 on the first conductive type silicon substrate 10 to form a wafer;

[0064] Step 2: selectively etching a deep trench on the upper surface of the first conductive type epitaxial layer 20, and then forming a field oxide layer on the surface of the first conductive type epitaxial layer 20 and the sidewalls and bottom of the deep trench;

[0065] Step 3: depositing conductive polysilicon on the surface of the field oxide layer, wherein the conductive polysilicon fills the deep trench;

[0066] Step 4: etching the conductive polysilicon above the upper surface of the first conductive type epitaxial layer 20, leaving only the conductive polysilicon in the deep trench, to form the shielding gate polysilicon 4;

[0067] Step 5: etching the field oxide layer in the deep trench near the top of the deep trench;

[0068] Step 6: forming a gate oxide layer on the sidewalls of the top of the deep trench and the upper surface of the first conductive type epitaxial layer 20;

[0069] Step 7: depositing conductive polysilicon on the surface of the gate oxide layer, and then etching away the conductive polysilicon above the upper surface of the first conductive type epitaxial layer 20 to form a gate polysilicon 3 at the top of the deep trench;

[0070] Step eight: implanting second conductivity type impurities into the upper surface of the first conductivity type epitaxial layer 20 and annealing to form a second conductivity type body region 30 on the upper surface of the first conductivity type epitaxial layer 20;

[0071] Step nine: selectively implanting oxygen ions at a preset position on the upper surface of the second conductivity type body region 30, where the oxygen ions react with silicon to form a silicon dioxide buried layer 2;

[0072] Step 10: Then, the first conductive type impurities are injected and activated to form a first conductive type source region 40 on the upper surface of the second conductive type body region 30 and the silicon dioxide buried layer 2;

[0073] Step 11: depositing an insulating dielectric on the first conductive type source region 40 and the deep trench to form an insulating dielectric layer;

[0074] Step 12: selectively etching the insulating dielectric layer 50 to form a through hole, wherein the through hole penetrates the insulating dielectric layer and the first conductive type source region 40 and enters the second conductive type body region 30, and then injecting second conductive type impurities into the through hole, and after activation, forming a second conductive type source region at the interface between the through hole and the second conductive type body region 20;

[0075] Step 13: depositing an insulating filler 1 and a metal into the through hole on the insulating dielectric layer 50 in sequence, and forming a source metal 60 on the insulating dielectric layer 50 .

[0076] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0077] The above is a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A shielded gate power device for improving the EAS capability of the device, comprising a first conductive type silicon substrate, a first conductive type epitaxial layer, a second conductive type body region, a first conductive type source region, an insulating dielectric layer and a source metal arranged in sequence from bottom to top, characterized in that: The first conductive type silicon substrate is connected to the drain potential, the source metal is connected to the source potential, deep trenches parallel to each other are provided in the first conductive type source region, the deep trenches penetrate downwards into the first conductive type source region and enter the second conductive type body region; shielding gate polysilicon connected to the source potential and gate polysilicon connected to the gate potential are provided in the deep trenches, the gate polysilicon is located at the top of the deep trenches, gate oxide layers are provided between the gate polysilicon and the first conductive type source region, the second conductive type body region and the first conductive type epitaxial layer respectively, and a field oxide layer is provided between the shielding gate polysilicon and the first conductive type epitaxial layer; A deep contact hole is provided in the insulating dielectric layer, and the deep contact hole penetrates downward through the insulating dielectric layer and the first conductive type source region into the second conductive type body region; an insulating filler and a source metal are sequentially provided in the deep contact hole from bottom to top, the source metal is in ohmic contact with the first conductive type source region and the second conductive type body region respectively, and the insulating filler is in contact with the second conductive type body region; A silicon dioxide buried layer is arranged around the deep contact hole in the second conductive type body region, a first conductive type source region is located above the silicon dioxide buried layer, and the silicon dioxide buried layer is located in the second conductive type body region and does not contact the first conductive type epitaxial layer.

2. The shielded gate power device for improving the EAS capability of the device as claimed in claim 1, characterized in that: A portion of the second conductivity type body region located between the silicon dioxide buried layer and the deep contact hole is a P+ region.

3. The shielded gate power device for improving the EAS capability of the device as claimed in claim 2, characterized in that: The P+ region contacts the first conductive type source region.

4. The shielded gate power device for improving the EAS capability of the device as claimed in claim 3, characterized in that: The P+ region is in contact with the insulating filler and the source metal.

5. The shielded gate power device for improving the EAS capability of the device as claimed in claim 1, characterized in that: The distance between the silicon dioxide buried layer and the gate oxide layer is to 6. The shielded gate power device for improving the EAS capability of the device as claimed in claim 1, characterized in that: The distance between the lower surface and the upper surface of the insulating filler ranges from 0.1 micrometers to 4 micrometers.

7. The shielded gate power device for improving the EAS capability of the device as claimed in claim 1, characterized in that: The gate oxide layer, field oxide layer, insulating dielectric layer and insulating filler are all made of silicon dioxide or silicon nitride.

8. The shielded gate power device for improving the EAS capability of the device as claimed in claim 1, characterized in that: When the shielded gate power device is an N-type device, the first conductivity type is N-type and the second conductivity type is P-type; or, when the shielded gate power device is a P-type device, the first conductivity type is P-type and the second conductivity type is N-type.

9. A method for manufacturing a shielded gate power device for improving the EAS capability of the device as claimed in any one of claims 1 to 8, characterized in that: The steps include: Step 1: providing a first conductive type silicon substrate, and growing a first conductive type epitaxial layer on the first conductive type silicon substrate to form a wafer; Step 2: selectively etching a deep trench on the upper surface of the first conductive type epitaxial layer, and then forming a field oxide layer on the surface of the first conductive type epitaxial layer and the sidewalls and bottom of the deep trench; Step 3: depositing conductive polysilicon on the surface of the field oxide layer, wherein the conductive polysilicon fills the deep trench; Step 4: etching the conductive polysilicon above the upper surface of the first conductive type epitaxial layer, leaving only the conductive polysilicon in the deep trench, to form shielding gate polysilicon; Step 5: etching the field oxide layer in the deep trench near the top of the deep trench; Step 6: forming a gate oxide layer on the sidewalls of the top of the deep trench and the upper surface of the first conductive type epitaxial layer; Step 7: depositing conductive polysilicon on the surface of the gate oxide layer, and then etching away the conductive polysilicon above the upper surface of the first conductive type epitaxial layer to form gate polysilicon at the top of the deep trench; Step eight: implanting second conductivity type impurities into the upper surface of the first conductivity type epitaxial layer and annealing to form a second conductivity type body region on the upper surface of the first conductivity type epitaxial layer; Step nine: selectively implanting oxygen ions at a preset position on the upper surface of the second conductive type body region, where the oxygen ions react with silicon to form a buried silicon dioxide layer; Step 10: Then, the first conductivity type impurities are injected and activated to form a first conductivity type source region on the upper surface of the second conductivity type body region and the silicon dioxide buried layer; Step 11: depositing an insulating dielectric on the first conductive type source region and the deep trench to form an insulating dielectric layer; Step 12: selectively etching the insulating dielectric layer to form a through hole, wherein the through hole penetrates the insulating dielectric layer and the first conductive type source region and enters the second conductive type body region, and then injecting second conductive type impurities into the through hole, and after activation, forming a second conductive type source region at the interface between the through hole and the second conductive type body region; Step 13: depositing insulating fillers and metals into the through holes on the insulating dielectric layer in sequence, and forming source metals on the insulating dielectric layer.

10. The method for manufacturing a shielded gate power device for improving the EAS capability of the device as claimed in claim 9, characterized in that: In the step nine, the width of the generated buried silicon dioxide layer does not exceed 1 / 4 of the width of the deep trench.

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