FPGA-based single-chip high-speed logic analyzer and logic analysis method

Abstract

The invention relates to the technical field of digital signal processing, in particular to a single-chip high-speed logic analyzer based on an FPGA and a logic analysis method. The single-chip high-speed logic analyzer based on the FPGA comprises an electrostatic discharge protection module, an external oscillator, a system clock generation module, a dual-data-rate IO port, a pulse width modulation module, a reference voltage module, a first interface and a second interface. The first interface is a USB2.0 interface, the first interface is used for receiving an acquisition instruction of an external upper computer, so that the FPGA-based single-chip high-speed logic analyzer analyzes the acquisition instruction to obtain acquisition parameters, and the acquisition parameters are used for controlling the FPGA-based single-chip high-speed logic analyzer to perform data acquisition on to-be-acquired equipment; obtaining target data; the second interface is used for transmitting the target data to the external upper computer, the second interface is a preset SerDes interface, and the preset SerDes interface is used for realizing a data transmission function of a USB3.0 interface so as to perform high-speed data transmission.

Description

Technical Field

[0001] The present application relates to the technical field of digital signal processing, and in particular to a single-chip high-speed logic analyzer and a logic analysis method based on FPGA. Background Art

[0002] Logic analyzer is a commonly used data signal test instrument, which is widely used in software and hardware debugging and testing of various digital systems. Development engineers can connect probes to digital systems and use logic analyzers to capture target signals in the system, thereby analyzing the operating status of the system and troubleshooting. Logic analyzers can be divided into stand-alone, USB and PCIE types according to their form and purpose.

[0003] The stand-alone logic analyzer has its own screen and operation buttons. Although it is powerful, the whole machine is expensive and large in size, and is suitable for use in fixed places such as laboratories. PCIE-type logic analyzers are known for their high acquisition speed and usually need to be used on desktop computers. High-speed signal acquisition is performed by inserting a logic analyzer acquisition card on the motherboard, which is suitable for application environments in fixed places. USB-type logic analyzers are the most suitable type for mobile use due to their small size and convenient connectivity. It can be easily connected to desktops, laptops, and even tablets, supporting debugging anytime and anywhere. However, most USB-type logic analyzers currently use USB2.0 interfaces, which are limited to a bandwidth of 480Mbps. When high-speed signals above 100M need to be acquired, a built-in cache chip such as SDRAM or DDR is usually required to cache the signal before transmitting it to the computer.

[0004] Although this caching method can alleviate bandwidth limitations, it also brings some disadvantages: first, it increases the cost of the cache chip; second, the capacity of the cache chip is limited, resulting in a limit on the length of the signal that can be captured; finally, the caching and transmission process generates delays, making it impossible to display the signal in real time. These limitations have affected the performance and application scope of USB logic analyzers to a certain extent. Summary of the invention

[0005] An object of an embodiment of the present invention is to provide a single-chip high-speed logic analyzer and a logic analysis method based on FPGA, so as to solve the technical problems of high cost, transmission delay, low bandwidth and low practicality of existing logic analyzers.

[0006] In a first aspect, an embodiment of the present invention provides a single-chip high-speed logic analyzer based on FPGA, characterized in that it includes an electrostatic discharge protection module, an external oscillator, a system clock generation module, a dual data rate IO port, a pulse width modulation module, a reference voltage module, a first interface and a second interface; the first interface is a USB2.0 interface, and the first interface is used to receive an acquisition instruction from an external host computer, so that the single-chip high-speed logic analyzer based on FPGA parses the acquisition instruction to obtain acquisition parameters, and the acquisition parameters are used to control the single-chip high-speed logic analyzer based on FPGA to perform data acquisition on a device to be acquired to obtain target data; the second interface is used to transmit the target data to the external host computer, and the second interface is a preset SerDes interface, and the preset SerDes interface is used to implement the data transmission function of the USB3.0 interface to perform high-speed data transmission.

[0007] In a second aspect, an embodiment of the present invention provides a logic analysis method, characterized in that a single-chip high-speed logic analyzer based on FPGA is applied to a logic analysis system, wherein the logic analysis system further includes a host computer and a device to be collected, and the method includes:

[0008] Receiving a collection instruction sent by the host computer through the first interface;

[0009] Parsing the acquisition instruction to obtain acquisition parameters, wherein the acquisition parameters are used to control the FPGA-based single-chip high-speed logic analyzer to perform data acquisition on the device to be acquired;

[0010] According to the acquisition instruction and the acquisition parameters, data is collected from the device to be collected to obtain target data;

[0011] The target data is sent to the host computer through the second interface, and the host computer parses the target data to display the waveform corresponding to the target data. The second interface is a preset SerDes interface, and the preset SerDes interface is used to implement the data transmission function of the USB3.0 interface.

[0012] In a third aspect, an embodiment of the present invention provides a computer device, including:

[0013] at least one processor; and,

[0014] a memory communicatively connected to the at least one processor; wherein,

[0015] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to the second aspect.

[0016] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the processor executes the method as described in the second aspect.

[0017] In the scheme implemented by the above-mentioned FPGA-based single-chip high-speed logic analyzer, logic analysis method, device and storage medium, the FPGA-based single-chip high-speed logic analyzer includes an electrostatic discharge protection module, an external oscillator, a system clock generation module, a double data rate IO port, a pulse width modulation module, a reference voltage module, a first interface and a second interface; the first interface is a USB2.0 interface, and the first interface is used to receive an acquisition instruction from an external host computer, so that the FPGA-based single-chip high-speed logic analyzer parses the acquisition instruction to obtain acquisition parameters, and the acquisition parameters are used to control the FPGA-based single-chip high-speed logic analyzer to perform data acquisition on the device to be acquired to obtain target data; the second interface is used to transmit the target data to the external host computer, and the second interface is a preset SerDes interface, and the preset SerDes interface is used to implement the data transmission function of the USB3.0 interface to perform high-speed data transmission. This solution uses a preset SerDes interface to achieve data transmission at the speed of the USB3.0 interface, significantly improving the speed of data acquisition, and is particularly suitable for acquiring high-speed signals; further, since data is directly transmitted through the preset SerDes interface, the cache chip required in the traditional USB2.0 interface logic analyzer is reduced, thereby reducing the delay in the cache + transmission process; further, the use of the cache chip is omitted, which not only reduces the hardware cost, but also reduces the volume and weight of the overall equipment, so that the production cost and maintenance cost are effectively controlled; therefore, this solution realizes a single-chip high-speed logic analyzer based on FPGA, and on the basis of maintaining a high acquisition rate and real-time performance, further simplifies the design of the logic analyzer, reduces the cost, and reduces the area of ​​the logic analyzer. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0019] Figure 1 is a structural schematic diagram of a logic analysis system in one embodiment of the present invention;

[0020] Figure 2AIt is a structural schematic diagram of a single-chip high-speed logic analyzer based on FPGA in one embodiment of the present invention;

[0021] Figure 2B is a structural schematic diagram of a second interface in one embodiment of the present invention;

[0022] Figure 3 is a flow chart of a logic analysis method in one embodiment of the present invention;

[0023] Figure 4 It is a schematic diagram of the structure of a computer device in one embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0025] It should be noted that, if there is no conflict, the various features in the embodiments of the present invention can be combined with each other, all within the scope of protection of the present invention. In addition, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in a different order from the module division in the device or the flow chart. Furthermore, the words "first", "second", "third", etc. used in the present invention do not limit the data and execution order, but only distinguish the same items or similar items with basically the same functions and effects.

[0026] The technical solution of the present application can be applied to various logic analysis usage scenarios.

[0027] In view of this, the present application proposes a logic analysis method to solve the above problems, which is introduced in detail below.

[0028] See also Figure 1 In this solution, a single-chip high-speed logic analyzer 20 based on FPGA, a host computer 30 and a device to be collected 40 constitute a logic analysis system 10.

[0029] Among them, the single-chip high-speed logic analyzer 20 based on FPGA is responsible for collecting, processing and transmitting the digital signals of the device to be collected 40. Utilizing the high programmability of FPGA, the logic analyzer 20 can perform complex signal processing tasks, such as signal triggering, data capture, timing analysis, etc. The logic analyzer 20 is usually equipped with multiple IO interfaces for communicating with the host computer 30 and the device to be collected 40. In particular, the collected signal data is transmitted to the host computer through the USB3.0 interface realized by the SerDes interface, ensuring the rapidity and stability of data transmission.

[0030] The host computer 30 is usually a computer or workstation, which is responsible for sending acquisition instructions, receiving and analyzing data collected by the logic analyzer 20. The software running on the host computer 30 provides a user interface, allowing the user to configure acquisition parameters, control the acquisition process, and display and analyze waveform data in real time. The host computer 30 is connected to the logic analyzer 20 via USB, Ethernet or other communication interfaces for command and data transmission.

[0031] The device to be collected 40 is the target device to be monitored and analyzed by the logic analyzer 20, and can be any electronic component or system that generates digital signals. The signal line of the device to be collected 40 is connected to the IO interface of the logic analyzer 20 through an appropriate interface for signal collection.

[0032] Therefore, through reasonable configuration and collaborative work, the logic analysis system 10 can efficiently and accurately complete the acquisition and analysis tasks of complex signals, providing users with powerful data analysis and signal debugging capabilities.

[0033] See also Figure 2A , Figure 2A A schematic diagram of the structure of a single-chip high-speed logic analyzer 20 based on FPGA provided in an embodiment of the present invention. The single-chip high-speed logic analyzer 20 based on FPGA includes an electrostatic discharge protection module 201, an external oscillator 202, a system clock generation module 203, a double data rate IO port 204, a pulse width modulation module 205, a reference voltage module 206, a first interface 207 and a second interface 208; the first interface 207 is a USB2.0 interface, and the first interface 207 is used to receive an acquisition instruction from an external host computer 30, so that the single-chip high-speed logic analyzer 20 based on FPGA parses the acquisition instruction to obtain acquisition parameters, and the acquisition parameters are used to control the single-chip high-speed logic analyzer 20 based on FPGA to perform data acquisition on a device to be acquired 40 to obtain target data; the second interface 208 is used to transmit the target data to the external host computer 30, and the second interface 208 is a preset SerDes interface, and the preset SerDes interface is used to implement the data transmission function of the USB3.0 interface to perform high-speed data transmission.

[0034] Among them, the electrostatic discharge (ESD) protection module 201 is used to prevent static electricity from damaging the FPGA chip and its peripheral circuits. It usually includes transient voltage suppressor (TVS) diodes, resistors, capacitors and other components, which are used to quickly guide overvoltage to the ground when an ESD event occurs, thereby protecting sensitive electronic components. In high-speed signal transmission, static electricity may cause data errors or equipment damage, so ESD protection is an important part of ensuring system reliability.

[0035] In one embodiment, the external oscillator 202 is used to provide a basic clock signal. The external oscillator 202 serves as the basis for the internal clock generation of the FPGA. It usually has high stability and accuracy. The frequency of the external oscillator determines the basic frequency of the system clock, affecting the synchronization and timing accuracy of the entire system.

[0036] Optionally, the external oscillator 202 also serves as the clock source of the second interface 208, which is the basic clock of USB3.0. At each rising edge of pclk, the data acquisition part will send 32-bit data to the USB3 PHY IP.

[0037] In one embodiment, the system clock generation module 203 is used to multiply the basic clock signal provided by the external oscillator 202 by an internal PLL frequency multiplication to obtain a sampling clock frequency.

[0038] Specifically, the system clock generation module 203 generates various clock signals required by the system, including the base clock and the multiplied sampling clock, based on the signal of the external oscillator 202. Through PLL or digital clock manager (DCM), the system clock generation module 203 can flexibly adjust the clock frequency to meet different acquisition requirements and ensure the correct timing of the internal logic and IO operations of the FPGA.

[0039] For example, the FPGA uses an external 125M active crystal oscillator (external oscillator 202) as a basic clock input, and uses an internal PLL to multiply the frequency to 125M, 250M, 375M, and 500M as a data sampling clock.

[0040] In one embodiment, the double data rate IO port 204 implements an adjustable level threshold through SSTL level configuration to ensure identification and acquisition of the device to be acquired.

[0041] The double data rate (DDR) IO port 204 allows data to be transmitted twice (rising edge and falling edge) in one clock cycle, thereby increasing the data transmission rate. In high-speed data acquisition, DDR technology can effectively increase data bandwidth and improve acquisition efficiency.

[0042] In one embodiment, the double data rate IO port 204 performs data sampling using a double data rate acquisition mode, wherein the double data rate acquisition mode triggers sampling at both the rising edge and the falling edge of the sampling clock frequency to achieve a doubling of the sampling rate.

[0043] For example, FPGA uses the SDR acquisition method, which triggers sampling at both the rising and falling edges of the sampling reference clock to double the sampling rate. That is, under the previous reference clock, the sampling rates of 250M, 500M, 750M, and 1000M are achieved respectively.

[0044] The reference voltage module 206 provides a stable voltage reference for biasing analog circuits and level setting of IO interfaces, ensuring the accuracy and consistency of signal acquisition, especially when processing analog signals.

[0045] The first interface 207 (USB 2.0 interface) receives the acquisition instruction from the external host computer 30 and transmits the configuration parameters, and supports reliable communication with the host computer 30 by using the USB 2.0 protocol stack and hardware interface.

[0046] This solution uses a preset SerDes interface to achieve data transmission at the speed of the USB3.0 interface, significantly improving the speed of data acquisition, and is particularly suitable for acquiring high-speed signals; further, since data is directly transmitted through the preset SerDes interface, the cache chip required in the traditional USB2.0 interface logic analyzer is reduced, thereby reducing the delay in the cache + transmission process; further, the use of the cache chip is omitted, which not only reduces the hardware cost, but also reduces the volume and weight of the overall equipment, so that the production cost and maintenance cost are effectively controlled; therefore, this solution realizes a single-chip high-speed logic analyzer based on FPGA, and on the basis of maintaining a high acquisition rate and real-time performance, further simplifies the design of the logic analyzer, reduces the cost, and reduces the area of ​​the logic analyzer.

[0047] In one embodiment, the second interface 208 is a preset SerDes interface, which includes a receiver, a transmitter, a clock data recovery module, a serial to parallel converter, a buffer, a decoding module, an encoding module, a first protocol interface, a second protocol interface, and a parallel to serial converter.

[0048] Among them, see Figure 2B , Figure 2B A schematic diagram of the structure of a second interface provided by an embodiment of the present invention. Figure 2BThe figure shows the complete structure of the SerDes interface. It is mainly used to convert parallel data into serial data for transmission, and then restore the received serial data to parallel data. The figure describes in detail the components of the SerDes interface and its data flow.

[0049] Specifically, in Figure 2B In the example, SerDes Rx is a receiver responsible for receiving incoming serial data. The first and second pins of the receiver are used to receive differential signals. SerDes Tx is a transmitter responsible for converting parallel data into serial data and transmitting it. The third and fourth pins of the transmitter are used to send differential signals.

[0050] In one embodiment, the receiver includes a first pin and a second pin, and the first pin and the second pin are used to receive differential signals; the transmitter includes a third pin and a fourth pin, and the third pin and the fourth pin are used to send differential signals.

[0051] The receiver and transmitter are responsible for converting parallel data into serial data and vice versa. The SerDes Rx receives serial data from the physical medium and converts it into parallel data for subsequent modules to use; while the SerDes Tx converts parallel data into serial data and then sends it out through the physical medium.

[0052] Among them, the first pin, the second pin, the third pin and the fourth pin are the input and output ports of the physical layer, which are used to connect to the actual physical link. Specifically, the first pin can be RXN, which is used to receive the negative polarity signal input terminal; the second pin can be RXN, which is used to receive the negative polarity signal input terminal. The two input terminals (RXP and RXN) together constitute a complete differential signal receiving path to ensure accurate signal reception and noise immunity.

[0053] The third pin may be TXP, which is the positive output terminal of the differential signal pair. The fourth pin may be TXN, which is the negative output terminal of the differential signal pair. TXP and TXN, as differential outputs, can provide high-speed, high-bandwidth data transmission while maintaining signal stability and reliability.

[0054] Specifically, CDR is a clock data recovery module, which is used to extract the clock signal from the received serial data and synchronize it to the local clock domain. At the same time, it is also responsible for recovering the original data bits from the serial data.

[0055] Specifically, Elastic Buffer is a buffer used to temporarily store and decouple the differences between data streams of different speeds. It can absorb sudden changes in data flow and ensure that downstream modules are not affected by speed fluctuations of upstream modules.

[0056] Specifically, 8b / 10b Decode is a decoding module that decodes the received encoded data to restore the original data.

[0057] Specifically, 8b / 10b Encode is an encoding module that encodes data before it is sent to improve transmission efficiency and data anti-interference ability. 8b / 10b Encode encodes 8-bit data into 10 bits to ensure DC balance and synchronization of data transmission. The encoding process adds redundancy to help error detection.

[0058] Specifically, Serial to Parallel is a serial to parallel converter that converts received serial data into parallel data for subsequent processing.

[0059] Specifically, Parallel to Serial is a parallel to serial converter that converts internally processed parallel data into serial data for transmission through a transmitter.

[0060] The Serial to Parallel and Parallel to Serial modules respectively realize the conversion between serial data and parallel data. The Serial to Parallel module converts the serial data received from the PIPE interface into parallel data, while the Parallel to Serial module does the opposite.

[0061] Specifically, the PIPE Interface and the PIPI Interface correspond to the first protocol interface and the second protocol interface respectively, support the implementation of different communication protocols, and ensure compatibility with a host computer or other devices.

[0062] Among them, PIPI Interface is located at the top level, serving as the entrance and exit of the entire system, responsible for communicating with other systems or devices. PIPE Interface connects the PIPI interface and the data processing module below.

[0063] Among them, this solution does not require additional buffering during implementation, and uses the high bandwidth of USB3.0 for direct transmission, and performs data processing and display on the host computer. The maximum transmission rate of USB3 PHY is 125Mx32bit, that is, theoretically, 16 channels can be collected simultaneously at 250M, 8 channels can be collected simultaneously at 500M, and 4 channels can be collected simultaneously at 100M. In fact, due to the influence of different host computer configurations and the convenient setting of system clock integer multiples, the conservatively set parameters of the USB3.0 logic analyzer are: 125M@16CH, 375M@8CH, 750M@4CH, 1500M@2CH.

[0064] It should be noted that, in each of the above-mentioned embodiments, there is not necessarily a certain order between the above-mentioned steps. A person skilled in the art can understand, based on the description of the embodiments of the present application, that in different embodiments, the above-mentioned steps may have different execution orders, that is, they may be executed in parallel, may be executed interchangeably, and so on.

[0065] See also Figure 3 , Figure 3 A flow chart of a logic analysis method provided in an embodiment of the present invention is applied to a single-chip high-speed logic analyzer based on FPGA in a logic analysis system, wherein the logic analysis system further includes a host computer and a device to be collected. The method includes the following steps:

[0066] S10. Receive a collection instruction sent by the host computer through the first interface.

[0067] Among them, FPGA (Field-Programmable Gate Array) is a programmable logic device that can be configured by the user after production to achieve specific hardware functions. FPGA-based logic analyzers take advantage of the flexibility and high-speed processing capabilities of FPGAs to customize data acquisition, processing, and transmission functions.

[0068] The communication interface of the first interface standard can be a USB 2.0 interface. The first interface is responsible for establishing a communication connection with a host computer (such as a computer, a workstation, etc.) to ensure that the instructions can be accurately transmitted to the logic analyzer. The USB 2.0 interface has wide compatibility and stable transmission performance and is suitable for most computing devices.

[0069] Among them, the acquisition instruction is a command generated by the host computer software. The acquisition instruction contains the parameters and settings that the logic analyzer needs to follow during the data acquisition process, such as sampling rate, trigger conditions, data depth, etc.

[0070] In a specific implementation, the user connects the first interface of the logic analyzer to the USB port of the host computer through a USB2.0 cable. The host computer identifies the newly connected device and loads the corresponding driver to establish communication with the logic analyzer. The user sets the acquisition parameters in the host computer, such as sampling rate, trigger mode, channel selection, etc.; after the user confirms the settings, the host computer encodes these parameters into a specific instruction format and sends them to the logic analyzer through the USB2.0 interface.

[0071] It can be seen that the single-chip high-speed logic analyzer based on FPGA in this embodiment can efficiently and accurately receive and execute the acquisition instructions sent by the host computer.

[0072] S20, parsing the acquisition instruction to obtain acquisition parameters, where the acquisition parameters are used to control the FPGA-based single-chip high-speed logic analyzer to perform data acquisition on the device to be acquired.

[0073] The acquisition parameters may include but are not limited to sampling rate, number of sampling points, sampling channel, trigger mode, trigger level, etc.

[0074] The sampling rate may include but is not limited to 250M, 500M, 750M, and 1000M.

[0075] Specifically, the sampling rate defines the number of times data is collected per second, usually in megasamples per second (MS / s). The higher the sampling rate, the richer the signal details that can be captured. In FPGA, the sampling rate is controlled by the clock management unit and can be adjusted by the internal PLL multiplication or division. The number of sampling points (Sample Depth) refers to the number of data points that the logic analyzer can collect and store after a trigger. The more points, the longer the signal history that can be traced back and analyzed. The number of sampling points is limited by the capacity of the internal storage resources of the FPGA. Sampling channels (Channels) refer to the number of channels that the logic analyzer can collect data simultaneously. Each channel can be set independently to collect different signals. The number of FPGA IO ports determines the number of available sampling channels. Trigger mode (Trigger Mode) defines the conditions for the logic analyzer to start collecting data. Common trigger modes include edge trigger, level trigger, _PATTERN trigger, etc. The trigger mode is implemented by the trigger logic unit inside the FPGA, and data collection can be started according to preset conditions. Trigger level (Trigger The trigger level refers to the voltage level that the logic analyzer needs to reach to recognize signal changes in trigger mode. The trigger level can be set by the user according to the characteristics of the signal to be collected to ensure accurate triggering.

[0076] In the specific implementation process, when the acquisition instructions arrive at the FPGA-based single-chip high-speed logic analyzer through the first interface (such as USB2.0), a special module (usually a hard-core processor or a soft-core processor) inside the FPGA will be responsible for parsing these instructions. The parsing module will extract the values ​​of various parameters, such as sampling rate, number of sampling points, etc., from the received data stream according to the predetermined protocol.

[0077] Once the acquisition parameters are parsed and confirmed, the FPGA will configure its internal data acquisition logic according to these parameters to ensure that the logic analyzer can perform data acquisition according to the expected parameters. For example, adjust the clock frequency to set the sampling rate, allocate memory resources to determine the number of sampling points, configure IO ports to select sampling channels, etc. When all parameters are configured, the logic analyzer will enter the waiting state. Once the trigger condition is met, the FPGA will start to collect data according to the set parameters.

[0078] It can be seen that, through analysis and parameter setting in this embodiment, the FPGA-based single-chip high-speed logic analyzer can flexibly and efficiently perform data acquisition and adapt to various complex signal analysis requirements.

[0079] S30: performing data collection on the device to be collected according to the collection instruction and the collection parameters to obtain target data.

[0080] After receiving the acquisition instruction and parsing the acquisition parameters, the FPGA will initialize its internal data acquisition hardware, including IO ports, clock management units, trigger logic units, and storage buffers. The IO port will be configured as an input mode, and the appropriate electrical characteristics (such as voltage threshold, input impedance, etc.) will be set to match the signal characteristics of the device to be acquired. According to the sampling rate, the clock management unit inside the FPGA will generate a stable sampling clock signal. If necessary, the PLL will be used to multiply or divide the frequency to obtain the required sampling rate.

[0081] The acquisition process is usually initiated by a trigger mechanism. Based on the preset trigger mode and trigger level, the logic analyzer starts acquisition when a specific signal condition is detected. For example, edge triggering starts acquisition when the signal rises or falls to a certain level. Once the trigger condition is met, the logic analyzer starts capturing signal data at the set sampling rate. The high-speed processing capability of FPGA enables it to capture a large number of data points in a short period of time, ensuring that signal details are not lost. If multiple sampling channels are specified in the acquisition parameters, the logic analyzer will synchronously acquire signals from different channels.

[0082] Optionally, when acquiring multiple channels, it is necessary to ensure that the sampling of all channels is performed synchronously to maintain the relative time relationship between the signals.

[0083] Optionally, prior to data acquisition, the signal may need to be conditioned, such as amplified, filtered, or level shifted, to ensure that the signal fits within the input range of the FPGA.

[0084] Optionally, the collected data is temporarily stored in buffers inside the FPGA. These buffers can be block RAM or distributed RAM of the FPGA, and their size determines the number of data points that can be stored. If the amount of data exceeds the size of the buffer, a circular buffer or external memory (such as SDRAM) may be used to store the data.

[0085] The target data refers to the data set that meets the user's needs, which may include data before and after the trigger point, depending on the number of sampling points and the trigger position.

[0086] It can be seen that in this embodiment, by collecting instructions and parameters, the FPGA-based single-chip high-speed logic analyzer can efficiently and accurately collect data from the acquisition device, and use the collected target data for subsequent analysis and processing.

[0087] S40, sending the target data to the host computer through the second interface, the host computer parses the target data to display a waveform diagram corresponding to the target data, the second interface is a preset SerDes interface, and the preset SerDes interface is used to implement the data transmission function of the USB3.0 interface.

[0088] Among them, the preset SerDes (Serializer / Deserializer) interface is a technology that converts parallel data into serial data (and vice versa). It plays a key role in high-speed data transmission. In this solution, the preset SerDes interface is used to implement the data transmission function of the USB3.0 interface. The USB3.0 interface is suitable for the fast transmission of large amounts of data with its high bandwidth and stability. In this implementation, the SerDes technology is responsible for converting the parallel data inside the FPGA into a serial data format suitable for USB3.0 transmission.

[0089] Before data transmission, the target data is formatted and packaged inside the FPGA to meet the requirements of the USB3.0 transmission protocol. This includes steps such as data serialization and frame synchronization. Once the data is prepared, the FPGA starts data transmission through the SerDes interface. The high-speed characteristics of the USB3.0 interface ensure that the data can be transmitted to the host computer in a short time, supporting real-time data analysis.

[0090] Furthermore, the host computer receives the serial data stream from the logic analyzer through the USB3.0 interface and deserializes it into parallel data using the corresponding SerDes technology. The host computer software decodes the data according to the preset protocol or format and converts the original binary data into usable numerical values. The decoded data is mapped to the time axis to form a waveform. The waveform is an important tool for signal analysis, which intuitively shows the trend of signal changes over time.

[0091] It can be seen that the USB 3.0 transmission function implemented by the preset SerDes interface in this embodiment has good compatibility and can adapt to different host computer devices.

[0092] The method receives the acquisition instruction sent by the host computer through the first interface, thereby flexibly configuring the acquisition behavior of the logic analyzer, improving the applicability and ease of operation of the device; further, by parsing the acquisition instruction to obtain accurate acquisition parameters, the accuracy and effectiveness of data acquisition can be ensured to meet the requirements of different test scenarios; and the data transmission function of the USB3.0 interface is realized by using the preset SerDes interface, which can greatly improve the data transmission speed, meet the requirements of high-speed data transmission, and reduce transmission delay; further, the host computer parses the target data and displays the corresponding waveform diagram, so that the user can observe and analyze the data in real time, improving the practicality of the system and user experience.

[0093] In one embodiment, data is collected from the device to be collected according to the collection instruction and the collection parameters to obtain target data, including: setting the IO interface standard of the FPGA-based single-chip high-speed logic analyzer according to the collection parameters, so that the IO interface standard realizes an adjustable level threshold through SSTL level configuration to ensure identification and collection of the device to be collected; multiplying the basic clock signal according to the collection parameters to obtain a sampling clock frequency; and continuously performing digital level sampling on the device to be collected according to the IO interface standard, the sampling clock frequency and a preset collection mode to obtain target data.

[0094] Among them, the FPGA's IO interface is used to exchange data with external devices. Correctly configuring these interfaces is the basis for ensuring the accuracy of signal acquisition.

[0095] Among them, SSTL (Stub Series Terminated Logic) is a commonly used IO standard suitable for high-speed signal transmission. Through SSTL level configuration, an adjustable level threshold can be achieved to adapt to different signal level standards.

[0096] Among them, according to the acquisition parameters, the FPGA can dynamically adjust the level threshold of the IO interface to ensure the correct identification and acquisition of devices with different level standards.

[0097] Among them, there is usually a basic clock signal inside the FPGA, which serves as the benchmark for all timing operations.

[0098] According to the acquisition parameters, the logic analyzer needs a higher sampling clock frequency. Through frequency multiplication, the basic clock signal can be increased to the required sampling frequency. The frequency multiplication process is usually implemented through PLL or digital clock manager (DCM).

[0099] The sampling clock frequency determines the time resolution of data acquisition. A higher sampling frequency can capture more subtle signal changes. However, too low a frequency may lead to information loss, while too high a frequency increases the complexity of processing.

[0100] The preset acquisition mode defines how to process and store the collected data. The preset acquisition mode may include whether to enable the trigger mechanism, the data storage strategy (such as a ring buffer), and the data preprocessing method (such as filtering).

[0101] Specifically, after configuring the IO interface standard and sampling clock, the logic analyzer begins to continuously sample the digital level of the acquisition device. This process involves converting analog signals into digital signals and recording data at the set sampling rate. Through continuous sampling, the digital signal data collected by the logic analyzer is processed and stored to form the target data.

[0102] It can be seen that in this embodiment, by collecting instructions and parameters, the FPGA-based single-chip high-speed logic analyzer can efficiently and accurately collect the signal to be tested, and provide necessary data support for subsequent host computer analysis and waveform display.

[0103] It should be noted that, in each of the above-mentioned embodiments, there is not necessarily a certain order between the above-mentioned steps. A person skilled in the art can understand, based on the description of the embodiments of the present application, that in different embodiments, the above-mentioned steps may have different execution orders, that is, they may be executed in parallel, may be executed interchangeably, and so on.

[0104] See also Figure 4 , Figure 4 4 is a schematic diagram of a computer device provided in an embodiment of the present application. The computer device includes one or more processors 41 and a memory 42. The memory 42 is connected to the one or more processors 41, for example, connected to the processor 41 via a bus.

[0105] The processor 41 is configured to support the computer device to perform the corresponding functions in the method in the above method embodiment. The processor 41 can be a central processing unit (CPU), a network processor (NP), a hardware chip or any combination thereof. The above hardware chip can be an application specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0106] The memory 42 is used to store program codes, etc. The memory 42 may include a volatile memory (VM), such as a random access memory (RAM); the memory 42 may also include a non-volatile memory (NVM), such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD); the memory 42 may also include a combination of the above-mentioned types of memories.

[0107] The memory 42 can be used to store non-volatile software programs, non-volatile computer executable programs and modules, such as program instructions / modules corresponding to the logic analysis method in the embodiment of the present application. The processor 41 executes the logic analysis method and various functional applications and data processing of the single-chip high-speed logic analyzer based on FPGA by running the non-volatile software programs, instructions and modules stored in the memory 42, that is, realizes the functions of the logic analysis method provided by the above method embodiment and the various modules or units of the single-chip high-speed logic analyzer based on FPGA.

[0108] The memory 42 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required by at least one function. The data storage area may store data created according to the use of the FPGA-based single-chip high-speed logic analyzer, etc. In some embodiments, the memory 42 may optionally include a memory 42 remotely arranged relative to the processor 41, and these remote memories 42 may be connected to the FPGA-based single-chip high-speed logic analyzer via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0109] The memory 42 can be used to store non-volatile software programs, non-volatile computer executable programs and modules, such as program instructions / modules corresponding to the logic analysis method in the embodiment of the present application. The processor 41 executes the various functional applications and data processing of the logic analysis method and the motion damping device of the adaptive S-type planning curve by running the non-volatile software programs, instructions and modules stored in the memory 42, that is, realizes the functions of each module or unit of the logic analysis method and the motion damping device of the adaptive S-type planning curve provided in the above method embodiment.

[0110] The memory 42 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required by at least one function. The data storage area may store data created according to the use of the motion damping device of the adaptive S-shaped planning curve, etc. In some embodiments, the memory 42 may optionally include a memory 42 remotely arranged relative to the processor 41, and these remote memories 42 may be connected to the motion damping device of the adaptive S-shaped planning curve via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0111] The one or more modules are stored in the memory 42, and when executed by the one or more processors 41, they execute the logical analysis method in any of the above method embodiments, for example, execute the method steps described in the above method embodiments to realize the functions of the modules described in the above device embodiments.

[0112] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a computer, the computer executes the method described in the above embodiment.

[0113] A person skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0114] The above disclosure is only the preferred embodiment of the present application, which certainly cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are still within the scope covered by the present application.

Claims

1. A single-chip high-speed logic analyzer based on FPGA, characterized in that: It includes an electrostatic discharge protection module, an external oscillator, a system clock generation module, a dual data rate IO port, a pulse width modulation module, a reference voltage module, a first interface and a second interface; the first interface is a USB2.0 interface, and the first interface is used to receive an acquisition instruction from an external host computer, so that the FPGA-based single-chip high-speed logic analyzer parses the acquisition instruction to obtain acquisition parameters, and the acquisition parameters are used to control the FPGA-based single-chip high-speed logic analyzer to perform data acquisition on the acquisition device to obtain target data; the second interface is used to transmit the target data to the external host computer, and the second interface is a preset SerDes interface, and the preset SerDes interface is used to realize the data transmission function of the USB3.0 interface to perform high-speed data transmission.

2. The single-chip high-speed logic analyzer based on FPGA according to claim 1, characterized in that: The external oscillator is used to provide a basic clock signal.

3. The single-chip high-speed logic analyzer based on FPGA according to claim 1, characterized in that: The system clock generation module is used to perform frequency multiplication processing on the basic clock signal provided by the external oscillator through internal PLL frequency multiplication to obtain a sampling clock frequency.

4. The single-chip high-speed logic analyzer based on FPGA according to claim 1, characterized in that: The dual data rate IO port realizes an adjustable level threshold through SSTL level configuration to ensure the identification and collection of the device to be collected.

5. The single-chip high-speed logic analyzer based on FPGA according to claim 1 or 4, characterized in that: The double data rate IO port uses a double data rate acquisition mode to perform data sampling. The double data rate acquisition mode achieves doubling of the sampling rate by triggering sampling at both the rising edge and the falling edge of the sampling clock frequency.

6. The single-chip high-speed logic analyzer based on FPGA according to claim 1, characterized in that: The second interface is a preset SerDes interface, which includes a receiver, a transmitter, a clock data recovery module, a serial to parallel converter, a buffer, a decoding module, an encoding module, a first protocol interface, a second protocol interface, and a parallel to serial converter.

7. The single-chip high-speed logic analyzer based on FPGA according to claim 6, characterized in that: The receiver includes a first pin and a second pin, and the first pin and the second pin are used to receive a differential signal; the transmitter includes a third pin and a fourth pin, and the third pin and the fourth pin are used to send a differential signal.

8. A logic analysis method, characterized in that: A single-chip high-speed logic analyzer based on FPGA applied to a logic analysis system, wherein the logic analysis system further comprises a host computer and a device to be collected, and the method comprises: Receiving a collection instruction sent by the host computer through the first interface; Parsing the acquisition instruction to obtain acquisition parameters, wherein the acquisition parameters are used to control the FPGA-based single-chip high-speed logic analyzer to perform data acquisition on the device to be acquired; According to the acquisition instruction and the acquisition parameters, data is collected from the device to be collected to obtain target data; The target data is sent to the host computer through the second interface, and the host computer parses the target data to display the waveform corresponding to the target data. The second interface is a preset SerDes interface, and the preset SerDes interface is used to implement the data transmission function of the USB3.0 interface.

9. The method according to claim 8, characterized in that The step of collecting data from the device to be collected according to the collection instruction and the collection parameters to obtain target data includes: The IO interface standard of the FPGA-based single-chip high-speed logic analyzer is set according to the acquisition parameters, so that the IO interface standard realizes an adjustable level threshold through SSTL level configuration to ensure the identification and acquisition of the device to be acquired; Perform frequency multiplication processing on the basic clock signal according to the acquisition parameters to obtain the sampling clock frequency; Continuously perform digital level sampling on the device to be sampled according to the IO interface standard, the sampling clock frequency and the preset acquisition mode to obtain target data.

10. A computer device, comprising a memory and a processor, wherein the memory is connected to the processor, and the processor is used to execute one or more computer programs stored in the memory, and when the processor executes the one or more computer programs, the computer device implements the method according to any one of claims 8 to 9.

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