Memory, control method thereof and electronic equipment

Abstract

The invention relates to a memory, a control method thereof and electronic equipment, the memory comprises a memory chip and a logic chip, the memory chip and the logic chip are packaged by adopting a three-dimensional stacking process, the memory has a memory mode and a calculation mode, and the memory is configured as follows: in the memory mode, the logic chip is connected with the memory chip; realizing information interaction of the storage chip through a first information interaction path; and in the calculation mode, realizing information interaction of the storage chip through a second information interaction path. According to the application, two information interaction channels are set, and the first information interaction channel enables information interaction to be more efficient; the second information interaction path provides higher data bandwidth for the logic chip; therefore, the memory provided by the invention has the two advantages, one interaction path can be flexibly selected according to requirements, and the application scene of the memory is enriched.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a memory and a control method thereof, and an electronic device. Background Art

[0002] like Figure 1 As shown, when the traditional two-dimensional memory communicates with the outside, it usually implements the corresponding function according to the commands or data sent by the external controller to the memory. The traditional two-dimensional memory interface circuit receives these commands or data and transmits these commands to the memory control logic circuit. The control logic further parses these commands into operation instructions of the memory control circuit, and controls the relevant circuits to execute the instruction operation through the control path to realize the system communication function; the data will be stored in the memory or read out from the memory according to these instruction operations. Therefore, in the traditional scheme, inside the memory chip, there is only one control path and data path for the memory circuit to communicate with the outside of the memory chip. The control path and data path usually pass through the interface circuit, data buffer circuit and control logic circuit inside the memory, and finally reach the memory circuit.

[0003] As the bottleneck of the memory "storage wall" becomes increasingly serious, three-dimensional memory realized through advanced packaging technology has gradually become the mainstream solution for improving memory data bandwidth and other performance indicators in the "post-Moore era". This type of architecture can package multiple memory chips and logic chips together, and realize the electrical connection between these chips through advanced packaging. However, the interface circuit of this type of memory is usually designed on the logic chip, which means that the memory circuit in the memory chip needs to pass through a longer control path and data path to complete the communication task with the outside. Such a control path and data path architecture has become a serious bottleneck for further improving the performance of this type of memory.

[0004] like Figure 2 As shown in the figure, HBM is a three-dimensional stacked memory based on TSV technology, usually composed of multiple DRAM memory chips and logic chips stacked. Its memory interface circuit is located on the bottom logic chip. Between different chips, the control path and the data path are vertical IO built by TSV technology. In the logic chip, the control path is designed between the interface circuit, control logic, memory chip controller and data buffer circuits, while the data path mainly exists between the interface circuit, data buffer and other circuits. In the memory chip, the control path mainly exists between the control circuit and the memory circuit, while the data path is mainly composed of the input or output channel of the data.

[0005] Although three-dimensional memories such as HBM have broken through the performance bottleneck of traditional two-dimensional memory chips to a certain extent through advanced packaging technology, the control path and data path of such memory chips are essentially no different from those of traditional two-dimensional memory chips. In particular, the path from the interface circuit to the storage circuit in the memory chip is even more complicated than that of traditional two-dimensional memory chips. Data needs to be transmitted over a long period of time to reach the interface circuit. It can be said that such a path architecture seriously affects the memory access efficiency.

[0006] Therefore, it is necessary to improve the existing memory. Summary of the invention

[0007] In response to the above problems, the present invention provides a memory, including a memory chip and a logic chip, wherein the memory chip and the logic chip are packaged using a three-dimensional stacking process, and the memory has a storage mode and a computing mode, and is configured as follows: in the storage mode, information interaction of the memory chip is achieved through a first information interaction path; and in the computing mode, information interaction of the memory chip is achieved through a second information interaction path.

[0008] The memory provided in the present application adaptively matches information interaction paths that meet the data transmission requirements and characteristics of each operating mode based on the different operating modes of the memory. According to the operation that the memory needs to perform, one of the information interaction paths that is more efficient in performing the operation can be flexibly selected. Compared with a memory in which all operations can be implemented through only one path, the overall performance of the memory is improved and its application scenarios are enriched.

[0009] Optionally, the memory also includes an interface circuit, which is configured for information exchange between the memory and the outside, the first information interaction path is arranged between the interface circuit and the memory chip, and the second information interaction path is arranged between the functional circuit of the logic chip and the memory chip.

[0010] Optionally, the functional circuit includes a circuit for realizing any function or a combination of error correction function, calculation functions such as multiplication, division, addition and subtraction, cache function, control function, protection function, drive function, load function, connection function and interface function.

[0011] Among them, the functional circuit may also include any of basic logic circuits (such as AND gates, OR gates, NOT gates, XOR gates, etc.), storage circuits (such as triggers, registers), timing control circuits (such as clocks, counters, timers) and data processing circuits (encoders, decoders, multiplexers, etc.) and their combinations.

[0012] The memory provided by the present application is provided with two information interaction paths, wherein the first information interaction path can directly realize the control of the memory chip and data transmission based on external instructions based on the interface circuit, making the information interaction more efficient; the second information interaction path, due to the use of the IO interface between the three-dimensional stacked chips realized by advanced packaging, significantly improves the resource utilization of the memory chip and provides a higher data bandwidth for the logic chip; therefore, the memory provided by the present application can take into account the above two advantages.

[0013] Optionally, the memory is also provided with a control circuit, which is connected to the first information interaction path and the second information interaction path. The control circuit can arbitrate based on the type of instructions for accessing the memory, and based on the arbitration result, selectively allow the memory to realize information interaction between the outside and the memory chip through the first information interaction path or the second information interaction path.

[0014] The memory provided in the present application, through the setting of the control circuit, can, on the one hand, coordinate the transmission of information through the interactive path of instructions according to preset rules, thereby avoiding errors and conflicts; on the other hand, the preset rules can be combined with the application scenario, so that the memory can always exchange information through the interactive path adapted to the current application scenario, taking into account both efficiency and bandwidth.

[0015] Optionally, the “the control circuit can arbitrate based on the type of instruction accessing the memory” includes:

[0016] If the type of instruction for accessing the memory is a memory access-related instruction, determining to implement information interaction between the external device and the memory chip through the first information interaction path; and

[0017] If the type of instruction for accessing the memory is a calculation-related instruction, it is determined that information interaction between the outside and the memory chip is implemented through the second information interaction path.

[0018] Optionally, the first information interaction path includes a first data path and a first control path, the second information interaction path includes a second data path and a second control path, the first data path and the second data path are used for data information transmission, the first control path and the second control path are used for control information transmission, the control circuit is arranged in the memory chip, and the memory chip further includes:

[0019] A storage circuit, used to implement a storage function, including a plurality of memory groups;

[0020] A plurality of data selection circuits are arranged corresponding to the plurality of memory groups, including a control end, a data interaction end, a first data path end and a second data path end, wherein the control end is connected to the control circuit, the data interaction end is connected to the plurality of memory groups, the first data path end and the second data path end are connected to the first data path and the second data path respectively, and the data selection circuit can selectively connect the data interaction end with the first data path end or the second data path end based on a signal from the control end.

[0021] Optionally, the interface circuit is arranged in the logic chip.

[0022] Optionally, the interface circuit is arranged in the storage chip.

[0023] Optionally, the memory chip is provided with a first interface corresponding to each memory group for information interaction with the logic chip. Accordingly, the logic chip is provided with a second interface corresponding to the position of the first interface in the stacking direction with the memory chip, and the first interface is connected to the second interface to form part of the second data path.

[0024] Such configuration can further increase the bandwidth of the second data path.

[0025] Optionally, the first interface and the second interface are electrically connected using TSV, hybrid bonding or hybrid bonding technology.

[0026] In order to achieve the above-mentioned object of the invention, the present application provides a memory control method, which is applied to control the memory mentioned above, comprising the steps of:

[0027] determining an operating mode of the memory; and

[0028] Based on the operation mode, an information interaction path matching the operation mode is selected to implement information interaction of the storage chip.

[0029] Optionally, the memory control method further includes:

[0030] Data consistency detection step: in response to the change / switching of the information interaction path, detecting the correctness of the data stored in the storage chip.

[0031] Based on the memory control method provided in the present application, the correctness of the data stored in the memory chip is ensured through data consistency detection when receiving data transmitted in different paths, thereby avoiding errors.

[0032] Optionally, the memory control method further includes:

[0033] Only one information exchange channel is accessible at a time.

[0034] Through the above method, not only can the data / instructions and paths be matched, but also at the same time, only one information interaction path can enter the working state. At this time, the other information interaction path enters the inaccessible state, thereby avoiding conflicts.

[0035] In order to achieve the above-mentioned purpose of the invention, the present application provides an electronic device using the memory described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is the architecture of the memory in the prior art.

[0037] Figure 2 It is a memory architecture packaged by a three-dimensional stacking process in the prior art.

[0038] Figure 3 It is a schematic diagram of the architecture of the memory provided in an embodiment of the present invention.

[0039] Figure 4 It is a schematic diagram of the architecture of the memory provided in an embodiment of the present invention.

[0040] Figure 5 It is a schematic diagram of the architecture of the memory provided in an embodiment of the present invention.

[0041] Figure 6 It is a schematic diagram of the steps of a memory control method provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] like Figure 3 As shown, this embodiment provides a memory, including a memory chip 100 and a logic chip 200. The memory chip 100 and the logic chip 200 are packaged using a three-dimensional stacking packaging process. The memory has a storage mode and a computing mode, and is configured as follows: in the storage mode, information interaction of the memory chip 100 is achieved through a first information interaction path; and in the computing mode, information interaction of the memory chip 100 is achieved through a second information interaction path.

[0044] Optionally, the memory also includes an interface circuit 300, which is configured for information exchange between the memory and the outside, a first information interaction path is set between the interface circuit 300 and the memory chip 100, and a second information interaction path is set between the functional circuit 250 of the logic chip 200 and the memory chip 100.

[0045] In other words, the memory is configured with a first information interaction path for directly interacting with the memory chip 100 via the interface circuit 300 , and a second information interaction path for interacting with the memory chip 100 via the functional circuit 250 of the logic chip 200 .

[0046] Among them, the functional circuit 250 includes any of the basic logic circuits (such as AND gates, OR gates, NOT gates, XOR gates, etc.), storage circuits (such as triggers, registers), timing control circuits (such as clocks, counters, timers) and data processing circuits (encoders, decoders, multiplexers, etc.) and their combinations; the functional circuit 250 also includes but is not limited to: circuits for realizing error correction functions, calculation functions such as multiplication, division, addition and subtraction, caching functions, control functions, protection functions, driving functions, load functions, connection functions, and interface functions.

[0047] In this embodiment, two information interaction paths are set up, among which the first information interaction path can directly realize the control of the memory chip 100 based on external instructions based on the interface circuit 300, so that the information interaction is more efficient; the second information interaction path, due to the use of the IO interface between the three-dimensional stacked chips realized by advanced packaging, significantly improves the resource utilization of the memory chip 100 and provides a higher data bandwidth for the logic chip 200; therefore, the memory provided by this embodiment can take into account the above two advantages, and can flexibly select one of the information interaction paths that is more efficient in executing the operation according to the operation that the memory needs to execute. Compared with the memory in which all operations can be implemented through only one path, the overall performance of the memory is improved and its application scenarios are enriched.

[0048] Optionally, the memory is further provided with a control circuit 400, and the control circuit 400 is connected to the first information interaction path and the second information interaction path, and the memory chip 100 is configured to selectively interact with the outside of the memory through the first information interaction path, or interact with the logic chip 200 through the second information interaction path based on the arbitration result of the control circuit 400. In this embodiment, through the setting of the control circuit 400, on the one hand, it is possible to coordinate the information to be transmitted through the specified interaction path according to the preset rules, thereby avoiding errors and conflicts. On the other hand, the preset rules can be combined with the application scenario, so that the memory can always interact with the information through the interaction path adapted to the current application scenario, so that different types of operation instructions can be selectively implemented through a more efficient information interaction path, taking into account both efficiency and bandwidth.

[0049] In other words, the control circuit 400 can arbitrate based on the instruction type for accessing the memory, and based on the arbitration result, selectively allow the memory to implement information interaction between the outside and the memory chip 100 through the first information interaction path or the second information interaction path.

[0050] The memory provided in this embodiment, through the setting of the control circuit 400, can, on the one hand, coordinate the transmission of information through the interactive path of instructions according to preset rules, thereby avoiding errors and conflicts; on the other hand, the preset rules can be combined with the application scenario, so that the memory can always exchange information through the interactive path adapted to the current application scenario, taking into account both efficiency and bandwidth.

[0051] Optionally, “the control circuit 400 is capable of arbitrating based on the type of instruction for accessing the memory” includes:

[0052] If the instruction type for accessing the memory is a memory access related instruction, determining to implement information interaction between the external device and the memory chip 100 through a first information interaction path; and

[0053] If the type of the instruction for accessing the memory is a calculation-related instruction, it is determined that information interaction between the external device and the memory chip 100 is implemented through the second information interaction path.

[0054] More specifically, when performing a traditional memory chip 100 access operation, information interaction can be achieved through the first information interaction path. Compared with the second information interaction path, the information transmission path is shortened. When performing operations such as data rearrangement and calculation, the second information interaction path has the advantage of bandwidth. The user can selectively transmit information based on the path that matches the interactive information, thereby improving the performance of the memory.

[0055] Since the types of information exchanged between the memory chip 100, the logic chip 200 and between the two and the external system mainly include control information and data information, in this embodiment, the first information exchange path includes a first data path (data path 1) for data exchange and a first control path (control path 1) for control instruction exchange, and the second information exchange path includes a second data path (data path 2) for data exchange and a second control path (control path 2) for control instruction exchange.

[0056] The control circuit 400 can be connected to the interface circuit 300 and the logic chip 200 through the first control path and the second control path respectively, and based on the control instruction, selectively enables the first data path or the second data path to perform data exchange with the memory chip 100.

[0057] The specific implementation scheme of the memory provided in this embodiment is exemplified below:

[0058] The control circuit 400 is arranged in the memory chip 100. In addition to the arbitration function described above, it can also realize the control of the memory circuit 110 of the memory chip 100. The memory circuit 110 includes a plurality of memory groups 111. The memory chip 100 also includes a plurality of data selection circuits 120 corresponding to the memory groups 111. The data selection circuit 120 has a control end, a data interaction end, a first data path end and a second data path end. The control end is connected to the control circuit 400. More specifically, the control end is connected to the arbitrator 410 arranged inside the control circuit 400, the data interaction end is connected to each memory group 111, and the first data path end and the second data path end are respectively connected to the first data path and the second data path.

[0059] Continue to refer Figure 3Optionally, the interface circuit 300 is arranged in the logic chip 200. In addition to the functional circuit 250, the logic chip 200 also includes: a control logic circuit 210, an interface data buffer circuit 220, a storage chip control circuit 230 and an internal data buffer circuit 240. It is used to buffer the data transmitted through the first data path. Among them, the control logic circuit 210 is connected to the interface circuit 300, and can convert external instructions into operation instructions such as the address, timing and control mode of the read and write operation. The storage chip control circuit 230 is respectively connected to the control logic circuit 210, the internal data buffer circuit 240, the functional circuit 250 and the control circuit 400, and can realize the control of the storage chip 100 by driving the control circuit 400. The functional circuit 250 can realize functions including logical calculation and control. It is connected to the storage chip control circuit 230 and the internal data buffer circuit 240, and can schedule the data buffered in the internal data buffer circuit 240, and can control the operation of the storage chip 100 through the storage chip control circuit 230 based on the calculation results and control tasks.

[0060] Figure 3 The specific working principle of the memory shown is:

[0061] The memory includes a storage mode and a calculation mode. In response to receiving instructions related to memory access, the interface circuit 300 issues instructions to the memory chip 100, causing the memory chip 100 to enter the storage mode. In the storage mode, the memory chip 100 receives instructions from the interface circuit 300 through the first control path, and writes data through the first data path (the data may include instructions from the functional circuit 250). In response to receiving instructions related to calculation, the interface circuit 300 issues instructions to the memory chip 100, causing the memory chip 100 to enter the calculation mode. In the calculation mode, the functional circuit 250 obtains instructions and data through the second data path, and processes the data based on the instructions.

[0062] It should be noted that, based on the different types of control instructions, the control arbitrator 410 sends an arbitration signal corresponding to the control instruction to the data selection circuit 120. Based on the arbitration signal, the data selection circuit 120 selects a path in the first data path and the second data path that matches the arbitration signal, and allows the path to interact with the memory group 111 through the data interaction terminal, thereby achieving accurate control of data path selection. At the same time, only one path can enter the working state. At this time, the other path enters an inaccessible state, thereby avoiding errors and conflicts.

[0063] Optionally, the first data path is formed by the interface circuit 300 → interface data buffer circuit 220 → memory chip 100 (data selection circuit 120), and the first control path is formed by the interface circuit 300 → control logic circuit 210 → memory chip control circuit 230 → memory chip 100 (control circuit 400); the second data path is formed by the functional circuit 250 → internal data buffer circuit 240 → memory chip 100 (data selection circuit 120), and the second control path is formed by the memory chip control circuit 230 → control circuit 400 / internal data buffer circuit 240 / functional circuit 250.

[0064] It should be noted that the “→” in the implementation manner is only used to express the information transmission path and does not constitute a limitation on the information transmission direction. In other words, various information can be bidirectionally interacted / transmitted between corresponding modules based on demand or instructions.

[0065] Since the advanced IO process of three-dimensional stacked packaging is applied between the internal data buffer circuit 240 and the data selection circuit 120, higher bandwidth data transmission is achieved compared with the first data path. Specifically, the internal data buffer circuit 240 and the data selection circuit 120 can be electrically connected by TSV, hybrid bonding or hybrid bonding technology. In addition, since the information transmission path of the first data path is shorter, the information transmission efficiency can be improved.

[0066] Optionally, in another embodiment of the present application, Figure 4 As shown, it is Figure 3 The difference between the memory shown in the figure is that the interface circuit 300 is arranged on the memory chip 100. In this case, the interface circuit 300 is directly connected to the control circuit 400 and the data selection circuit 120, the path of the information interaction path is shorter, and the advantage of efficient interaction can be better exerted. At the same time, there is no need to set an interface data buffer circuit and an interface circuit on the logic chip 200.

[0067] In this embodiment, a first data path is formed by an interface circuit 300 → a memory chip 100 (a data selection circuit 120); a first control path is formed by an interface circuit 300 → a memory chip 100 (a control circuit 400); a second data path is formed by an interface circuit 300 → a logic chip 200 (a functional circuit 250 → a data buffer circuit 240) → a memory chip 100 (a data selection circuit 120); and a second control path is formed by an interface circuit 300 → a logic chip 200 (a control logic circuit 210 → a memory chip control circuit 230; a functional circuit 250 → a memory chip control circuit 230; a data buffer circuit 240 → a memory chip control circuit 230) → a memory chip 100 (a control circuit 400).

[0068] pass Figure 3 and Figure 4 The paths of the data paths and control paths corresponding to the memory architecture shown can be learned. The first information interaction path (the first data path and the first control path) has a less complex path, so the information interaction is more efficient; the second information interaction path has a higher data bandwidth because its data transmission path is based on advanced packaging.

[0069] In addition, the advantages of setting the interface circuit 300 on the memory chip 100 also include: the interface circuit is generally a SerDes (Serialization / Deserialization) circuit, which is a high-speed serial-to-parallel / parallel-to-serial data conversion interface circuit, and its implementation method requires the use of analog circuit processes, including circuit design, circuit netlist simulation, layout design, parasitic parameter extraction and post-simulation, chip return test and other complex design and testing processes to ensure the correctness of the function; this means that if the interface circuit is migrated from one process to another, the above process needs to be re-performed, which brings a huge and complex workload, and the reliability cannot be guaranteed. The memory architecture provided by this embodiment sets the interface circuit on the memory chip, and does not need to migrate the interface circuit from the memory chip process to the logic chip process, thereby greatly reducing the design complexity and design difficulty of the three-dimensional stacked memory, and greatly improving the architectural iteration speed of such memory.

[0070] Alternatively, if Figure 5 As shown, in order to further increase the bandwidth advantage of the second information interaction path, the second information interaction path is designed as follows: the memory chip 100 is provided with a first interface 130 for data interaction with the logic chip 200 corresponding to each memory group 111. Accordingly, the logic chip 200 is provided with a second interface 260 in the stacking direction with the memory chip 100, taking the horizontal stacking of two chips as an example, that is, in the vertical direction, corresponding to the position of the first interface 130. The second interfaces 260 are all connected to the data buffer circuit 240 to form a part of the second data path. In this way, the logic chip 200 can control multiple memory groups 110 in the memory chip 100 to perform operations simultaneously, significantly improving the resource utilization of the memory chip 100 and providing a higher data bandwidth for the second information interaction path.

[0071] Furthermore, in this embodiment, different memory groups execute completely different, partially identical, or completely identical operations in response to corresponding control instructions.

[0072] In this way, compared with the memory in the prior art, the control method of the memory provided by this embodiment is more flexible, and different memory groups can execute different control instructions based on needs, thereby improving the utilization rate of the memory, the efficiency of data interaction and the diversity of working modes. Optionally, this embodiment also provides a control method for the memory, which is applied to control the memory provided by this embodiment, such as Figure 6 As shown, the steps include:

[0073] determining an operating mode of the memory; and

[0074] Based on the operation mode, an information interaction path matching the operation mode is selected to implement information interaction of the memory chip 100 .

[0075] Optionally, the memory control method further includes:

[0076] Data consistency detection step: In response to the change / switching of the information interaction path, the correctness of the data stored in the memory chip 100 is detected.

[0077] Specifically, it also includes: when responding to external memory access related instructions (such as read and write operations), it is determined that information interaction is achieved through a first information interaction path; when responding to calculation related instructions such as data rearrangement and calculation execution, it is determined that information interaction is achieved through a second information interaction path.

[0078] Among them, the purpose of data consistency detection is mainly to ensure that there is no data corruption or address error problem in the storage chip 100. Based on the memory control method provided in this embodiment, data consistency detection is used to ensure the correctness of the data stored in the storage chip when receiving data transmitted in different paths, thereby avoiding errors.

[0079] Optionally, the memory control method further includes: at the same time, only one information interaction path is in an accessible state.

[0080] Such a setting can not only achieve the matching of data / instructions and paths, but also only one information interaction path can enter the working state at the same time. At this time, the other information interaction path enters the inaccessible state, thereby avoiding conflicts.

[0081] Optionally, in this embodiment, the memory chip 100 is a Flash memory chip, a DRAM memory chip, an SRAM memory chip, an MRAM chip or an RRAM memory chip.

[0082] Optionally, the interface 120 of the memory group 110 is configured to receive any signal and a combination of address input signals, data input / output signals, word or byte selection input signals, hardware reset / sector protection unlock signals, output enable signals, command lane signals, address lane signals, Ready / Busy indication signals, differential clock signals, clock enable signals, chip select signals, row address select signals, column address select signals, write enable signals, data read and write clock signals, BANK address signals, data mask signals, termination resistor signals, calibration signals, command address signals, and data bus signals.

[0083] Optionally, when the memory has multiple layers of stacked memory chips, the upper memory chip and the bottom memory chip are connected via IO of the advanced packaging interface and are controlled by the memory group controller on the logic chip. For example, when a certain memory group controller on the logic chip is working, it can simultaneously access the memory groups corresponding to the memory group controller on these memory chips.

[0084] Optionally, this embodiment further provides an electronic device, which uses the memory provided by this embodiment, and the electronic device may be a computer.

[0085] So far, the technical solution of the present invention has been described in conjunction with the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to the above-mentioned specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A memory, characterized in that: The invention comprises a memory chip and a logic chip, wherein the memory chip and the logic chip are packaged by a three-dimensional stacking process, and the memory has a storage mode and a computing mode, and is configured as follows: In the storage mode, information interaction of the storage chip is realized through a first information interaction path; and In the computing mode, information interaction of the storage chip is achieved through a second information interaction path.

2. The memory according to claim 1, characterized in that: It also includes an interface circuit, which is configured to be used for the memory to exchange information with the outside, the first information interaction path is set between the interface circuit and the memory chip, and the second information interaction path is set between the functional circuit of the logic chip and the memory chip.

3. The memory according to claim 2, characterized in that: The functional circuit includes a circuit for realizing any function or a combination of the following functions: error correction function, calculation functions such as multiplication, division, addition and subtraction, cache function, control function, protection function, drive function, load function, connection function and interface function.

4. The memory according to claim 2 or 3, characterized in that: A control circuit is also provided, which is connected to the first information interaction path and the second information interaction path. The control circuit can arbitrate based on the type of instruction to access the memory, and based on the arbitration result, selectively allow the memory to realize information interaction between the outside and the storage chip through the first information interaction path or the second information interaction path.

5. The memory according to claim 4, characterized in that: The “the control circuit can arbitrate based on the type of instruction accessing the memory chip” includes: If the type of instruction for accessing the memory is a memory access-related instruction, determining to implement information interaction between the external device and the memory chip through the first information interaction path; and If the type of instruction for accessing the memory is a calculation-related instruction, it is determined that information interaction between the outside and the memory chip is implemented through the second information interaction path.

6. The memory according to claim 4, characterized in that: The first information exchange path includes a first data path and a first control path, the second information exchange path includes a second data path and a second control path, the first data path and the second data path are used for data information transmission, the first control path and the second control path are used for control information transmission, the control circuit is arranged in the memory chip, and the memory chip further includes: A storage circuit, used to implement a storage function, including a plurality of memory groups; A plurality of data selection circuits are arranged corresponding to the plurality of memory groups, including a control end, a data interaction end, a first data path end and a second data path end, wherein the control end is connected to the control circuit, the data interaction end is connected to the plurality of memory groups, the first data path end and the second data path end are connected to the first data path and the second data path respectively, and the data selection circuit can selectively connect the data interaction end with the first data path end or the second data path end based on a signal from the control end.

7. The memory according to any one of claims 1 to 3, characterized in that: The interface circuit is arranged on the logic chip.

8. The memory according to any one of claims 1 to 3, characterized in that: The interface circuit is arranged on the storage chip.

9. The memory according to claim 6, characterized in that: The memory chip is provided with a first interface corresponding to each memory group for information exchange with the logic chip. The logic chip is provided with a second interface corresponding to the position of the first interface in the stacking direction with the memory chip. The first interface is connected with the second interface to form part of the second data path.

10. The memory according to claim 9, characterized in that: The first interface and the second interface are electrically connected by using TSV, hybrid bonding or hybrid bonding technology.

11. A memory control method, applied to control the memory according to any one of claims 1 to 10, characterized in that: Includes steps: determining an operating mode of the memory; and Based on the operation mode, an information interaction path matching the operation mode is selected to implement information interaction of the storage chip.

12. The memory control method according to claim 11, characterized in that: Also includes: Data consistency detection step: in response to the change / switching of the information interaction path, detecting the correctness of the data stored in the storage chip.

13. An electronic device, characterized in that: Application of the memory described in any one of claims 1 to 10.

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