Low-noise fast duty cycle detector and duty cycle detection method thereof

Abstract

The invention relates to a low-noise fast duty cycle detector and a duty cycle detection method thereof. The duty cycle detector includes a current directing network to direct a first current to a second current to charge the first capacitance when the clock is in a first state of an even cycle and to direct the first current to a third current to charge the second capacitance when the clock is in a second state of the even cycle; the first charge sharing switch is used for promoting charge sharing between the first capacitor and the third capacitor when the clock is in the second state; the second charge sharing switch is used for promoting charge sharing between the second capacitor and the fourth capacitor when the clock is in the first state; the first discharge network is used for discharging the first capacitor when the clock is in a first state of an odd number period; and the second discharging network is used for discharging the second capacitor when the clock is in the second state of the odd number period.

Description

Technical Field

[0001] The present disclosure relates to duty cycle detectors, and more particularly to fast duty cycle detectors with low noise. Background Art

[0002] Many modern circuit systems require a precise clock signal to operate properly. A clock signal is a voltage signal that switches between a low state and a high state at regular intervals. The percentage of time that the voltage signal remains in the high state is called the duty cycle. Many circuits require a specific duty cycle to provide optimal performance, so a duty cycle detector is needed.

[0003] Some prior art duty cycle detection circuits use a low-pass filter to extract the DC level of the clock, which will be proportional to the duty cycle of the clock. In order to accurately extract the DC level, the cutoff frequency of the low-pass filter must be very small; therefore, it takes a long time to stabilize and detect the duty cycle. In other words, the duty cycle detector operates slowly.

[0004] Typically, an integrator circuit is used to generate a voltage that is proportional to the time the clock remains in the high state, and therefore proportional to the clock's duty cycle. The problem is that integrator circuits tend to generate a low-frequency noise that is called "flicker noise" in semiconductor components. This low-frequency noise can have a negative impact on the accuracy of duty cycle detection.

[0005] In view of this, a low noise and fast duty cycle detector is needed. Summary of the invention

[0006] In some embodiments, one of the objectives of the present disclosure is, but not limited to, to provide a duty cycle detector that can quickly detect the duty cycle of a clock.

[0007] In some embodiments, one of the objectives of the present disclosure is, but not limited to, to provide a duty cycle detector that can eliminate circuit noise.

[0008] In some embodiments, a duty cycle detection method includes: receiving a clock that periodically alternates between an even cycle and an odd cycle; using a current source to output a first current; when the clock is in a first state of the even cycle, directing the first current to a first capacitor and promoting charge sharing between a second capacitor and a fourth capacitor; when the clock is in a second state of the even cycle, directing the first current to the second capacitor and promoting charge sharing between the first capacitor and a third capacitor; when the clock is in the first state of the odd cycle, discharging the first capacitor and promoting charge sharing between the second capacitor and the fourth capacitor; and when the clock is in the second state of the odd cycle, discharging the second capacitor and promoting charge sharing between the first capacitor and the third capacitor.

[0009] In some embodiments, the duty cycle detector includes a current steering network for steering a first current into a second current to charge a first capacitor when a clock is in a first state of an even cycle, and steering the first current into a third current to charge a second capacitor when the clock is in a second state of the even cycle; a first charge sharing switch for facilitating charge sharing between the first capacitor and a third capacitor when the clock is in the second state; a second charge sharing switch for facilitating charge sharing between the second capacitor and a fourth capacitor when the clock is in the first state; a first discharge network for discharging the first capacitor when the clock is in the first state of an odd cycle; and a second discharge network for discharging the second capacitor when the clock is in the second state of the odd cycle.

[0010] In some embodiments, a duty cycle detection method includes: receiving a clock that periodically alternates between an even cycle and an odd cycle; using a current source to output a first current; establishing a four-stage continuous and cyclic timing scheme including a first stage, a second stage, a third stage, and a fourth stage according to the state of the clock and the state of a periodic signal that switches periodically and alternately; in the first stage, directing the first current to a first capacitor and promoting charge sharing between a second capacitor and a fourth capacitor; in the second stage, directing the first current to a second capacitor and promoting charge sharing between the first capacitor and a third capacitor; in the third stage, discharging the first capacitor and promoting charge sharing between the second capacitor and the fourth capacitor; and in the fourth stage, discharging the second capacitor and promoting charge sharing between the first capacitor and the third capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A flow chart of a working cycle detection method drawn according to some embodiments of the present disclosure;

[0012] Figure 2A An illustrative embodiment of the present disclosure is shown in FIG. Figure 1 A schematic diagram of a duty cycle detector of a duty cycle detection method;

[0013] Figure 2B According to some embodiments of the present disclosure Figure 2A A timing diagram of the operation of the duty cycle detector; and

[0014] Figure 3 A flow chart of another duty cycle detection method according to some embodiments of the present disclosure is shown.

[0015] Explanation of symbols

[0016] 100,300: Flowchart

[0017] 110,120,130,140,150,160: Step 200: Duty Cycle Detector (DCD)

[0018] 210: Current Source

[0019] 221~224,233~236,241,243,251,252: switch

[0020] 240: Divide by 2 Circuit

[0021] 242,244,253,254: AND gate

[0022] 310,320,330,340,350,360,370: Steps

[0023] C1: First capacitor

[0024] C2: Second capacitor

[0025] C3: The third capacitor

[0026] C4: The fourth capacitor

[0027] CB: Signal

[0028] CK: Clock

[0029] CSN: Current Steering Network

[0030] CSS1: The first charge sharing switch

[0031] CSS2: Second Charge Sharing Switch

[0032] DN1: First discharge network

[0033] DN2: Second discharge network

[0034] EC: Even-cycle signal

[0035] I1: First current

[0036] I2: Second current

[0037] I3: The third current

[0038] I cp : Charge pump current

[0039] I g : Ground current

[0040] OC: odd cycle signal

[0041] T: period

[0042] V1: first voltage

[0043] V2: Second voltage

[0044] V3: The third voltage

[0045] V4: fourth voltage

[0046] V DD : Supply voltage

[0047] φ1: First stage signal

[0048] φ2: Second stage signal

[0049] φ3: The third phase signal

[0050] φ4: Fourth stage signal DETAILED DESCRIPTION

[0051] The present disclosure relates to detecting duty cycles. Although this specification discloses several embodiments that may be considered as preferred examples for implementing the present disclosure, the present disclosure may be implemented in a variety of ways, and is not limited to the specific examples described below, nor to the specific ways in which the technical features of those specific examples are implemented. In addition, known details are not shown or described to avoid obstructing the presentation of the ideas of the present disclosure.

[0052] Those skilled in the art may understand the terms and basic concepts related to microelectronics used in the present disclosure, such as "voltage", "signal", "capacitor", "complementary metal oxide semiconductor (CMOS)", "P-type metal oxide semiconductor (PMOS)", "N-type metal oxide semiconductor (NMOS)", "switch", "low-pass filter", "clock", "cycle" and "duty cycle". The above terms and basic concepts are understandable to those skilled in the art, so their details are not repeated here.

[0053] A person skilled in the art can read the schematic diagram and recognize the circuit symbols such as switches, AND gates, grounds (corresponding to ground nodes), current sources, and capacitors therein, so no explanation is required.

[0054] The expressions of the present disclosure are based on engineering perspectives rather than strict mathematical meanings. For example, for two variables X and Y, when it is said that "variable X is equal to variable Y", it means "variable X is approximately the same as variable Y", that is, "the difference between variable X and variable Y is less than a specific engineering error". When it is said that "variable X is equal to 0", it means "variable X is approximately equal to 0", that is, "variable X is less than an engineering error". When it is said that "variable X is significantly less than variable Y", it means "variable X is negligible relative to variable Y", that is, "the ratio between variable X and variable Y is less than a specific engineering error, so variable X is negligible compared to variable Y".

[0055] In the present disclosure, a signal may be a voltage, the level of which may vary over time, and the level of the signal at a specific moment represents the state of the signal at the specific moment.

[0056] A logic signal is a voltage signal having two states: a first state and a second state. In some embodiments, the first state is a high state and the second state is a low state. In other embodiments, the first state is a low state and the second state is a high state. The low state may also be referred to as a "0" state, and the high state may also be referred to as a "1" state. For the logic signal Q, "logic signal Q is high" or "logic signal Q is low" represents "logic signal Q is in a high state" or "logic signal Q is in a low state". Similarly, "logic signal Q is 1" or "logic signal Q is 0" represents "logic signal Q is in a 1 state" or "logic signal Q is in a 0 state".

[0057] When the logic signal switches from low to high, it undergoes a transition from low to high and presents a rising edge. When the logic signal switches from high to low, it undergoes a transition from high to low and presents a falling edge.

[0058] If a first logic signal is referred to as a logical inversion of a second logic signal, the first logic signal and the second logic signal always have two opposite states. In other words, when the first logic signal is low (i.e., 0), the second logic signal is high (i.e., 1); when the first logic signal is high (i.e., 1), the second logic signal is low (i.e., 0). When the first logic signal is referred to as a logical inversion of the second logic signal, the first logic signal and the second logic signal are referred to as complements of each other.

[0059] A clock is a logic signal that switches back and forth between a low state and a high state periodically. A clock cycle begins with a low-to-high transition and ends before the next low-to-high transition.

[0060] The inverter receives the first logic signal and outputs a second logic signal, such that the second logic signal is the logical inversion of the first logic signal.

[0061] A switch is a device with two possible states ("on" and "off"). When the switch is in the "on" state, the switch is generally in a short circuit state. When the switch is in the "off" state, the switch is generally in an open circuit state. A switch can be implemented using an NMOS transistor or a PMOS transistor. When a MOS transistor (which can be an NMOS transistor or a PMOS transistor) is used to implement a switch, the switch can be controlled via a control signal, and the control signal is a logic signal applied to the gate of the transistor. A switch implemented by an NMOS transistor is in the "on" state when the control signal is high, and in the "off" state when the control signal is low. A switch implemented by a PMOS transistor is in the "on" state when the control signal is low, and in the "off" state when the control signal is high. In any case, when its control signal is asserted (deasserted), the switch is in the "on" ("off") state. In the present disclosure, when a switch is incorporated, no specific embodiment is specified, and the circuit design can choose to use any embodiment known in the prior art, at the discretion of the circuit designer.

[0062] A circuit is a collection of transistors, resistors, and / or other circuit devices connected in a specific way to perform a specific function. A network is a circuit or a collection of circuits.

[0063] like Figure 1As described in the flowchart 100 shown, according to an embodiment of the present disclosure, a working cycle detection method includes the following steps: (step 110) receiving a clock that periodically alternates between an even cycle and an odd cycle; (step 120) using a current source to output a first current; (step 130) when the clock is in a first state of an even cycle, directing the first current to the first capacitor and promoting charge sharing between the second capacitor and the fourth capacitor; (step 140) when the clock is in a second state of an even cycle, directing the first current to the second capacitor and promoting charge sharing between the first capacitor and the third capacitor; (step 150) when the clock is in the first state of an odd cycle, discharging the first capacitor and promoting charge sharing between the second capacitor and the fourth capacitor; (step 160) when the clock is in the second state of an odd cycle, discharging the second capacitor and promoting charge sharing between the first capacitor and the third capacitor.

[0064] Figure 2A A schematic diagram of a duty cycle detector (DCD) 200 is shown. Figure 1 The DCD 200 includes a divide-by-2 circuit 240 configured to receive a clock CK and a signal CB (which is the logic inversion of the clock CK) and output an even cycle signal EC and an odd cycle signal OC, wherein the odd cycle signal OC is the logic inversion of the even cycle signal EC; a current source 210, receiving a power supply voltage V DD , and configured to output a first current I1; a current steering network CSN, configured to guide the first current I1 to a second current I2 when both the even-numbered cycle signal EC and the clock CK are high, guide the first current I1 to a third current I3 when both the even-numbered cycle signal EC and the signal CB are high, and guide the first current I1 to ground (as a ground current I3) when the odd-numbered cycle signal OC is high. g ); a first capacitor C1, configured to receive a second current I2; a second capacitor C2, configured to receive a third current I3; a third capacitor C3, configured to share charge with the first capacitor C1 through a first charge sharing switch CSS1 controlled by a signal CB; a fourth capacitor C4, configured to share charge with the second capacitor C2 through a second charge sharing switch CSS2 controlled by a clock CK; a first discharge network DN1, configured to discharge the first capacitor C1 when the odd-numbered cycle signal OC and the clock CK are both high; and a second discharge network DN2, configured to discharge the second capacitor C2 when the odd-numbered cycle signal OC and the signal CB are both high.

[0065] Figure 2BThe timing diagram of DCD 200 is shown. Clock CK is a clock that switches between high and low states periodically. One cycle of clock CK starts from a low-to-high transition and ends before the next low-to-high transition. As shown in the figure, clock CK periodically alternates between even cycles and odd cycles. One cycle of clock CK is T. The pulse width of clock CK is τ, which is equal to the period T multiplied by the working cycle of clock CK. Signal CB is the logical inversion of clock CK, so the pulse width of signal CB is T-τ. Even cycle signal EC is a clock divided by 2, switching high and low states at the rising edge of clock CK. Odd cycle signal OC is the logical inversion of even cycle signal EC. When even cycle signal EC is high (odd cycle signal OC is low), it indicates that clock CK is in an even cycle; when odd cycle signal OC is high (even cycle signal EC is low), it indicates that clock CK is in an odd cycle. DCD 200 operates in a four-stage manner according to the periodicity of clock CK and even cycle signal EC. In the first stage (φ l ), when the clock CK and the even-cycle signal EC are both high, the first current I1 is directed to the first capacitor C1, and the first capacitor C1 is effectively charged via the current steering network CSN to establish a first voltage V1, while the second capacitor C2 shares charge with the fourth capacitor C4 via the second charge sharing switch CSS2; at the end of the first stage, the total charge stored on the first capacitor C1 is I1τ, and the first voltage V1 is equal to I1τ / C1.

[0066] In the second stage (φ2), when the signal CB and the even-numbered cycle signal EC are both high, the first current I1 is directed to the second capacitor C2, and the second capacitor C2 is effectively charged via the current-directing network CSN to establish the second voltage V2, while the first capacitor C1 shares the charge with the third capacitor C3 via the first charge-sharing switch CSS1; at the end of the second stage, the total charge stored on the second capacitor C2 is I1(T-τ), and the second voltage V2 is equal to I1(T-τ) / C2. In the third stage (φ3), when the clock CK and the odd-numbered cycle signal OC are both high, the first capacitor C1 is discharged, and the second capacitor C2 shares the charge with the fourth capacitor C4. In the fourth stage (φ4), when the signal CB and the odd-numbered cycle signal OC are both high, the second capacitor C2 is discharged, and the first capacitor C1 shares the charge with the third capacitor C3. In this way, in each cycle of the four stages, the first current I1 alternately charges the first capacitor C1 and the second capacitor C2, and its charge is then shared with the third capacitor C3 and the fourth capacitor C4, respectively, and then discharged. Finally, due to the charge sharing between the first capacitor C1 and the third capacitor C3, the third voltage V3 on the third capacitor C3 will be I1τ / (C1+C3), or equivalent to I1(T / 2+(τ-T / 2)) / (C1+C3); due to the charge sharing between the second capacitor C2 and the fourth capacitor C4, the fourth voltage V4 on the fourth capacitor C4 will be I1(T-τ) / (C2+C4), or equivalent to I1(T / 2-(τ-T / 2)) / (C2+C4). The first capacitor C1 and the second capacitor C2 have the same capacitance value, and the third capacitor C3 and the fourth capacitor C4 also have the same capacitance value. The difference between the third voltage V3 and the fourth voltage V4 is proportional to (τ-T / 2), and is therefore proportional to the duty cycle error of the clock CK (which is relative to a 50% duty cycle). Therefore, the duty cycle detection function is implemented.

[0067] The divide-by-2 circuit 240 can be implemented using a data flip flop (DFF) triggered by the clock CK (and the signal CB) and configured as a negative feedback structure so that the even-cycle signal EC (and the odd-cycle signal OC) switch states at the rising edge of the clock CK (which is also the falling edge of the signal CB); this is understandable to those skilled in the art and is therefore not described in detail herein.

[0068] The current steering network CSN includes four switches 221, 222, 223 and 224 controlled by the odd cycle signal OC, the even cycle signal EC, the clock CK and the signal CB. During the even cycle (when the even cycle signal EC is high), the first current I1 is steered as the charge pump current I via the switch 222. cp , and during the odd cycle (when the odd cycle signal OC is high), the ground current I is guided to the ground via the switch 221.g During even cycles, when the clock CK is high, the charge pump current I cp The current is further directed to the second current I2 via the switch 223 , and is directed to the third current I3 via the switch 224 when the signal CB is high.

[0069] In some alternative embodiments, switches 222, 223, and 224 are removed and replaced by two switches 251 and 252 controlled by a first phase signal φ1 and a second phase signal φ2, which are respectively generated by two AND gates 253 and 254. Among them, AND gate 253 receives the even cycle signal EC and the clock CK and outputs the first phase signal φ1, while AND gate 254 receives the even cycle signal EC and the signal CB and outputs the second phase signal φ2. Functionally, this alternative embodiment achieves the same function; this is understandable to those skilled in the art, so it is not explained in detail here.

[0070] The first discharge network DN1 includes two switches 233 and 234 connected in series, which are controlled by the odd-numbered cycle signal OC and the clock CK, respectively. When the odd-numbered cycle signal OC and the clock CK are both high, these switches are configured to provide a discharge path for the first capacitor C1. The second discharge network DN2 includes two switches 235 and 236 connected in series, which are controlled by the odd-numbered cycle signal OC and the signal CB, respectively. When the odd-numbered cycle signal OC and the signal CB are both high, these switches are configured to provide a discharge path for the second capacitor C2.

[0071] In some alternative embodiments, switches 233 and 234 are removed and replaced by switch 241 controlled by third phase signal φ3, which is generated by AND gate 242 according to odd cycle signal OC and clock CK. Similarly, switches 235 and 236 are removed and replaced by switch 243 controlled by fourth phase signal φ4, which is generated by AND gate 244 according to odd cycle signal OC and signal CB. Functionally, this alternative embodiment achieves the same function; this is understandable to those skilled in the art and is therefore not explained in detail herein.

[0072] Due to the alternating current guidance, the noise of the first current I1 will be stored in the first capacitor C1 and the second capacitor C2, and then shared with the third capacitor C3 and the fourth capacitor C4 respectively, so as to appear as common mode noise, and the noise can be suppressed when the output is defined by the difference between the third voltage V3 and the fourth voltage V4. In this way, the goal of low-noise duty cycle detection can be achieved. In addition, only two cycles of the clock CK are required to obtain the difference between the third voltage V3 and the fourth voltage V4 (which can represent the duty cycle error of the clock CK). Therefore, the goal of fast duty cycle detection can be achieved.

[0073] In addition, the charge sharing between the first capacitor C1 and the third capacitor C3 forms a discrete time (switched capacitor) low pass filter, and can further filter out the noise of the first current I1. The same is true for the second capacitor C2 and the fourth capacitor C4. Therefore, by selecting a smaller cut-off frequency of the discrete time low pass filter, the noise of the first current I1 can be further suppressed, which is achieved by using a smaller first ratio and a smaller second ratio (wherein the first ratio is the ratio between the first capacitor C1 and the third capacitor C3, and the second ratio is the ratio between the second capacitor C2 and the fourth capacitor C4), but at the cost of a slower duty cycle detection speed.

[0074] In some embodiments, DCD 200 is integrated and manufactured using CMOS process technology on a silicon substrate. Current source 210 can be implemented by a PMOS transistor controlled by a bias voltage; this is understood by those skilled in the art and is not explained in detail here. The switch can be implemented by an NMOS transistor, a PMOS transistor, or a combination of the two; this is also understood by those skilled in the art and is not explained in detail here.

[0075] like Figure 3 As shown, according to another embodiment of the present disclosure, the flowchart 300 includes the following steps: (step 310) receiving a clock that periodically alternates between even cycles and odd cycles; (step 320) using a current source to output a first current; (step 330) establishing a four-stage continuous and cyclic timing scheme including a first stage, a second stage, a third stage and a fourth stage according to the state of the clock and the state of the periodic signal that switches periodically and alternately; (step 340) in the first stage, directing the first current to the first capacitor and promoting charge sharing between the second capacitor and the fourth capacitor; (step 350) in the second stage, directing the first current to the second capacitor and promoting charge sharing between the first capacitor and the third capacitor; (step 360) in the third stage, discharging the first capacitor and promoting charge sharing between the second capacitor and the fourth capacitor; (step 370) in the fourth stage, discharging the second capacitor and promoting charge sharing between the first capacitor and the third capacitor.

[0076] Although the embodiments of the present disclosure are described above, the embodiments are not intended to limit the present disclosure. Technicians in this technical field may make changes to the technical features of the present disclosure based on the explicit or implicit contents of the present disclosure. All these changes may fall within the scope of patent protection sought by the present disclosure. In other words, the scope of patent protection of the present disclosure shall be subject to the scope of the patent application defined in this specification.

Claims

1. A working cycle detection method, comprising: receiving a clock that periodically alternates between an even-numbered cycle and an odd-numbered cycle; Using a current source to output a first current; When the clock is in a first state of the even cycle, the first current is directed to a first capacitor, and charges are shared between a second capacitor and a fourth capacitor; When the clock is in a second state of the even cycle, directing the first current to the second capacitor and promoting charge sharing between the first capacitor and a third capacitor; When the clock is in the first state of the odd cycle, the first capacitor is discharged, and charge sharing between the second capacitor and the fourth capacitor is promoted; and When the clock is in the second state of the odd cycle, the second capacitor is discharged, and charge sharing between the first capacitor and the third capacitor is promoted.

2. The duty cycle detection method according to claim 1, further comprising: A periodic signal is generated to switch when the periodic state of the clock changes, so that the clock is in the even cycle when the periodic signal is in the first state, and is in the odd cycle when the periodic signal is in the second state.

3. The duty cycle detection method as claimed in claim 2, wherein causing the charge sharing between the first capacitor and the third capacitor comprises: The first capacitor is connected to the third capacitor via a first charge sharing switch, wherein the first charge sharing switch is controlled by a logic inversion of the clock.

4. The duty cycle detection method as claimed in claim 3, wherein causing the charge sharing between the second capacitor and the fourth capacitor comprises: The second capacitor is connected to the fourth capacitor via a second charge sharing switch, wherein the second charge sharing switch is controlled by the clock.

5. The duty cycle detection method as claimed in claim 2, wherein directing the first current to the first capacitor comprises: The first current is guided to the first capacitor via a first switch network, wherein the first switch network is turned on when both the periodic signal and the clock are in the first state.

6. The duty cycle detection method as claimed in claim 5, wherein directing the first current to the second capacitor comprises: The first current is guided to the second capacitor via a second switch network, wherein the second switch network is turned on when the periodic signal is in the first state and the clock is in the second state.

7. The duty cycle detection method as claimed in claim 2, wherein discharging the first capacitor comprises: The first capacitor is connected to a ground node via a first switch network, wherein the first switch network is turned on when the clock is in the first state and the periodic signal is in the second state.

8. The duty cycle detection method as claimed in claim 7, wherein discharging the first capacitor comprises: The second capacitor is connected to the ground node via a second switch network, wherein the second switch network is turned on when both the clock and the periodic signal are in the second state.

9. The working cycle detection method as described in claim 8, wherein the first switch network includes two first switches connected in series, and the two first switches are respectively controlled by a logic inversion of the clock and the periodic signal, and the second switch network includes two second switches connected in series, and the two second switches are respectively controlled by a logic inversion of the clock and the logic inversion of the periodic signal.

10. A duty cycle detector comprising: a current steering network for steering a first current into a second current to charge a first capacitor when a clock is in a first state of an even cycle, and steering the first current into a third current to charge a second capacitor when the clock is in a second state of the even cycle; a first charge sharing switch, used for promoting charge sharing between the first capacitor and a third capacitor when the clock is in the second state; a second charge sharing switch, used for promoting charge sharing between the second capacitor and a fourth capacitor when the clock is in the first state; a first discharge network, used for discharging the first capacitor when the clock is in the first state of an odd cycle; as well as A second discharge network is used to discharge the second capacitor when the clock is in the second state of the odd cycle.

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