Method and device for constructing electro-thermal migration effect circuit model of interconnection line

Abstract

The embodiment of the invention relates to the technical field of packaging interconnection reliability analysis, and provides a construction method and device for an electro-thermal migration effect circuit model of an interconnection line, and the method comprises the steps: converting an electro-thermal migration effect into a circuit parameter change based on a Korhonen control equation and boundary conditions, capturing the significant influence of temperature and temperature gradient on atom migration, and carrying out the analysis of the reliability of the interconnection line. According to the method, an equivalent circuit model of the interconnection line under the electro-thermal migration effect is deduced, a circuit matrix equation corresponding to the equivalent circuit model is determined by using an improved node analysis method, dimension reduction processing is performed on the circuit matrix equation, and an electro-thermal migration effect circuit model of the interconnection line is obtained, so that the system dimension is effectively compressed; therefore, the calculation complexity is effectively reduced, the solving efficiency is remarkably improved, the stress evolution in the complex multi-branch interconnection line can be rapidly analyzed, meanwhile, the cavity length evolution is dynamically simulated, and the precision requirement and the efficiency requirement are both considered.

Description

Technical Field

[0001] The present disclosure relates to the technical field of package interconnect reliability analysis, and in particular to a method and device for constructing an electro-thermal migration effect circuit model of an interconnect line. Background Art

[0002] Aging and failure problems caused by electromigration (EM) have become one of the main issues that need to be urgently addressed in the reliability of integrated packaging in advanced nanotechnology. Electromigration refers to the process in which the momentum of electrons in the interconnects is transferred to metal atoms under high current density, causing these metal atoms to gradually migrate from their lattice positions. In addition, the thermal migration (TM) effect also has a significant driving effect on atomic migration. Among them, thermal migration refers to the atomic migration phenomenon caused by temperature gradient, and atoms have a tendency to move from high temperature to low temperature. As technology develops towards miniaturization and three-dimensional stacking integration, the impact of TM will become more prominent, but most existing technologies do not fully consider the impact of TM on the atomic migration process.

[0003] At present, the physics-based EM analysis method is mainly carried out by solving partial differential equations (PDEs) caused by stress diffusion controlled by the Korhonen governing equation. The Korhonen governing equation describes the evolution of stress inside the wire over time and is an important theoretical basis for studying electromigration failure. This method usually relies on introducing boundary conditions and initial conditions at the nodes of the interconnect structure to accurately track the stress changes in the multi-branch interconnect tree. However, due to the complexity of the multi-branch interconnect structure and the diversity of boundary conditions, the boundary conditions and initial conditions that need to be processed in the solution process are relatively complex, which not only increases the difficulty of calculation, but may also lead to reduced solution efficiency and accuracy, which brings significant challenges to practical applications.

[0004] In addition, acceleration calculation methods such as model reduction and macromodeling have become relatively mature, such as the Krylov subspace method and the singular value decomposition method. These methods can significantly improve the computational efficiency, especially in large-scale complex systems. However, the application of these technologies in electro-thermal migration problems is still relatively limited, and their potential has not yet been fully explored. Summary of the invention

[0005] The present disclosure aims to solve at least one of the problems existing in the prior art and provides a method and device for constructing an electro-thermal migration effect circuit model of an interconnect line.

[0006] In one aspect of the present disclosure, a method for constructing an electro-thermal migration effect circuit model of an interconnect is provided, the method comprising: Based on the Korhonen governing equations and boundary conditions, the equivalent circuit model of the interconnect under the electro-thermal migration effect is derived; Determine the circuit matrix equation corresponding to the equivalent circuit model by using an improved node analysis method; The circuit matrix equation is subjected to dimensionality reduction processing to obtain an electro-thermal migration effect circuit model of the interconnection line.

[0007] Optionally, the equivalent circuit model of the interconnect under the electro-thermal migration effect is derived based on the Korhonen control equation and boundary conditions, including: Dividing the interconnection line into a plurality of line segment units, and considering that each of the line segment units is consistent in terms of current density, temperature, and temperature gradient; The physical meanings of voltage, current, resistance, and capacitance are mapped to the relationship between voltage and diffusion flux of the electro-thermal migration effect, and the resistance, capacitance, and current in the equivalent circuit model corresponding to the line segment unit are expressed as: ; ; ; Wherein, i represents the number of the line segment unit; represents the resistance in the equivalent circuit model corresponding to the i-th line segment unit; represents the capacitance in the equivalent circuit model corresponding to the i-th line segment unit; represents the current in the equivalent circuit model corresponding to the i-th line segment unit; represents the Boltzmann constant; represents the temperature in the equivalent circuit model corresponding to the i-th line segment unit; represents the length in the equivalent circuit model corresponding to the i-th line segment unit; represents the diffusion coefficient in the equivalent circuit model corresponding to the i-th line segment unit; represents the cross-sectional area in the equivalent circuit model corresponding to the i-th line segment unit; represents the first scale factor; represents the bulk modulus; represents the atomic volume; represents the second scale factor; Indicates the amount of electron charge; represents the effective valence charge; represents resistivity; represents the current density in the equivalent circuit model corresponding to the i-th line segment unit; represents atomic transfer heat; Represents displacement in space.

[0008] Optionally, the determining the circuit matrix equation corresponding to the equivalent circuit model by using an improved node analysis method includes: Using the improved node analysis method, the circuit matrix equation of the void nucleation stage is expressed as: ; in, They represent the capacitance matrix, conductance matrix, and current source matrix in the void nucleation stage, respectively. represents a vector consisting of voltages of n nodes obtained by dividing the interconnection line into a number of line segment units, express The rate of change of Based on the improved node analysis method, it is assumed that the interconnection line A void is formed at the hole, and the circuit matrix equation in the void growth stage is expressed as; ; ; in, Indicates the location of the generated hole; They represent the capacitance matrix, conductance matrix, and current source matrix in the void nucleation stage respectively; represents the capacitance indicating the predicted void length and , represents the third scale factor; represents the conductance used to indicate the void boundary condition and ; Indicates the initial length of the cavity when it is generated; They represent the node voltage and current source of the line segment unit where the void is located.

[0009] Optionally, the performing dimensionality reduction processing on the circuit matrix equation to obtain the electro-thermal migration effect circuit model of the interconnect line includes: According to the circuit matrix equation, a transient voltage node equation and a stress conversion equation are constructed; wherein the transient voltage node equation is expressed as: ; The stress conversion equation is expressed as: ; in, The initial voltage value ; Respectively represent the initial voltage values ​​corresponding to the 1st, 2nd, …, nth nodes; Respectively represent the capacitance matrix, conductance matrix, and current source matrix of the circuit matrix equation; in the void nucleation stage, The values ​​of are ; In the cavity growth stage, The values ​​of are ; express Stress at time; transposed matrix of matrix L for A matrix of order , which means that r samples are selected from n nodes for the measurement of stress Σ; T represents the transpose of the matrix; Based on the Arnoldi method, when When the initial voltage value is not 0, the macro modeling of the system is performed, and the Laplace transform of the transient voltage node equation is performed to obtain the stress vector in the complex frequency domain. : ; in, represents a complex variable; represents the current in the equivalent circuit model corresponding to the nth line segment unit; A represents the first intermediate variable and ; R represents the second intermediate variable and ; Corresponding stress vector Perform Taylor expansion, calculate the coefficient matrix of the expansion, and use QR decomposition to determine the basis vectors, and construct the space transformation matrix X based on the basis vectors: ; Among them, q represents the order after dimensionality reduction; Use the spatial transformation matrix X to Performing order reduction, we get: ; ; ; ; in, Respectively represent the reduced ; use The transient voltage node equation is reduced in dimension to obtain the electro-thermal migration effect circuit model of the interconnect: ; in, express The rate of change.

[0010] Optionally, the construction method further includes: verifying the electro-thermal migration effect circuit model.

[0011] Optionally, the verifying the electro-thermal migration effect circuit model includes: The electro-thermal migration effect circuit model is solved by using a SPICE solver or an Euler iteration method to reconstruct the distribution of the high-dimensional stress field, and the distribution of the high-dimensional stress field is expressed as: , and obtain the corresponding model simulation results; among them, express The corresponding high-dimensional stress field and ; Using the finite element method to simulate the electro-thermal migration effect of the interconnection line to obtain corresponding finite element simulation results; The model simulation results are compared with the finite element simulation results to obtain verification results of the electro-thermal migration effect circuit model.

[0012] Another aspect of the present disclosure provides a device for constructing an electro-thermal migration effect circuit model of an interconnect line, the device comprising: A derivation module is used to derive the equivalent circuit model of the interconnect under the electro-thermal migration effect based on the Korhonen control equation and boundary conditions; A determination module, used to determine the circuit matrix equation corresponding to the equivalent circuit model by using an improved node analysis method; The dimension reduction module is used to perform dimension reduction processing on the circuit matrix equation to obtain the electro-thermal migration effect circuit model of the interconnection line.

[0013] Optionally, the construction device further comprises: A verification module is used to verify the electro-thermal migration effect circuit model.

[0014] Another aspect of the present disclosure provides an electronic device, including: at least one processor; and, a memory communicatively connected to at least one processor; wherein, The memory stores instructions that can be executed by at least one processor, and the instructions are executed by at least one processor so that the at least one processor can execute the method for constructing the circuit model of the electro-thermal migration effect of the interconnection line described above.

[0015] Another aspect of the present disclosure provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the method for constructing the electro-thermal migration effect circuit model of the interconnection line described above.

[0016] Another aspect of the present disclosure provides a computer program product, including a computer program, which, when executed by a processor, implements the method for constructing the electro-thermal migration effect circuit model of the interconnection line described above.

[0017] Compared with the prior art, the present invention converts the electro-thermal migration effect into circuit parameter changes based on the Korhonen control equation and boundary conditions, captures the significant influence of temperature and temperature gradient on atomic migration, derives the equivalent circuit model of the interconnect under the electro-thermal migration effect, uses the improved node analysis method to determine the circuit matrix equation corresponding to the equivalent circuit model, and performs dimensionality reduction processing on the circuit matrix equation to obtain the electro-thermal migration effect circuit model of the interconnect, effectively compresses the system dimension, thereby effectively reducing the computational complexity, and significantly improving the solution efficiency, so that it can quickly analyze the stress evolution in complex multi-branch interconnects, and dynamically simulate the evolution of void length, taking into account both accuracy requirements and efficiency requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0019] Figure 1 A flow chart of a method for constructing an electro-thermal migration effect circuit model of an interconnect provided in one embodiment of the present disclosure; Figure 2 A schematic diagram of an equivalent circuit model of an i-th line segment unit provided in another embodiment of the present disclosure; Figure 3 A schematic diagram of an equivalent circuit model of a void nucleation stage of a three-segment interconnect structure provided by another embodiment of the present disclosure; Figure 4 A schematic diagram of an equivalent circuit model of a two-segment interconnect structure in a void growth stage provided by another embodiment of the present disclosure; Figure 5 The matrix obtained by solving another embodiment of the present disclosure is Schematic diagram of the first 24 largest eigenvalues; Figure 6 A schematic diagram showing a comparison between a model simulation result and a finite element simulation result of a section of interconnect line at a void nucleation stage provided by another embodiment of the present disclosure; Figure 7 A schematic diagram showing a comparison between a model simulation result and a finite element simulation result of a section of interconnect line in a void growth stage provided by another embodiment of the present disclosure; Figure 8 A schematic structural diagram of a device for constructing an electro-thermal migration effect circuit model of an interconnect provided by another embodiment of the present disclosure; Fig. 9 A schematic structural diagram of an electronic device provided in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. However, it can be understood by those skilled in the art that in each embodiment of the present disclosure, many technical details are proposed in order to enable readers to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed for protection in the present disclosure can also be implemented. The division of the following embodiments is for the convenience of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments can be combined and referenced with each other without contradiction.

[0021] One embodiment of the present disclosure relates to a method for constructing an electro-thermal migration effect circuit model of an interconnect, the process of which is as follows: Figure 1 As shown, including: Step S110, deriving an equivalent circuit model of the interconnect under the electro-thermal migration effect based on the Korhonen control equation and boundary conditions.

[0022] Specifically, the temperature of the thermal migration effect is determined by the Joule heat generated by the interconnect under a certain current density. Step S110 can determine the current density, temperature and temperature gradient of the interconnect element as inputs of the equivalent circuit model to calculate the circuit element value of the equivalent circuit model. In addition, to ensure the consistency of the model unit, multiple scaling factors can be introduced for the conversion of variables.

[0023] Exemplarily, step S110 includes: dividing the interconnect into a plurality of line segment units, and assuming that each line segment unit is consistent in terms of current density, temperature, and temperature gradient. In this case, the control equation of electro-thermal migration is The governing equations of the non-inductive and non-leakage transmission line Therefore, the physical meanings of voltage, current, resistance, and capacitance can be mapped to the relationship between voltage and diffusion flux of the electro-thermal migration effect, and the resistance and capacitance in the equivalent circuit model corresponding to the line segment unit can be expressed as: ; .

[0024] A current source is introduced to describe the flux flow between the starting and ending points of the line segment unit. According to the boundary conditions, the current of the i-th line segment unit can be expressed as: .

[0025] Wherein, i represents the number of the line segment unit; represents the resistance in the equivalent circuit model corresponding to the i-th line segment unit; represents the capacitance in the equivalent circuit model corresponding to the i-th line segment unit; represents the current in the equivalent circuit model corresponding to the i-th line segment unit; represents the Boltzmann constant; represents the temperature in the equivalent circuit model corresponding to the i-th line segment unit; represents the length in the equivalent circuit model corresponding to the i-th line segment unit; represents the diffusion coefficient in the equivalent circuit model corresponding to the i-th line segment unit; represents the cross-sectional area in the equivalent circuit model corresponding to the i-th line segment unit; represents the first scale factor; represents the bulk modulus; represents the atomic volume; represents the second scale factor; Indicates the amount of electron charge; represents the effective valence charge number; represents resistivity; represents the current density in the equivalent circuit model corresponding to the i-th line segment unit; represents atomic transfer heat; Represents displacement in space.

[0026] Based on the above content, the equivalent circuit model of the i-th line segment unit is as follows Figure 2 As shown, and Respectively represent the end and starting end of the i-th line segment unit.

[0027] During the void growth phase, assuming that the interconnect is at position A void is generated at the location. Based on the boundary conditions of the void location and the prediction method of the void length, the conductivity can be defined. and capacitor , which are used to describe the boundary conditions of the cavity and predict its length change. Indicates the location of the generated hole. Indicates the initial length of the hole when it is generated. Represents the third scale factor.

[0028] Step S120: using an improved node analysis method, determine a circuit matrix equation corresponding to the equivalent circuit model.

[0029] Specifically, based on the equivalent circuit model of each line segment unit obtained in step S110, the equivalent circuit models of the interconnects at different stages under the action of electro-thermal migration are written in the form of a matrix using an improved node analysis method.

[0030] For example, Figure 3Taking the three-segment interconnect structure as an example, the equivalent circuit model of its void nucleation stage is shown. Figure 3 (a) in the figure shows a three-segment interconnection line structure and four line segment units at the connection. Figure 3 (b) in the formula indicates Figure 3 (a) shows the equivalent circuit model of four line segment units in the void nucleation stage. Figure 4 Taking the two-segment interconnect structure as an example, the equivalent circuit model of the void growth stage is shown. Figure 4 (a) in the figure shows a two-segment interconnection line structure and two line segment units on its right. Figure 4 (b) in the formula indicates Figure 4 (a) shows the equivalent circuit model of two line segment units in the void growth stage. Figure 3 and Figure 4 On this basis, the circuit matrix equations corresponding to the equivalent circuit models of the void nucleation stage and the void growth stage can be determined respectively.

[0031] Exemplarily, step S120 includes: using an improved node analysis method, expressing the circuit matrix equation in the void nucleation stage as: .in, They represent the capacitance matrix, conductance matrix, and current source matrix in the void nucleation stage respectively. A vector representing the voltages of n nodes obtained by dividing the interconnect into several line segment units. express The rate of change.

[0032] Based on the improved node analysis method, it is assumed that the interconnection line A void is formed at the hole, and the circuit matrix equation in the void growth stage is expressed as; ; .in, Indicates the location of the generated hole. They represent the capacitance matrix, conductance matrix, and current source matrix in the void nucleation stage respectively. represents the capacitance indicating the predicted void length and , Represents the third scale factor. represents the conductance used to indicate the void boundary condition and . Indicates the initial length of the hole when it is generated. They represent the node voltage and current source of the line segment unit where the void is located.

[0033] Step S130 , performing dimension reduction processing on the circuit matrix equation to obtain an electro-thermal migration effect circuit model of the interconnection line.

[0034] Specifically, step S130 can be based on the circuit matrix equation obtained in step S120, and further derive an improved PRIMA method by applying the Arnoldi process to reduce the dimensionality of the circuit system. This can effectively reduce the dimension of the system while retaining the main dynamic characteristics of the system. On this basis, the improved PRIMA method uses orthogonal decomposition technology to extract the most representative low-dimensional subspace from the original high-dimensional circuit matrix, thereby generating a low-dimensional macro model as the circuit model of the electro-thermal migration effect of the interconnect. The low-dimensional macro model can significantly reduce the computational complexity while maintaining sufficient accuracy, which is convenient for quickly solving and analyzing complex electro-thermal migration problems. This reduction method can greatly improve the simulation efficiency, especially when dealing with large-scale multi-branch interconnect structures, it has significant advantages.

[0035] Exemplarily, step S130 includes: constructing transient voltage node equations and stress conversion equations according to the circuit matrix equation.

[0036] Among them, the transient voltage node equation is expressed as: The stress conversion equation is expressed as: .

[0037] in, The initial voltage value . They represent the initial voltage values ​​corresponding to the 1st, 2nd,…,nth nodes respectively. Respectively represent the capacitance matrix, conductance matrix, and current source matrix of the circuit matrix equation. In the void nucleation stage, The values ​​of are During the cavity growth phase, The values ​​of are . express The stress at the moment. The transposed matrix of matrix L for The matrix of order , represents the selection of r samples from n nodes for the measurement of stress Σ. T represents the transpose of the matrix.

[0038] Based on the Arnoldi method, when When the initial voltage value is not 0, the macro modeling of the system is performed, and the Laplace transform of the transient voltage node equation is performed to obtain the stress vector in the complex frequency domain. : .

[0039] in, Represents a complex variable. represents the current in the equivalent circuit model corresponding to the nth line segment unit. A represents the first intermediate variable and . R represents the second intermediate variable and .

[0040] Corresponding stress vector Perform Taylor expansion, calculate the coefficient matrix of the expansion, and use QR decomposition to determine the basis vectors, and construct the space transformation matrix X based on the basis vectors: ; Among them, q represents the order after dimensionality reduction. The value of q can be obtained by calculating the matrix For example, the number of eigenvalues ​​whose cumulative energy exceeds a preset value, such as 97%, can be selected as the order q after dimensionality reduction. This setting can significantly reduce the computational complexity while maintaining sufficient accuracy. For example, Figure 5 The matrix obtained by solving The first 24 largest eigenvalues ​​of , and the order after dimensionality reduction can be determined by the proportion of eigenvalues.

[0041] The solution process of the space transformation matrix X is: .

[0042] Use the spatial transformation matrix X to Perform rank reduction to obtain a low-dimensional matrix: ; ; ; .

[0043] in, Respectively represent the reduced .

[0044] use The transient voltage node equation is reduced in dimension to obtain the circuit model of the electro-thermal migration effect of the interconnect: .in, express The rate of change.

[0045] Exemplarily, the method for constructing the electro-thermal migration effect circuit model of the interconnect line further includes: verifying the electro-thermal migration effect circuit model.

[0046] Specifically, after obtaining the electro-thermal migration effect circuit model of the interconnect, the electro-thermal migration effect circuit model can be solved by a SPICE solver or Euler iteration, and the high-dimensional stress field distribution can be reconstructed to verify the accuracy and effectiveness of the electro-thermal migration effect circuit model.

[0047] Exemplarily, verifying the electro-thermal migration effect circuit model includes: solving the electro-thermal migration effect circuit model using a SPICE solver or an Euler iteration method, reconstructing the distribution of the high-dimensional stress field, and expressing the distribution of the high-dimensional stress field as: , and get the corresponding model simulation results. Among them, express The corresponding high-dimensional stress field and The finite element method (FEM) is used to simulate the electro-thermal migration effect of the interconnection line and obtain the corresponding finite element simulation results. The model simulation results are compared with the finite element simulation results to obtain the verification results of the electro-thermal migration effect circuit model.

[0048] For example, Figure 6 The figure shows the comparison between the model simulation results and the finite element simulation results of a section of interconnect line during the void nucleation stage. Figure 6 (a) is the stress distribution diagram at different time points. Figure 6 (b) is a comparison chart of the relative errors between the model simulation results and the finite element simulation results at different time points. Figure 7 The figure shows the comparison between the model simulation results and the finite element simulation results of a section of interconnect line during the void growth stage. Figure 7 (a) shows the change in the length of the void when there is a void at the beginning (without going through the void nucleation stage). Figure 7 (b) shows the change in void length in the initial void-free state (after the void nucleation stage and then into the void growth stage). Figure 6 and Figure 7 In, COMSOL is used to refer to the finite element simulation results obtained using COMSOL software, and SPICE is used to refer to the model simulation results obtained using the SPICE solver. The following Table 1 shows the simulation performance comparison between the model simulation results of multi-segment interconnects and the finite element simulation results. Among them, the number of segments and the number of nodes respectively represent the number of segments of the multi-segment interconnects and the number of nodes obtained by dividing the interconnects into a number of line segment units. q represents the order after dimensionality reduction, that is, the order of the electro-thermal migration effect circuit model of the interconnects. FEM represents the time used for solving using the finite element method. The order reduction, solution, and sum in the time of this method respectively represent the order reduction time, solution time, order reduction time, and solution time sum used for solving the electro-thermal migration effect circuit model of the interconnects constructed using the embodiments of the present disclosure. The acceleration multiple represents the multiple of the task completion speed of solving the electro-thermal migration effect circuit model of the interconnects constructed using the embodiments of the present disclosure relative to the task completion speed of solving using the finite element method. The error represents the relative error between the model simulation result and the finite element simulation result.

[0049] Table 1 Comparison of simulation performance of multi-segment interconnects

[0050] Combination Figure 6 , Figure 7 As can be seen from Table 1, the electro-thermal migration effect circuit model of the interconnect constructed in the embodiment of the present disclosure can effectively reduce the computational complexity, improve the solution efficiency, and has high accuracy, providing a simplified but accurate analysis tool for complex multi-physical field coupling problems, thereby providing support for reliability evaluation and optimization in engineering design.

[0051] Compared with the prior art, the method for constructing the electro-thermal migration effect circuit model of the interconnect provided by the embodiment of the present disclosure converts the electro-thermal migration effect into circuit parameter changes based on the Korhonen control equation and boundary conditions, captures the significant influence of temperature and temperature gradient on atomic migration, derives the equivalent circuit model of the interconnect under the electro-thermal migration effect, uses the improved node analysis method to determine the circuit matrix equation corresponding to the equivalent circuit model, and performs dimensionality reduction processing on the circuit matrix equation to obtain the electro-thermal migration effect circuit model of the interconnect, effectively compresses the system dimension, thereby effectively reducing the computational complexity, significantly improving the solution efficiency, enabling it to quickly analyze the stress evolution in complex multi-branch interconnects, and dynamically simulate the evolution of void length, taking into account both accuracy requirements and efficiency requirements.

[0052] Another embodiment of the present disclosure relates to a device for constructing an electro-thermal migration effect circuit model of an interconnect line, such as Figure 8 As shown, it includes a derivation module 810, a determination module 820, and a dimensionality reduction module 830.

[0053] The derivation module 810 is used to derive an equivalent circuit model of the interconnect under the electro-thermal migration effect based on the Korhonen control equation and boundary conditions.

[0054] The determination module 820 is used to determine the circuit matrix equation corresponding to the equivalent circuit model by using an improved node analysis method.

[0055] The dimension reduction module 830 is used to perform dimension reduction processing on the circuit matrix equation to obtain an electro-thermal migration effect circuit model of the interconnection line.

[0056] Exemplarily, the apparatus for constructing the electro-thermal migration effect circuit model of interconnects further includes a verification module. The verification module is used to verify the electro-thermal migration effect circuit model.

[0057] The specific implementation method of the device for constructing the electro-thermal migration effect circuit model of the interconnect provided in the embodiment of the present disclosure can be referred to the construction method of the electro-thermal migration effect circuit model of the interconnect provided in the embodiment of the present disclosure, which will not be repeated here.

[0058] Compared with the prior art, the device for constructing the circuit model of the electro-thermal migration effect of the interconnect provided by the embodiment of the present disclosure converts the electro-thermal migration effect into a circuit parameter change based on the Korhonen control equation and boundary conditions, captures the significant influence of temperature and temperature gradient on atomic migration, derives the equivalent circuit model of the interconnect under the electro-thermal migration effect, uses the improved node analysis method to determine the circuit matrix equation corresponding to the equivalent circuit model, and performs dimensionality reduction processing on the circuit matrix equation to obtain the circuit model of the electro-thermal migration effect of the interconnect, effectively compresses the system dimension, thereby effectively reducing the computational complexity, and significantly improving the solution efficiency, so that it can quickly analyze the stress evolution in complex multi-branch interconnects, and dynamically simulate the evolution of void length, taking into account both accuracy requirements and efficiency requirements.

[0059] Another embodiment of the present disclosure relates to an electronic device, such as Fig. 9 As shown, including: at least one processor 901; and, A memory 902 is communicatively connected to at least one processor 901; wherein, The memory 902 stores instructions executable by at least one processor 901 , and the instructions are executed by at least one processor 901 so that the at least one processor 901 can execute the method for constructing the electro-thermal migration effect circuit model of the interconnection line described in the above embodiment.

[0060] Among them, the memory and the processor are connected in a bus manner, and the bus may include any number of interconnected buses and bridges, and the bus connects various circuits of one or more processors and memories together. The bus can also connect various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be one element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices on a transmission medium. The data processed by the processor is transmitted on a wireless medium via an antenna, and further, the antenna also receives data and transmits the data to the processor.

[0061] The processor is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory can be used to store data used by the processor when performing operations.

[0062] Another embodiment of the present disclosure relates to a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the method for constructing an electro-thermal migration effect circuit model of an interconnection line described in the above embodiment.

[0063] That is, those skilled in the art can understand that all or part of the steps in the method described in the above embodiments can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium, including a number of instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0064] Another embodiment of the present disclosure relates to a computer program product, including a computer program, which implements the method for constructing the electro-thermal migration effect circuit model of the interconnection line described in the above embodiment when the computer program is executed by a processor.

[0065] Those skilled in the art will appreciate that the above-mentioned embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A method for constructing an electro-thermal migration effect circuit model of an interconnect, characterized in that: The construction method comprises: Based on the Korhonen governing equations and boundary conditions, the equivalent circuit model of the interconnect under the electro-thermal migration effect is derived; Determine the circuit matrix equation corresponding to the equivalent circuit model by using an improved node analysis method; The circuit matrix equation is subjected to dimensionality reduction processing to obtain an electro-thermal migration effect circuit model of the interconnection line.

2. The construction method according to claim 1, characterized in that: Based on the Korhonen control equation and boundary conditions, an equivalent circuit model of the interconnect under the electro-thermal migration effect is derived, including: Dividing the interconnection line into a plurality of line segment units, and considering that each of the line segment units is consistent in terms of current density, temperature, and temperature gradient; The physical meanings of voltage, current, resistance, and capacitance are mapped to the relationship between voltage and diffusion flux of the electro-thermal migration effect, and the resistance, capacitance, and current in the equivalent circuit model corresponding to the line segment unit are expressed as: ； ； ； Wherein, i represents the number of the line segment unit; represents the resistance in the equivalent circuit model corresponding to the i-th line segment unit; represents the capacitance in the equivalent circuit model corresponding to the i-th line segment unit; represents the current in the equivalent circuit model corresponding to the i-th line segment unit; represents the Boltzmann constant; represents the temperature in the equivalent circuit model corresponding to the i-th line segment unit; represents the length in the equivalent circuit model corresponding to the i-th line segment unit; represents the diffusion coefficient in the equivalent circuit model corresponding to the i-th line segment unit; represents the cross-sectional area in the equivalent circuit model corresponding to the i-th line segment unit; represents the first scale factor; represents the bulk modulus; represents the atomic volume; represents the second scale factor; Indicates the amount of electrons; represents the effective valence charge number; represents resistivity; represents the current density in the equivalent circuit model corresponding to the i-th line segment unit; represents the heat transferred by atoms; Represents displacement in space.

3. The construction method according to claim 2, characterized in that: The method of using the improved node analysis method to determine the circuit matrix equation corresponding to the equivalent circuit model includes: Using the improved node analysis method, the circuit matrix equation of the void nucleation stage is expressed as: ； in, They represent the capacitance matrix, conductance matrix, and current source matrix in the void nucleation stage, respectively. represents a vector consisting of voltages of n nodes obtained by dividing the interconnection line into a number of line segment units, express The rate of change of Based on the improved node analysis method, it is assumed that the interconnection line A void is formed at the hole, and the circuit matrix equation in the void growth stage is expressed as; ； ； in, Indicates the location of the generated hole; They represent the capacitance matrix, conductance matrix, and current source matrix in the void nucleation stage respectively; represents the capacitance used to indicate the predicted void length and , represents the third scale factor; represents the conductance used to indicate the void boundary condition and ; Indicates the initial length of the cavity when it is generated; They represent the node voltage and current source of the line segment unit where the void is located.

4. The construction method according to claim 3, characterized in that: The circuit matrix equation is subjected to dimensionality reduction processing to obtain the electro-thermal migration effect circuit model of the interconnection line, including: According to the circuit matrix equation, a transient voltage node equation and a stress conversion equation are constructed; wherein the transient voltage node equation is expressed as: ; The stress conversion equation is expressed as: ; in, The initial voltage value ; Respectively represent the initial voltage values ​​corresponding to the 1st, 2nd, …, nth nodes; Respectively represent the capacitance matrix, conductance matrix, and current source matrix of the circuit matrix equation; in the void nucleation stage, The values ​​of are ; In the cavity growth stage, The values ​​of are ; express Stress at time; transposed matrix of matrix L for A matrix of order , which means that r samples are selected from n nodes for the measurement of stress Σ; T represents the transpose of the matrix; Based on the Arnoldi method, when When the initial voltage value is not 0, the macro modeling of the system is performed, and the Laplace transform of the transient voltage node equation is performed to obtain the stress vector in the complex frequency domain. : ； in, represents a complex variable; represents the current in the equivalent circuit model corresponding to the nth line segment unit; A represents the first intermediate variable and ; R represents the second intermediate variable and ; Corresponding stress vector Perform Taylor expansion, calculate the coefficient matrix of the expansion, and use QR decomposition to determine the basis vectors, and construct the space transformation matrix X based on the basis vectors: ； Among them, q represents the order after dimensionality reduction; Use the spatial transformation matrix X to Performing order reduction, we get: ； ； ； ； in, Respectively represent the reduced ; use The transient voltage node equation is reduced in dimension to obtain the electro-thermal migration effect circuit model of the interconnect: ； in, express The rate of change.

5. The construction method according to claim 4, characterized in that: The construction method further includes: verifying the electro-thermal migration effect circuit model.

6. The construction method according to claim 5, characterized in that: The verifying of the electro-thermal migration effect circuit model includes: The electro-thermal migration effect circuit model is solved by using a SPICE solver or an Euler iteration method to reconstruct the distribution of the high-dimensional stress field, and the distribution of the high-dimensional stress field is expressed as: , and obtain the corresponding model simulation results; among them, express The corresponding high-dimensional stress field and ; Using the finite element method to simulate the electro-thermal migration effect of the interconnection line to obtain corresponding finite element simulation results; The model simulation results are compared with the finite element simulation results to obtain verification results of the electro-thermal migration effect circuit model.

7. A device for constructing a circuit model of an electro-thermal migration effect of an interconnect, characterized in that: The construction device comprises: A derivation module is used to derive the equivalent circuit model of the interconnect under the electro-thermal migration effect based on the Korhonen control equation and boundary conditions; A determination module, used to determine the circuit matrix equation corresponding to the equivalent circuit model by using an improved node analysis method; The dimension reduction module is used to perform dimension reduction processing on the circuit matrix equation to obtain the electro-thermal migration effect circuit model of the interconnection line.

8. An electronic device, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 6.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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