PWM waveform output device supporting single pulse mode and application method thereof

Abstract

The invention discloses a PWM waveform output device supporting a single pulse mode and an application method thereof.The device comprises a register module, a pulse number control processing module and a pulse delay control processing module, and the register module is connected with the control end of the pulse number control processing module and the control end of the pulse delay control processing module; input PWM square waves firstly enter the pulse number control processing module for number control, and then are subjected to delay control through the pulse delay control processing module to obtain output PWM square waves. On the basis that the high-precision pulse width modulator outputs PWM square waves with adjustable frequency and duty ratio, the PWM waveforms with fixed delay and quantity are automatically output through mode enabling after relevant configuration is carried out according to user requirements, it is ensured that the specific requirements of users are met, and the phenomenon of repeated sampling is avoided.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design, and in particular relates to a PWM waveform output device supporting a single pulse mode and an application method thereof. Background Art

[0002] In integrated circuit design, enhanced High-Resolution PulseWidth Modulator (eHRPWM) can be used to achieve output waveforms with adjustable frequency and duty cycle. It is widely used in many fields such as measurement and power control. Its main function is to output PWM square waves with adjustable frequency and duty cycle, and channels A and B are independent of each other. Users can configure eHRPWM according to their needs to obtain the required PWM waveform. However, most of the PWM waveforms currently output by eHRPWM are continuous periodic square waves. If the user has specific requirements for the delay and quantity of the required output waveform, the continuous output waveform will lead to repeated sampling and other phenomena, affecting user use. The single pulse mode is widely used in medical equipment, radar systems, electronic measurement and other fields. Output single pulse mode OPM (One-Pulse Mode) such as Figure 1 As shown, in the single pulse mode, after receiving an external or internal trigger event, a single pulse with a controllable delay can be generated. At the same time, single or multiple pulses can be output according to the configuration. This mode is currently mainly used in timers, but the configurable space for the duty cycle of the timer output waveform and the number of selectable outputs are relatively limited. Summary of the invention

[0003] Technical problem to be solved by the present invention: In view of the above-mentioned problems in the prior art, a PWM waveform output device supporting a single pulse mode and an application method thereof are provided. The present invention aims to realize an output PWM square wave with adjustable frequency and duty cycle based on a high-precision pulse width modulator, and through mode enabling, perform relevant configuration according to user needs, and automatically output a PWM waveform with a fixed delay and quantity to ensure that the user's specific needs are met and avoid the phenomenon of repeated sampling.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: A PWM waveform output device supporting a single pulse mode comprises a register module, a pulse quantity control processing module and a pulse delay control processing module. The register module is used to realize the delay and quantity configuration in the single pulse mode and the enabling control of the single pulse mode. The register module is respectively connected to the control ends of the pulse quantity control processing module and the pulse delay control processing module. The input PWM square wave first enters the pulse quantity control processing module for quantity control and then passes through the pulse delay control processing module for delay control to obtain an output PWM square wave.

[0005] Optionally, the single pulse mode output control module further includes a configuration interface, which is connected to the CPU for configuring a register module, and the configuration value is used to control control parameters of both the pulse quantity control processing module and the pulse delay control processing module.

[0006] Optionally, the PWM waveform output device includes two channels, channel A and channel B, and the register module includes a control register OPMCTL, which is used to configure whether to enable the single pulse mode; a channel A waveform quantity register OPMNUMA, which is used to set the number of waveforms output by channel A in the single pulse mode; a channel A delay quantity register OPMDELAYA, which is used to set the delay number of the waveform output by channel A in the single pulse mode; a channel B waveform quantity register OPMNUMB, which is used to set the number of waveforms output by channel B in the single pulse mode; a channel B delay quantity register OPMDELAYB, which is used to set the delay number of the waveform output by channel A in the single pulse mode. B output waveform delay number; the pulse quantity control processing module controls the quantity of PWM square waves output by channel A and channel B according to the configuration values ​​of channel A waveform quantity register OPMNUMA and channel B waveform quantity register OPMNUMB when the control register OPMCTL selects to enable the single pulse mode; the pulse delay control processing module controls the delay of PWM square waves output by channel A and channel B according to the configuration values ​​of channel A delay quantity register OPMDELAYA and channel B delay quantity register OPMDELAYB when the control register OPMCTL selects to enable the single pulse mode.

[0007] Optionally, the control register OPMCTL includes two enable control bits, channel A enable OPMAEN and channel B enable OPMBEN, wherein channel A enable OPMAEN is used to individually control the enablement of channel A single pulse mode, and channel B enable OPMBEN is used to individually control the enablement of channel B single pulse mode.

[0008] Optionally, the control register OPMCTL includes an enable control bit of output enable OPMABEN, and the output enable OPMABEN is used to control the enable of channel A and channel B at the same time.

[0009] Optionally, the bit widths of the channel A waveform quantity register OPMNUMA, the channel A delay quantity register OPMDELAYA, the channel B waveform quantity register OPMNUMB, and the channel B delay quantity register OPMDELAYB are all 16.

[0010] Optionally, the pulse quantity control processing module performs quantity control including: counting the rising edges of the periodic PWM square waves input into channel A and channel B respectively; if the rising edge count value of channel A and the register value of the waveform quantity register OPMNUMA of channel A are consistent, then the periodic PWM square wave output of channel A is terminated and the output is kept at a low level; otherwise, the periodic PWM square wave output of channel A is maintained; if the rising edge count value of channel B and the register value of the waveform quantity register OPMNUMB of channel B are consistent, then the periodic PWM square wave output of channel B is terminated and the output is kept at a low level; otherwise, the periodic PWM square wave output of channel B is maintained.

[0011] Optionally, the pulse delay control processing module performs delay control including: respectively counting the high level and low level of the PWM square wave input by channel A and channel B after being processed by the pulse quantity control processing module; if the level count value of channel A and the register value of the channel A delay quantity register OPMDELAYA are consistent, channel A is output with the PWM waveform after the current delay processing; if the level count value of channel B and the register value of the channel B delay quantity register OPMDELAYB are consistent, the PWM waveform after the current delay processing of channel B is output.

[0012] Optionally, the input end of the pulse quantity control processing module is connected to a waveform generator that generates an input PWM square wave.

[0013] In addition, the present invention also provides an application method of the PWM waveform output device supporting the single pulse mode, comprising the following steps: S101, the pulse quantity control processing module and the pulse delay control processing module read the control register OPMCTL respectively to determine whether to enter the single pulse mode. If the single pulse mode is entered, the PWM square wave is output and the step is jumped to S102, otherwise the step is directly jumped to S104; S102, the pulse quantity control processing module reads the register value of the waveform quantity register OPMNUMA of channel A and the register value of the waveform quantity register OPMNUMB of channel B respectively; counts the rising edges of the periodic PWM square waves input into the two channels of channel A and channel B respectively, if the rising edge count value of channel A and the register value of the waveform quantity register OPMNUMA of channel A are consistent, then the periodic PWM square wave output of channel A is terminated and the output is kept at a low level, otherwise the periodic PWM square wave output of channel A is maintained; if the rising edge count value of channel B and the register value of the waveform quantity register OPMNUMB of channel B are consistent, then the periodic PWM square wave output of channel B is terminated and the output is kept at a low level, otherwise the periodic PWM square wave output of channel B is maintained; finally, the PWM square wave after the quantity control is completed is output to the pulse delay control processing module; S103, the pulse delay control processing module reads the register value of the channel A delay quantity register OPMDELAYA and the register value of the channel B delay quantity register OPMDELAYB respectively, and counts the high level and low level of the PWM square wave input by the two channels A and channel B after being processed by the pulse quantity control processing module respectively. If the level count value of channel A and the register value of the channel A delay quantity register OPMDELAYA are consistent, channel A outputs the PWM waveform after the current delay processing; if the level count value of channel B and the register value of the channel B delay quantity register OPMDELAYB are consistent, channel B outputs the PWM waveform after the current delay processing; finally, the PWM square wave after the quantity control and delay control is completed is obtained; S104, outputting the PWM square wave after completing quantity control and delay control. If the single pulse mode is not enabled, outputting it as a periodic PWM square wave.

[0014] Compared with the prior art, the present invention mainly has the following advantages: the PWM waveform output device of the present invention includes a register module, a pulse quantity control processing module and a pulse delay control processing module, the register module is used to realize the delay and quantity configuration in the single pulse mode and the enable control of the single pulse mode, the register module is respectively connected to the control ends of the pulse quantity control processing module and the pulse delay control processing module, the input PWM square wave first enters the pulse quantity control processing module for quantity control, and then passes through the pulse delay control processing module for delay control to obtain the output PWM square wave, the present invention can configure the enable, output delay and quantity register of the single pulse mode through the register module, the pulse quantity control processing module and the pulse delay control processing module, and can automatically output a certain number of PWM square waves with adjustable duty cycle after fixed quantity and delay processing, to ensure that the specific needs of users are met and avoid repeated sampling. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the output single pulse mode (OPM mode) in the prior art.

[0016] Figure 2 Schematic diagram of the overall structure of the PWM waveform output device in an embodiment of the present invention.

[0017] Figure 3 Schematic diagram of the working process of the PWM waveform output device in an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be further described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention. The present invention is expected to design a PWM waveform output device that supports a single pulse mode (One-Pulse Mode, OPM mode) on the basis of realizing an output PWM square wave with adjustable frequency and duty cycle. By enabling the mode and performing relevant configuration according to user needs, the PWM waveform with a fixed delay and quantity can be automatically output to avoid the continuous waveform output affecting user use. Figure 2 As shown, the PWM waveform output device supporting the single pulse mode in this embodiment includes a register module, a pulse quantity control processing module and a pulse delay control processing module. The register module is used to realize the delay and quantity configuration in the single pulse mode and the enable control of the single pulse mode. The register module is respectively connected to the control ends of the pulse quantity control processing module and the pulse delay control processing module. The input PWM square wave first enters the pulse quantity control processing module for quantity control, and then passes through the pulse delay control processing module for delay control to obtain the output PWM square wave.

[0019] like Figure 2 As shown, the PWM waveform output device of this embodiment also includes a configuration interface, which is connected to the CPU for configuring the register module, and the configuration value is used to control the control parameters of both the pulse quantity control processing module and the pulse delay control processing module.

[0020] This embodiment combines the characteristics of a PWM waveform output device that supports a single pulse mode with a high-precision pulse width modulator (hereinafter referred to as eHRPWM) to design a PWM waveform output device that supports single pulse mode output. This embodiment supports a PWM waveform output device in a single pulse mode that can achieve pulse width modulation (hereinafter referred to as PWM) waveform output with adjustable frequency and duty cycle, and the component includes two independent channels, channel A and channel B, represented by: ePWMA and ePWMB, which are independent of each other. The single pulse mode can control the delay of the output waveform and the number of output waveforms. This solution has a flexible configuration method, and users can configure the delay and number of output PWM waveforms according to their needs to obtain a PWM waveform output with an adjustable duty cycle under the single pulse mode.

[0021] The register module is used to implement the delay, quantity configuration and enable control in the single pulse mode. After the basic configuration of the eHRPWM component, the two independent channels can continuously generate periodic PWM square waves respectively. The user can control the generation of PWM waveforms in the single pulse mode by configuring the registers related to the single pulse mode. A total of five registers are used for control. The single pulse mode can be enabled. According to the configuration values ​​of the channel A / B waveform quantity and the delay quantity register, a fixed delay and quantity-controlled PWM waveform is output. Specifically, the register module in this embodiment includes: Control register OPMCTL is used to configure whether to enable single pulse mode; Channel A waveform quantity register OPMNUMA is used to set the number of channel A output waveforms in single pulse mode; Channel A delay quantity register OPMDELAYA is used to set the delay quantity of the output waveform of channel A in single pulse mode; Channel B waveform quantity register OPMNUMB is used to set the number of channel B output waveforms in single pulse mode; Channel B delay quantity register OPMDELAYB is used to set the delay quantity of the output waveform of channel B in single pulse mode; When the control register OPMCTL selects to enable the single pulse mode, the pulse quantity control processing module controls the quantity of PWM square waves output by channel A and channel B according to the configuration values ​​of the channel A waveform quantity register OPMNUMA and the channel B waveform quantity register OPMNUMB; when the control register OPMCTL selects to enable the single pulse mode, the pulse delay control processing module controls the delay of the PWM square waves output by channel A and channel B according to the configuration values ​​of the channel A delay quantity register OPMDELAYA and the channel B delay quantity register OPMDELAYB.

[0022] According to the control register OPMCTL, the current single pulse mode enable can be selected. If enabled, the single pulse mode processing is performed. If not enabled, the original periodic PWM waveform is output. As an optional implementation, the control register OPMCTL in this embodiment includes two enable control bits, channel A enable OPMAEN and channel B enable OPMBEN, wherein channel A enable OPMAEN is used to control the enable of channel A alone, and channel B enable OPMBEN is used to control the enable of channel B alone. In this embodiment, the bit width of the control register OPMCTL is 16 bits, and the domain definition of the control register OPMCTL is shown in Table 1.

[0023] Table 1: Field definition of control register OPMCTL

[0024] As another optional implementation, the control register OPMCTL includes an enable control bit of output enable OPMABEN, and the output enable OPMABEN is used to control the enable of channel A and channel B at the same time.

[0025] In this embodiment, the bit widths of channel A waveform quantity register OPMNUMA, channel A delay quantity register OPMDELAYA, channel B waveform quantity register OPMNUMB, and channel B delay quantity register OPMDELAYB are all 16, and the domain definitions are shown in Tables 2 to 5.

[0026] Table 2: Field definition of channel A waveform number register OPMNUMA

[0027] Table 3: Field definition of channel A delay quantity register OPMDELAYA

[0028] Table 4: Field definition of channel B waveform number register OPMNUMB

[0029] Table 5: Field definition of channel B delay quantity register OPMDELAYB

[0030] In this embodiment, the pulse quantity control processing module performs quantity control including: counting the rising edges of the periodic PWM square waves inputted by the two channels A and B respectively; if the rising edge count value of channel A and the register value of the waveform quantity register OPMNUMA of channel A are consistent, then the periodic PWM square wave output of channel A is terminated and the output is kept at a low level, otherwise the periodic PWM square wave output of channel A is maintained; if the rising edge count value of channel B and the register value of the waveform quantity register OPMNUMB of channel B are consistent, then the periodic PWM square wave output of channel B is terminated and the output is kept at a low level, otherwise the periodic PWM square wave output of channel B is maintained. For example, when the single pulse mode is enabled, taking the OPMNUMA / OPMNUMB register value as 0x4 as an example, 4 PWM square waves will be output, and then maintained at a low level until the next register value modification and the output processing is performed again.

[0031] In this embodiment, the pulse delay control processing module performs delay control including: respectively counting the high level and low level of the PWM square wave processed by the pulse quantity control processing module input to the two channels of channel A and channel B, if the level count value of channel A and the register value of the channel A delay quantity register OPMDELAYA are consistent, then channel A outputs the PWM waveform after the current delay processing; if the level count value of channel B and the register value of the channel B delay quantity register OPMDELAYB are consistent, then channel B outputs the PWM waveform after the current delay processing. For example, when the single pulse mode is enabled, taking the OPMDELAYA / OPMDELAYB register value of 0x4 as an example, based on the original PWM waveform after the quantity control processing, the PWM waveform will be delayed for 4 clock cycles before being output, until the next register value modification is performed and the output processing is performed again.

[0032] In addition, in this embodiment, the input end of the pulse quantity control processing module of the PWM waveform output device supporting the single pulse mode is connected to a waveform generator that generates an input PWM square wave.

[0033] like Figure 3 As shown, this embodiment also provides an application method of the PWM waveform output device supporting the single pulse mode, comprising the following steps: S101, the pulse quantity control processing module and the pulse delay control processing module read the control register OPMCTL respectively to determine whether to enter the single pulse mode. If the single pulse mode is entered, the PWM square wave is output and the step is jumped to S102, otherwise the step is directly jumped to S104; S102, the pulse quantity control processing module reads the register value of the waveform quantity register OPMNUMA of channel A and the register value of the waveform quantity register OPMNUMB of channel B respectively; counts the rising edges of the periodic PWM square waves input into the two channels of channel A and channel B respectively, if the rising edge count value of channel A and the register value of the waveform quantity register OPMNUMA of channel A are consistent, then the periodic PWM square wave output of channel A is terminated and the output is kept at a low level, otherwise the periodic PWM square wave output of channel A is maintained; if the rising edge count value of channel B and the register value of the waveform quantity register OPMNUMB of channel B are consistent, then the periodic PWM square wave output of channel B is terminated and the output is kept at a low level, otherwise the periodic PWM square wave output of channel B is maintained; finally, the PWM square wave after the quantity control is completed is output to the pulse delay control processing module; when the register value of the waveform quantity register OPMNUMA of channel A and the register value of the waveform quantity register OPMNUMB of channel B are rewritten, the rising edges are counted again; S103, the pulse delay control processing module reads the register value of the delay quantity register OPMDELAYA of channel A and the register value of the delay quantity register OPMDELAYB of channel B respectively, and counts the high level and low level of the PWM square wave input by the two channels A and channel B after being processed by the pulse quantity control processing module respectively. If the level count value of channel A and the register value of the delay quantity register OPMDELAYA of channel A are consistent, channel A outputs the PWM waveform after the current delay processing; if the level count value of channel B and the register value of the delay quantity register OPMDELAYB of channel B are consistent, channel B outputs the PWM waveform after the current delay processing; finally, the PWM square wave after the quantity control and delay control is completed is obtained; when the register value of the delay quantity register OPMDELAYA of channel A and the register value of the delay quantity register OPMDELAYB of channel B are rewritten, the counting is restarted; S104, outputting the PWM square wave after completing quantity control and delay control. If the single pulse mode is not enabled, outputting it as a periodic PWM square wave.

[0034] It can be seen that the PWM waveform output device supporting the single pulse mode in this embodiment mainly has the following two improvements: 1. Single pulse mode PWM waveform output with adjustable duty cycle: On the basis of the existing eHRPWM device outputting PWM square waves with adjustable frequency and duty cycle, the delay and quantity control in the single pulse mode is introduced. By counting the rising edge of the PWM square wave and comparing it with the quantity configuration register in the single pulse mode, the PWM waveform after quantity processing is obtained; and on this basis, the high level and low level of its waveform are processed and compared with the delay control register in the single pulse mode to obtain the PWM waveform output after delay and quantity processing in the single pulse mode. The device in this embodiment adds single pulse mode control on the basis of the periodic PWM square wave output by the eHRPWM device. Users can configure the generation of PWM waveforms with fixed delay and quantity according to their needs, and the PWM duty cycle is adjustable, the configuration is flexible, and the repeated sampling caused by the periodic PWM square wave is avoided under the background of specific needs, thereby improving the flexibility of use. 2. Adding independent selection registers for delay and quantity in single pulse mode: The device of this embodiment adds delay and quantity selection registers in single pulse mode for the two independent channels of the eHRPWM device. Both registers are 16-bit registers, which are consistent with the register bit width of the eHRPWM device. The device of this embodiment can configure registers for the two independent channel outputs of the eHRPWM device to realize the output delay and quantity selection of the PWM waveform in the single pulse mode. The main advantages of the device of this embodiment are: 1. On the basis of the output waveform of the eHRPWM device, by adding a single pulse mode output control, the user can configure the relevant registers according to the needs, and after logical processing, a fixed delay and quantity PWM square wave can be obtained. Compared with the output waveform of the ordinary eHRPWM device, it can be flexibly configured according to user needs, which increases the use efficiency and avoids repeated sampling under specific needs. 2. The control registers of the single pulse mode are configured for the two independent channels of the eHRPWM device to improve the flexibility of use. 3. Give priority to the single pulse mode enable control, optimize power consumption, and reduce unnecessary signal flips.

[0035] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A PWM waveform output device supporting a single pulse mode, characterized in that: It includes a register module, a pulse quantity control processing module and a pulse delay control processing module. The register module is used to realize the delay and quantity configuration in the single pulse mode and the enable control of the single pulse mode. The register module is respectively connected to the control ends of the pulse quantity control processing module and the pulse delay control processing module. The input PWM square wave first enters the pulse quantity control processing module for quantity control, and then passes through the pulse delay control processing module for delay control to obtain the output PWM square wave.

2. The PWM waveform output device supporting the single pulse mode according to claim 1, characterized in that: The single pulse mode output control module also includes a configuration interface, which is connected to the CPU for configuring the register module, and the configuration value is used to control the control parameters of both the pulse quantity control processing module and the pulse delay control processing module.

3. The PWM waveform output device supporting the single pulse mode according to claim 1, characterized in that: The PWM waveform output device includes two channels, channel A and channel B. The register module includes a control register OPMCTL, which is used to configure whether to enable the single pulse mode; a channel A waveform quantity register OPMNUMA, which is used to set the number of waveforms output by channel A in the single pulse mode; a channel A delay quantity register OPMDELAYA, which is used to set the delay number of the waveform output by channel A in the single pulse mode; a channel B waveform quantity register OPMNUMB, which is used to set the number of waveforms output by channel B in the single pulse mode; a channel B delay quantity register OPMDELAYB, which is used to set the delay number of the waveform output by channel B in the single pulse mode. Delay quantity; when the control register OPMCTL selects to enable the single pulse mode, the pulse quantity control processing module controls the quantity of PWM square waves output by channel A and channel B according to the configuration values ​​of channel A waveform quantity register OPMNUMA and channel B waveform quantity register OPMNUMB; when the control register OPMCTL selects to enable the single pulse mode, the pulse delay control processing module controls the delay of the PWM square waves output by channel A and channel B according to the configuration values ​​of channel A delay quantity register OPMDELAYA and channel B delay quantity register OPMDELAYB.

4. The PWM waveform output device supporting the single pulse mode according to claim 3, characterized in that: The control register OPMCTL includes two enable control bits, channel A enable OPMAEN and channel B enable OPMBEN, wherein channel A enable OPMAEN is used to individually control the enablement of channel A output single pulse mode, and channel B enable OPMBEN is used to individually control the enablement of channel B output single pulse mode.

5. The PWM waveform output device supporting the single pulse mode according to claim 3, characterized in that: The control register OPMCTL includes an enable control bit of output enable OPMABEN, and the output enable OPMABEN is used to control the enable of channel A and channel B at the same time.

6. The PWM waveform output device supporting the single pulse mode according to claim 3, characterized in that: The bit widths of the channel A output waveform quantity register OPMNUMA, the channel A output waveform delay quantity register OPMDELAYA, the channel B output waveform quantity register OPMNUMB, and the channel B output waveform delay quantity register OPMDELAYB are all 16.

7. The PWM waveform output device supporting the single pulse mode according to claim 3, characterized in that: The pulse quantity control processing module performs quantity control including: counting the rising edges of the periodic PWM square waves input into the two channels, channel A and channel B, respectively; if the rising edge count value of channel A and the register value of the waveform quantity register OPMNUMA of channel A are consistent, then the periodic PWM square wave output of channel A is terminated and the output is kept at a low level; otherwise, the periodic PWM square wave output of channel A is maintained; if the rising edge count value of channel B and the register value of the waveform quantity register OPMNUMB of channel B are consistent, then the periodic PWM square wave output of channel B is terminated and the output is kept at a low level; otherwise, the periodic PWM square wave output of channel B is maintained.

8. The PWM waveform output device supporting the single pulse mode according to claim 3, characterized in that: The pulse delay control processing module performs delay control including: respectively counting the high level and low level of the PWM square wave input by the two channels, channel A and channel B, after being processed by the pulse quantity control processing module; if the level count value of channel A and the register value of the channel A delay quantity register OPMDELAYA are consistent, channel A outputs the PWM waveform after the current delay processing; if the level count value of channel B and the register value of the channel B delay quantity register OPMDELAYB are consistent, channel B outputs the PWM waveform after the current delay processing.

9. The PWM waveform output device supporting the single pulse mode according to claim 3, characterized in that: The input end of the pulse quantity control processing module is connected to a waveform generator that generates an input PWM square wave.

10. An application method of the PWM waveform output device supporting a single pulse mode as claimed in any one of claims 3 to 8, characterized in that: The steps include: S101, the pulse quantity control processing module and the pulse delay control processing module read the control register OPMCTL respectively to determine whether to enter the single pulse mode. If the single pulse mode is entered, the PWM square wave is output according to the single pulse mode configuration and the step is jumped to S102, otherwise the step is directly jumped to S104; S102, the pulse quantity control processing module reads the register value of the waveform quantity register OPMNUMA of channel A and the register value of the waveform quantity register OPMNUMB of channel B respectively; counts the rising edges of the periodic PWM square waves input into the two channels of channel A and channel B respectively, if the rising edge count value of channel A and the register value of the waveform quantity register OPMNUMA of channel A are consistent, then the periodic PWM square wave output of channel A is terminated and the output is kept at a low level, otherwise the periodic PWM square wave output of channel A is maintained; if the rising edge count value of channel B and the register value of the waveform quantity register OPMNUMB of channel B are consistent, then the periodic PWM square wave output of channel B is terminated and the output is kept at a low level, otherwise the periodic PWM square wave output of channel B is maintained; finally, the PWM square wave after the quantity control is completed is output to the pulse delay control processing module; S103, the pulse delay control processing module reads the register value of the channel A delay quantity register OPMDELAYA and the register value of the channel B delay quantity register OPMDELAYB respectively, and counts the high level and low level of the PWM square wave input by the two channels A and channel B after being processed by the pulse quantity control processing module. If the level count value of channel A and the register value of the channel A delay quantity register OPMDELAYA are consistent, channel A outputs the PWM waveform after the current delay processing; If the level count value of channel B and the register value of the channel B delay quantity register OPMDELAYB are consistent, channel B outputs the PWM waveform after the current delay processing; Finally, the PWM square wave is obtained after completing quantity control and delay control; S104, outputting the PWM square wave after completing quantity control and delay control. If the single pulse mode is not enabled, outputting it as a periodic PWM square wave.

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