Integrated learning-based parasitic capacitance estimation method in pre-layout stage

Abstract

The invention belongs to the technical field of chip design, and particularly relates to a method for estimating interconnection line parasitic capacitance based on integrated learning in a pre-layout stage, which can improve the accuracy of dynamic power consumption calculation in the early stage of physical design. Comprising the following steps: S1, extracting original data of a circuit and calculating physical characteristics of an interconnection line; s2, establishing a feature-capacitance label supervision training data set of the interconnection line; s3, training an interconnection line parasitic capacitance prediction model; and S4, after the training stage is ended, entering a prediction stage, and taking the physical characteristics of the interconnection line in the current design pre-layout stage as the input of an interconnection line stray capacitance prediction model to obtain predicted stray capacitance. The method is simple and easy to use, the pre-layout information and the final design result have high consistency, the accuracy of circuit power consumption calculation in the early stage of physical design can be improved, and the design period is shortened.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip design, and in particular relates to a method for estimating parasitic capacitance of interconnect lines based on integrated learning in a pre-layout stage, which can improve the accuracy of dynamic power consumption calculation in the early stage of physical design. Background Art

[0002] In the digital integrated circuit design process, with the continuous advancement of semiconductor technology, the number of transistors integrated in the chip has grown exponentially as predicted by Moore's Law. While integration density and speed performance have made amazing progress, power consumption has quickly become one of the important considerations in digital integrated circuit design.

[0003] The power consumption of digital integrated circuits is divided into dynamic power consumption and static power consumption. Dynamic power consumption refers to the power consumption generated by the circuit due to signal flipping, including dynamic power consumption caused by charging and discharging capacitors and dynamic power consumption caused by short direct paths of devices during switching. The flip power consumption of charging and discharging capacitors is determined by the flip frequency of the signal and the output capacitance load, and is the main part of the circuit power consumption. The output capacitance load includes the parasitic capacitance of the interconnection line and the input capacitance of the driven port. With the continuous evolution of the process and the gradual reduction of the size of the interconnection line, the wiring of the interconnection line is denser and the parasitic capacitance is larger. A large number of parasitic capacitances of interconnection lines cannot be estimated and calculated into the flip power consumption in the early stage of design because the physical wiring has not been completed. In particular, when the power consumption of the register transfer level is estimated based on the logical connection of the gate-level netlist, the types and number of standard cells of the clock tree will be estimated in advance according to the register clock source point. The flip frequency of the standard cells used to generate the clock tree is high, and the interconnection lines are spread throughout the chip, which is prone to long line problems. Before the wiring is completed, it will not be considered, which will lead to greater neglect of the charging and discharging power consumption of the parasitic capacitance of the interconnection line.

[0004] Current state of the art 1. Interconnect load model In order to solve the problem that the power consumption of interconnects cannot be considered in the early stage of design, researchers have developed an interconnect load model. Through simulation and other means, they have established capacitance and resistance models for interconnects. When used for dynamic power consumption calculation, we pay more attention to the capacitance part. The interconnect capacitance load model gives the capacitance value per unit length. The length of the interconnect is estimated based on the number of loads driven by the output port, that is, the fan-out value. A one-dimensional lookup table of fan-out-line length is established. The values ​​within the fan-out range can be directly obtained by looking up the table. The fan-out values ​​that are not within the range can be interpolated based on the given slope value and the existing values ​​in the table to estimate the line length value. Then, the estimated capacitance value is obtained by multiplying the product based on the capacitance value per unit length. Generally speaking, the capacitance load model of interconnects provides multiple models to provide different pessimism for estimation, but the fan-out value alone is not enough to reflect the length of the interconnect, and it is difficult to accurately calculate the capacitance of the interconnect. Under the open source 45nm process, the error value between the interconnect capacitance estimated by the experimental interconnect capacitance load model and the interconnect capacitance extracted using parasitic parameters after wiring can be as high as 50%.

[0005] The interconnect load model is commonly used in older process nodes. It uses linear interpolation to estimate parasitic capacitance based on fan-out. The model estimates the capacitance value optimistically and gives the same parasitic capacitance value for interconnects with the same fan-out but different actual lengths in actual physical design. It is unable to perceive the physical characteristics of the circuit design, which limits the accuracy of the model. In addition, at advanced process nodes, the zero-line load model is often used for initial iterations, which can cause early designs to be overly optimistic and require an increased number of iterations to meet power consumption constraints, thus extending the design cycle and losing a large space for power consumption optimization in the early stages of the design.

[0006] Since the interconnection line load model has a large error, it has been gradually abandoned in the actual design process and replaced by the neutral line load model and topology mode.

[0007] 2. Neutral line load model In the physical design process of digital circuits, in order to optimize the performance, power consumption, and area of ​​chips, a zero-line load model is used in the early stage of design, that is, all interconnects are considered to have zero capacitance load in the early stage for power consumption, and then the design is iterated in the later stage. This prolongs the design cycle and loses the large power consumption optimization space in the early stage of design. In addition, many chips have design version iterations. For example, the chip released last year has a similar design in the same series this year. Ansys's PowerArtist power analysis prediction tool (hereinafter referred to as the "PA tool") uses iterative design data to calculate interconnect load models (called PACE models, i.e. PowerArtist Calibration and Estimation Model) for different circuit types, such as combinational logic, sequential logic, clock, and storage cells. The PA tool generates fan-out-capacitance models for different circuit types based on the design files after clock tree synthesis and layout generation, including netlist files, logic library files, and parasitic parameter extraction files. The PA tool establishes the PACE model as follows: (1) Parse the gate-level netlist designed after the layout. (2) Read the parasitic parameter extraction file designed after the layout. (3) Calculate and generate the PACE model.

[0008] Problems: For the PACE model used by the PA tool, the model calculates a customized line load model based on the type of circuit. The independent variable of the model is still the fan-out value. This feature alone cannot accurately reflect the physical differences between the interconnects, nor can it calculate the differentiated and accurate capacitance values. The same function is used to estimate the capacitance of interconnects within the same circuit type. The model lacks perception of the physical characteristics of the design. In addition, the model lacks generalization and requires iterations of the same design to provide an interconnect load model customized for a suitable circuit type.

[0009] 3. Topology mode The process of converting a digital circuit design from register transfer level code to a logical connection netlist of standard cells is called synthesis. Synopsys' Design Compiler tool (hereinafter referred to as "DC tool") is generally used. In the past, when the wire load model was still relatively effective, the wire load mode of the DC tool was used in the synthesis process. Nowadays, because the wire load model has produced large errors, the wire load mode of the DC tool is no longer used, and the DC tool's topology mode is used instead. The DC tool uses Synopsys' physical implementation strategy, namely virtual layout and routing, to generate a virtual layout of a circuit, and then obtains the actual interconnect line capacitance value through the line length and the corresponding line length-capacitance lookup table file. The method for the DC tool to calculate the parasitic capacitance of the interconnect line using the topology mode is as follows: (1) Input the design netlist, constraint file, logic library, physical library, etc. (2) Use the DC tool in topology mode for synthesis. (3) Write a parasitic parameter file in SPEF (Standard Parasitic Exchange Format) format to obtain the interconnect line capacitance value.

[0010] The DC tool can use the topology mode to synthesize the register transfer level netlist to obtain a virtual layout and give an estimated parasitic capacitance of the interconnect line. This mode has some problems. First, the implementation process of automatic layout and routing is extremely time-consuming, especially the routing stage. In the standard physical implementation of automatic layout and routing stage, the tool needs to check the physical design constraints at all times. The topology mode of the tool is a simplification of the automatic layout and routing process, which can omit the check of physical design constraints. However, for VLSI, it is as time-consuming and difficult to handle as just layout and generating routing. Second, this virtual layout is very time-consuming and difficult to handle. Figure 1There will definitely be a big difference between the results obtained after actual physical synthesis. First, as mentioned in the first point, physical design constraints run through the entire automatic layout and routing stage, and the generation of the virtual layout can choose whether to consider these constraints. The factors considered in virtual routing will be very different from those in real routing, and it is difficult to ensure that the generated interconnect capacitance is consistent with the results after real physical implementation. Secondly, the algorithm differences of the virtual layout engine and the manual placement differences of the intellectual property circuit design module in the layout planning stage will also lead to a big difference in the standard cell placement results of the virtual layout; thirdly, in addition to the common input files required for synthesis, the DC tool uses the topology mode input, and also needs to provide additional physical library and physical constraint files. The physical library format is the Milkyway format file unique to Synopsys, and it is difficult to build a library. In addition, physical constraint files such as layout planning constraints are also difficult to obtain in the early stages of design. Experienced physical design engineers are required to provide more accurate placement positions of intellectual property circuit design modules to ensure the consistency of the virtual layout and subsequent designs. These problems limit the front-end designers from using tools to better obtain interconnect parasitic capacitance and power consumption information earlier. In general, the tool provides designers with a design possibility and a more accurate power consumption reference for such a design. However, the trade-offs are that the process of generating a virtual layout and calculating the capacitance of interconnects is time-consuming. Second, the process of generating a virtual layout lacks the perception of the constraints added by the designer during the physical implementation process, and it is difficult to achieve consistency with the designer's design intent, which will lead to a large difference between the actual generated interconnect results and the results after the actual physical implementation. Third, the additional input files of the topology model are complex and not easy to use.

[0011] With the evolution of process technology, the dynamic power consumption caused by the parasitic capacitance of interconnects accounts for an increasingly large proportion of the total power consumption, and has reached a point where it cannot be ignored. It is critical to estimate the power consumption of circuits in the early stages of physical design, especially for low-power designs. In the pre-layout stage, standard cells and various circuit modules have been roughly laid out, but the wiring has not yet been completed, so it is difficult to determine the parasitic capacitance of interconnects, and the wiring work takes a lot of time. Estimating power consumption at an earlier stage of design helps to quickly iterate the design. In the case of no wiring in the pre-layout stage, in order to quickly and accurately calculate the dynamic power consumption caused by the interconnects, narrow the gap with the power consumption after wiring, and meet the power consumption indicators of the design, a method for estimating the parasitic capacitance of interconnects is needed. Summary of the invention

[0012] In view of the problems and shortcomings of the prior art, the purpose of the present application is to be able to estimate more accurate parasitic capacitance information of interconnect lines according to the physical characteristics of the interconnect lines in the pre-layout stage.

[0013] Technical solution of the present invention: A parasitic capacitance estimation method based on ensemble learning in a pre-layout stage comprises the following steps: S1, extracts raw circuit data and calculates physical characteristics of interconnects, including: For the current design in the pre-layout stage and the existing design with completed layout design (1) Extract the raw data related to the interconnection lines.

[0014] (2) Process the above data and calculate the physical characteristic data of the interconnection line.

[0015] The physical feature data of the interconnects extracted and processed from the current design are used for prediction in S4, and the physical feature data of the interconnects extracted and processed from the existing design are used for establishing the interconnect feature-capacitance label supervision training data set in S2 and the training model in S3.

[0016] S2, establish interconnect feature-capacitance label supervision training dataset; The capacitance value of each interconnect line of the existing design is extracted; the interconnect line capacitance is used as a label and the physical feature data of the interconnect line of the existing design of S1 constitutes a supervised training data set.

[0017] S3, training the interconnect parasitic capacitance prediction model: using the interconnect feature-capacitance supervision data set established in S2 as the input of the interconnect parasitic capacitance prediction model for model training, and obtaining the interconnect parasitic capacitance prediction model.

[0018] S4, after the training phase is completed, the prediction phase is entered, and the physical characteristics of the interconnection lines in the current design pre-layout phase are used as the input of the interconnection line parasitic capacitance prediction model to obtain the predicted parasitic capacitance.

[0019] Beneficial Effects The present invention optimizes the physical characteristics of interconnects, establishes a data structure for information related to the physical characteristics of the interconnects, extracts the physical characteristics and capacitance value information of the interconnects of existing designs, establishes a feature-capacitance label supervision training data set for the interconnects, and obtains a random forest model capable of predicting the capacitance value of the interconnects through training. After the interconnect capacitance prediction model is determined, the subsequent interconnect capacitance calculation step for a new design of the same process only needs to rely on the position information of the instantiated unit given in the pre-layout stage, and the physical characteristics of the interconnects can be obtained and the capacitance value of the interconnects can be predicted based on the logical connection relationship of the interconnects.

[0020] The method of the present invention is used to calculate the dynamic power consumption of the circuit, which helps to improve the accuracy of circuit power consumption calculation in the early stage of physical design, and makes up for the shortcomings of the interconnect load model that lacks physical perception and requires multiple design iterations to meet power consumption constraints under advanced processes.

[0021] The interconnect capacitance prediction model can be trained and generated before circuit design work, which speeds up the design cycle.

[0022] The input file required by the method of the present invention is universal and simple and easy to read. The model can quickly map from feature input to capacitance value, and the predicted capacitance value of the interconnect line can be obtained in the early stage of physical design without wiring operation. The method is simple and easy to use, and the pre-layout information has a high consistency with the final design result.

[0023] Compared with the existing methods, the present invention uses multiple circuit physical features to improve the accuracy of the model in order to address the shortcomings of the neutral line load model and the topological mode. The model of the present invention can be trained and generated before circuit design work, has high generalization, does not require design iteration, and speeds up the design cycle.

[0024] In view of the shortcomings of the topological mode solution, the model of the present invention maps features to predicted capacitance values ​​very quickly, without the need for virtual layout and routing, thus speeding up the design cycle; the physical features extracted by the present invention are derived from the pre-layout results in the physical design process of the circuit, and are highly consistent with the actual layout results; the physical library format used by the present invention is simple and easy to read, eliminating the cumbersome library building steps when using the topological mode solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of the implementation process of the interconnect capacitance estimation method according to an embodiment of the present invention; Figure 2 It is a schematic flow chart of the method for extracting and processing the physical characteristics of the real interconnection line in S1 of the present invention; Figure 3 Schematic diagram of fan-out and pin rectangle in embodiment S1 of the present invention; Figure 4 Schematic diagram of rectangular uniform density in Example S1 of the present invention; Figure 5 Schematic diagram of the structure of the random forest regression model in Example S3 of the present invention. DETAILED DESCRIPTION

[0026] The technical solution provided by the present application will be further described below in conjunction with specific embodiments and accompanying drawings. The advantages and features of the present application will become more apparent with the following description.

[0027] Example This embodiment provides a method for predicting the parasitic capacitance of interconnect lines in the pre-layout stage. Figure 1 The execution subject of this method may be a computing device.

[0028] The above steps are described in detail below.

[0029] S1, respectively extracting the original circuit data of the current design in the pre-layout stage and the existing design with completed layout design and calculating the physical characteristics of the interconnection lines.

[0030] The existing design for which layout design has been completed may be an iterative version of the current design or a post-layout design of other circuits using the same process.

[0031] The circuit scale of the existing design cannot be too small, otherwise it is difficult to learn the relationship between the physical characteristics of the interconnection line and the capacitance. In this embodiment, the layout design of the open source circuit aes is used as the existing design.

[0032] S1 Process Reference Figure 2 ,include: Step S101: Extracting original circuit data Parse the physical library (Library Exchange Format, LEF) file to extract the pin position information of all standard cells, parse the Design Exchange Format (Design Exchange Format, DEF) file to extract the placement and direction of all instantiated cells in the circuit design and the corresponding standard cell names, the pin connection relationship of each interconnection line in the circuit design and the instantiated unit corresponding to the pin, and provide them to step S102.

[0033] The pin location information of the standard unit is represented by the coordinates of the lower left vertex and the upper right vertex of the rectangle, or represented by the coordinates of each vertex of the polygon in a counterclockwise order in a polygon format.

[0034] Step S102: Calculate the physical characteristics of the interconnection lines The physical characteristic data of the interconnection lines are obtained by processing and calculating the original circuit design data.

[0035] Preferably, the physical characteristics of the interconnection line include: fan-out, pin rectangle width, pin rectangle height, pin rectangle semi-perimeter line length, number of Steiner tree candidate points, rectangular uniform density (Rectangular Uniform DensitY, RUDY), and pin density.

[0036] in, Fan-out is the number of input pins driven by an output pin; The pin rectangle is the smallest rectangle that can contain all pins; The pin rectangle width is the horizontal length of the smallest rectangle that can contain all pins; The pin rectangle height is the vertical length of the smallest rectangle that can contain all pins; The semi-perimeter length of the pin rectangle is half the perimeter of the pin rectangle, which is the sum of the width and height of the pin rectangle; See also Figure 3 , is a fan-out 4 interconnection line, the dotted line is the pin rectangle of the interconnection line, and the blue part of the actual routing is exactly equal to the half-circumference length of the pin rectangle, so the half-circumference length of the pin rectangle has a good linear correlation with the actual length of the interconnection line; The number of candidate points of the Steiner tree refers to the number of intersections formed inside and on the border of the smallest rectangle containing all the pins by routing each pin horizontally and vertically in the process of generating the shortest interconnection line; See also Figure 4 , Rectangular uniform density (RUDY) refers to the estimated increase in line length density caused by the overlapping pin rectangles for the target pin rectangle. Its calculation expression is as follows: Where W is the width of the target pin rectangle, H is the height of the target pin rectangle, n is the number of pin rectangles that overlap with it, and W i is the width of the i-th pin rectangle that overlaps with it, H i is the height of the i-th pin rectangle that overlaps with it, w i is the width of the overlapping rectangle, h i is the height of the overlapping rectangle, is the area of ​​the target pin rectangle; Pin density is the number of all pins inside the pin rectangle divided by the area of ​​the pin rectangle.

[0037] In one embodiment of the present invention, the calculation process of the physical characteristics of the interconnection line is as follows: Calculate the fan-out of the interconnects. According to the pin connection relationship of the interconnects, the total number of pins is obtained, and the number of driven pins is subtracted from one driving pin, i.e. the fan-out. Calculate the physical position of each pin corresponding to the interconnection line in the circuit design. According to the name of the instantiated unit corresponding to each pin, the placement position and placement direction of the instantiated unit and the relative position of each pin in the standard unit corresponding to the instantiated unit can be obtained. According to different placement directions, the physical position of each pin of the interconnection line is calculated. According to different placement directions, the calculation expression is as follows: The placement direction is N, and the coordinate expression of each vertex of the pin is (X+x, Y+y); The placement direction is S, and the coordinate expression of each vertex of the pin is (X+wx, Y+hy); The placement direction is W, and the coordinate expression of each vertex of the pin is (X+hy, Y+x); The placement direction is E, and the coordinate expressions of each vertex of the pin are (X+y, Y+wx); The placement direction is FN, and the coordinate expression of each vertex of the pin is (X+wx, Yy); The placement direction is FS, and the coordinate expression of each vertex of the pin is (X+x, Y+hy); The placement direction is FW, and the coordinate expression of each vertex of the pin is (X+y, Y+x); The placement direction is FE, and the coordinate expression of each vertex of the pin is (X+hy, Y+wx); Among them, (X, Y) is the placement position of the example unit, (x, y) is the relative position of the internal pins when the standard unit is placed at the origin in the N direction, and (w, h) is the size information of the unit; The placement direction follows the LEF / DEF file syntax standard and is defined as follows: In LEF files, the default standard cell is placed at the origin (0, 0), and the relative position of the pin is the relative position when the cell is placed in the N orientation. In DEF files, all cells are placed in the lower left corner regardless of the orientation, and the orientation determines how the pin position is calculated relative to the cell orientation.

[0038] Calculate the minimum and maximum values ​​of all pin coordinates on the horizontal and vertical axes, and represent the pin rectangle by the minimum horizontal and vertical coordinates (i.e., the lower left vertex of the pin rectangle) and the maximum horizontal and vertical coordinates (i.e., the upper right vertex of the pin rectangle); Calculate the width and height of the pin rectangle. The absolute value of the difference between the minimum and maximum coordinates of the pin rectangle in the horizontal direction is the width of the pin rectangle, and the absolute value of the difference in the vertical direction is the height of the pin rectangle. Calculate the semi-perimeter length of the pin rectangle, which is the sum of the width and height of the pin rectangle; Calculate the number of Steiner tree candidate points, calculate the average coordinate value of the vertex of each pin in the interconnect as the center point of the pin, and multiply the number of different coordinate values ​​of all pins in the interconnect in the horizontal direction by the number of different coordinate values ​​in the vertical direction and then subtract the number of pins to get the number of Steiner tree candidate points; Calculate the rectangular uniform density. For the target interconnect, traverse the remaining interconnects. If there is overlap, calculate the summation operator part according to the expression, and finally add the half perimeter of the target interconnect and divide it by the pin rectangular area of ​​the target interconnect. Calculate the pin density as the number of pins divided by the pin rectangle area; The above steps are repeatedly performed for each interconnection line to obtain the physical characteristics of all interconnections.

[0039] S2, establish the interconnect feature - capacitance label (in supervised learning, the label is used to identify the output or target value of the input sample. The interconnect feature is the input, and the capacitance is the label, that is, the target output value that the model should be trained to) supervised training data set S201 Extracting the capacitance of interconnect lines in an existing design Parasitic parameters are extracted for the existing design whose layout design has been completed, and the precise interconnect capacitance value of each interconnect line is extracted from the Standard Parastics Exchange Format (SPEF) file as a label for the existing design whose layout design has been completed.

[0040] S202 Create a data set According to the interconnect name, the interconnect capacitance is combined with the interconnect physical feature data of the existing design extracted and processed by S1 to establish a feature-capacitance label data pair, thereby obtaining a supervised training data set.

[0041] S3, training the interconnect parasitic capacitance prediction model, using the interconnect feature-capacitance supervision data set established in S2 as the input of the interconnect parasitic capacitance prediction model for model training, and obtaining the interconnect capacitance prediction model.

[0042] The training method of the interconnect parasitic capacitance prediction model includes: Taking the physical characteristics of the interconnects in the supervised training data set as input and the corresponding capacitance as output, a parasitic capacitance prediction model of the interconnects is trained; and the hyperparameters of the parasitic capacitance prediction model of the interconnects are adjusted.

[0043] Specifically, S301 uses random forest regression model to construct interconnect capacitance prediction model: The interconnect parasitic capacitance prediction model adopts a random forest regression model, which can process data with complex nonlinear relationships, handle missing values, is insensitive to the value range of features, and is applicable to different types of data distribution.

[0044] Assume that the training set is {(x1,y1),(x2,y2),…,(x n ,y n )}, where x is the characteristic value, corresponding to the characteristics of the interconnection line, and y is the label value, corresponding to the capacitance value of the interconnection line; The expression for constructing the initial random forest regression model is as follows: Among them, y is the prediction result of the model, y t is the predicted value of the t-th decision tree, and T is the total number of decision trees; The decision tree uses the mean square error (MSE) as the division criterion: Among them, n is the number of samples in the data set of the decision tree, y i is the true value of the i-th sample, yi ' is the predicted value of the i-th sample; The random forest model structure is as follows Figure 5 shown.

[0045] S302 Adjust hyperparameters of random forest regression model; The hyperparameters include: The number of trees; the maximum depth of the tree; the minimum number of samples required to split a node; the minimum number of samples for a leaf node; the maximum number of features when splitting; the number of random seeds; The above parameters can be adjusted when training a random forest model. For example, the number of trees can be adjusted. The more trees there are, the more stable and generalizable the model will be, but the computational cost will increase.

[0046] In the embodiment, an example of a set of hyperparameter values ​​is: the number of trees is 100, the maximum depth of the tree is set to allow the tree to be fully expanded, the minimum number of samples required to split a node is 2, the minimum number of samples of a leaf node is 1, the maximum number of features during splitting is 7 (all features), and the number of random seeds is 42 (only used to ensure that the training results are repeatable).

[0047] S303 inputs the training data set into the random forest model for training; S4, after the training phase is completed, the prediction phase is entered, and the physical characteristics of the interconnection lines in the current design pre-layout phase are used as the input of the interconnection line parasitic capacitance prediction model to obtain the predicted parasitic capacitance.

[0048] The random forest regression model obtained by S3 is loaded, and the physical characteristics of the interconnects in the current design pre-layout stage are used as the input of the interconnect parasitic capacitance prediction model to predict the interconnect capacitance value.

[0049] In summary, in the interconnect capacitance prediction method in the pre-layout stage provided by the above embodiment, the random forest integrated learning algorithm is used to predict the capacitance of the interconnect by mapping the physical characteristics of the interconnect, without the need for wiring operations, and the model training and generation process is independent of the target design process, which saves time for further power consumption calculation of subsequent circuits and accelerates the design cycle.

[0050] For the AES circuit, the method of the present invention is compared with the interconnect load model method. The average error between the interconnect load model-estimated parasitic capacitance of the interconnect and the interconnect capacitance extracted by the post-layout parasitic parameters is -25.22%, while the average error of the present method is -6.86%, which is improved by 3.68 times, which is helpful to accurately estimate the average power consumption of the circuit in the early stage of design.

Claims

1. A parasitic capacitance estimation method based on ensemble learning in the pre-layout stage, characterized in that: The following steps are involved: S1, extracts raw circuit data and calculates physical characteristics of interconnects, including: Process the current design in the pre-layout stage and the existing design with completed layout design respectively: (1) Extracting raw data related to interconnects; (2) Processing the above data to calculate the physical characteristic data of the interconnection line; The physical feature data of interconnects extracted and processed from the current design are used for prediction in S4, and the physical feature data of interconnects extracted and processed from the existing design are used for establishing the feature-capacitance label supervision training data set of interconnects in S2 and the training model in S3; S2, establish interconnect feature-capacitance label supervision training dataset; Extract the capacitance value of each interconnect line of the existing design; the interconnect line capacitance is used as a label and the physical characteristic data of the interconnect line of S1 existing design is combined into a supervised training data set; S3, training an interconnect parasitic capacitance prediction model: using the interconnect feature-capacitance supervision data set established in S2 as the input of the interconnect parasitic capacitance prediction model for model training, and obtaining the interconnect parasitic capacitance prediction model; S4, after the training phase is completed, the prediction phase is entered, and the physical characteristics of the interconnection lines in the current design pre-layout phase are used as the input of the interconnection line parasitic capacitance prediction model to obtain the predicted parasitic capacitance.

2. The parasitic capacitance estimation method based on ensemble learning in the pre-layout stage according to claim 1, characterized in that: In step S1, the interconnect physical features include: fan-out, pin rectangle width, pin rectangle height, pin rectangle semi-perimeter line length, number of Steiner tree candidate points, rectangle uniform density and pin density; in, Fan-out is the number of input pins driven by an output pin; The pin rectangle is the smallest rectangle that can contain all pins; The pin rectangle width is the horizontal length of the smallest rectangle that can contain all pins; The pin rectangle height is the vertical length of the smallest rectangle that can contain all pins; The semi-perimeter length of the pin rectangle is half the perimeter of the pin rectangle, which is the sum of the width and height of the pin rectangle; The number of candidate points of the Steiner tree refers to the number of intersections formed inside and on the border of the smallest rectangle containing all the pins by routing each pin horizontally and vertically in the process of generating the shortest interconnection line; Rectangular uniform density (RUDY) refers to the estimated increase in line length density caused by the pin rectangles that overlap the target pin rectangle. The calculation expression is as follows: Where W is the width of the target pin rectangle, H is the height of the target pin rectangle, n is the number of pin rectangles that overlap with it, and W i is the width of the i-th pin rectangle that overlaps with it, H i is the height of the i-th pin rectangle that overlaps with it, w i is the width of the overlapping rectangle, h i is the height of the overlapping rectangle, is the area of ​​the target pin rectangle; Pin density is the number of all pins inside the pin rectangle divided by the area of ​​the pin rectangle.

3. The parasitic capacitance estimation method based on ensemble learning in the pre-layout stage according to claim 2, characterized in that: Step S1 includes the following steps: Step S101: Extracting original circuit data Parse the physical library LEF file to extract the pin position information of all standard cells, parse the design exchange format DEF file to extract the placement and direction of all instantiated cells in the circuit design and the corresponding standard cell names, the pin connection relationship of each interconnection line in the circuit design and the instantiated cells corresponding to the pins, and provide them to step S102; Step S102: Calculate the physical characteristics of the interconnection lines The physical characteristic data of the interconnection lines are obtained by processing and calculating the original circuit design data.

4. The parasitic capacitance estimation method based on ensemble learning in the pre-layout stage according to claim 1, characterized in that: Step S2 includes the following steps: S201 Extracting the capacitance of interconnect lines in an existing design Extract parasitic parameters of existing designs that have completed layout design, and extract accurate interconnect capacitance values ​​of each interconnect from the standard parasitic exchange format file SPEF as labels of existing designs that have completed layout design; S202 Create a data set According to the interconnect name, the interconnect capacitance is combined with the interconnect physical feature data of the existing design extracted and processed by S1 to establish a feature-capacitance label data pair, thereby obtaining a supervised training data set.

5. The parasitic capacitance estimation method based on ensemble learning in the pre-layout stage according to claim 1, characterized in that: Step S3 includes the following steps: S301 uses random forest regression model to construct interconnect capacitance prediction model: The interconnect parasitic capacitance prediction model uses a random forest regression model, assuming that the training set is {(x1,y1),(x2,y2),…,(x n ,y n )}, where x is the characteristic value, corresponding to the characteristics of the interconnection line, and y is the label value, corresponding to the capacitance value of the interconnection line; The expression for constructing the initial random forest regression model is as follows: Among them, y is the prediction result of the model, y t is the predicted value of the t-th decision tree, and T is the total number of decision trees; The decision tree uses the mean square error (MSE) as the division criterion: Among them, n is the number of samples in the data set of the decision tree, y i is the true value of the i-th sample, y i ' is the predicted value of the i-th sample; S302 Adjust hyperparameters of random forest regression model; The hyperparameters include: The number of trees; the maximum depth of the tree; the minimum number of samples required to split a node; the minimum number of samples for a leaf node; the maximum number of features when splitting; the number of random seeds; The above parameters can be adjusted when training a random forest model. For example, the number of trees can be adjusted. The more trees there are, the more stable and generalizable the model will be, but the computational cost will increase. S303 inputs the training data set into the random forest model for training.

6. The parasitic capacitance estimation method based on ensemble learning in the pre-layout stage according to claim 5, characterized in that: The number of trees is 100, the maximum depth of the tree is set to allow the tree to fully expand, the minimum number of samples required to split a node is 2, the minimum number of samples for a leaf node is 1, the maximum number of features at splitting is 7, and the number of random seeds is 42.

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