High-voltage LDO circuit with off-chip capacitor

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a high-voltage LDO (Low Dropout Regulator) circuit with an off-chip capacitor, which comprises an error amplifier EA, a buffer circuit BUFFER, a power tube made of a first P-type DEMOS, an output voltage dividing sampling resistance circuit consisting of a first resistor R1 and a second resistor R2, a floating rail circuit, an enabling circuit and a load capacitor, the floating rail circuit comprises a Zener diode and a third resistor, and a floating low power rail VFLOAT having a stable difference value with the input voltage is provided for the EA and the BUFFER through the reverse bias breakdown voltage of the Zener diode; according to the characteristics of low output impedance and low input parasitic capacitance of the BUFFER circuit, a low-frequency secondary pole composed of an EA high output resistor and a power tube large grid parasitic capacitor is split into two high-frequency poles, and the loop stability of the high-voltage LDO is guaranteed.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a high-voltage LDO circuit with an off-chip capacitor. Background Art

[0002] LDO is a key circuit module in analog integrated circuits. It has excellent characteristics such as small output ripple, low noise, and strong power supply suppression. It can provide stable power supply voltage for other circuits inside the chip. The performance of LDO directly affects the stable operation of the entire chip. As the power supply circuit of the internal power supply of the chip, the requirements for the upper input voltage of LDO are also increasing with the increasing requirements of the input voltage range of power management chips. The upper limit of the input voltage range of traditional LDO is generally low. Therefore, designing an LDO that can work normally under high input voltage is one of the development directions of power management chips. Summary of the invention

[0003] In order to solve the above technical problems, the present invention provides a high-voltage LDO circuit with off-chip capacitors, including: an error amplifier EA, a first resistor R1, a second resistor R2, a third resistor R3, a buffer circuit BUFFER, an enable circuit EN, a first P-type DEMOS tube PDE1, a load capacitor CL1, and a Zener diode DZ1;

[0004] The positive input terminal of the error amplifier EA is connected to the reference voltage VREF, the negative input terminal thereof is connected to the lower end of the first resistor R1 and the upper end of the second resistor R2, the output terminal thereof is connected to the input end of the buffer circuit BUFFER, the high power rail thereof is connected to the input voltage VIN, and the low power rail thereof is connected to the floating power rail VFLOAT;

[0005] The output end of the buffer circuit BUFFER is connected to the gate of the first P-type DEMOS tube PDE1, the high power rail thereof is connected to the input voltage VIN, and the low power rail thereof is connected to the floating power rail VFLOAT;

[0006] The source of the first P-type DEMOS tube PDE1 is connected to the input voltage VIN, and the drain thereof is connected to the output voltage VOUT, the upper end of the first resistor R1 and the upper plate of the load capacitor CL1;

[0007] The lower end of the second resistor R2 and the lower plate of the load capacitor CL1 are grounded GND;

[0008] The upper end of the third resistor R3 is connected to the input voltage VIN, and the lower end thereof is connected to the cathode of the Zener diode DZ1;

[0009] The anode of the Zener diode DZ1 is connected to one end of the enable circuit EN and the floating power rail VFLOAT;

[0010] The other end of the enabling circuit EN is connected to the ground GND.

[0011] Beneficial effects of the present invention:

[0012] The present invention forms a floating power rail by connecting a Zener diode to an input voltage, and then connects an error amplifier circuit and a buffer circuit to the voltage domain of the input voltage to the floating power rail, so that a low-voltage MOS tube in the circuit can operate within the voltage domain, and connects a buffer circuit between the output of the error amplifier and the input of the adjustment tube, so that the loop can maintain normal operation under maximum load conditions.

[0013] The present invention can ensure the normal operation of LDO under different input voltage ranges by adopting a floating rail circuit of a Zener diode, and at the same time ensure the loop stability of LDO by using an NMOS source follower as a buffer circuit; in addition, an enable circuit is added to turn off the error amplifier, buffer and power tube when the LDO enable signal is low, thereby reducing power consumption and eliminating the need for an additional circuit to perform frequency compensation on the LDO circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a structural diagram of a high-voltage LDO circuit with an off-chip capacitor according to the present invention;

[0015] Figure 2 The present invention is a schematic diagram of a high-voltage LDO circuit with an off-chip capacitor. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] A high-voltage LDO circuit with an off-chip capacitor includes: an error amplifier EA, a first resistor R1, a second resistor R2, a third resistor R3, a buffer circuit BUFFER, an enable circuit EN, a first P-type DEMOS tube PDE1, a load capacitor CL1, and a Zener diode DZ1;

[0018] The positive input terminal of the error amplifier EA is connected to the reference voltage VREF, the negative input terminal thereof is connected to the lower end of the first resistor R1 and the upper end of the second resistor R2, the output terminal thereof is connected to the input end of the buffer circuit BUFFER, the high power rail thereof is connected to the input voltage VIN, and the low power rail thereof is connected to the floating power rail VFLOAT;

[0019] The output end of the buffer circuit BUFFER is connected to the gate of the first P-type DEMOS tube PDE1, the high power rail thereof is connected to the input voltage VIN, and the low power rail thereof is connected to the floating power rail VFLOAT;

[0020] The source of the first P-type DEMOS tube PDE1 is connected to the input voltage VIN, and the drain thereof is connected to the output voltage VOUT, the upper end of the first resistor R1 and the upper plate of the load capacitor CL1;

[0021] The lower end of the second resistor R2 and the lower plate of the load capacitor CL1 are grounded GND;

[0022] The upper end of the third resistor R3 is connected to the input voltage VIN, and the lower end thereof is connected to the cathode of the Zener diode DZ1;

[0023] The anode of the Zener diode DZ1 is connected to one end of the enable circuit EN and the floating power rail VFLOAT;

[0024] The other end of the enabling circuit EN is connected to the ground GND.

[0025] Figure 1 A circuit implementation structure diagram of a high-voltage LDO with off-chip capacitors is given, and the circuit includes an error amplifier EA, a buffer circuit BUFFER, a power tube made of a first P-type DEMOS, an output voltage voltage-dividing sampling resistor circuit composed of a first resistor R1 and a second resistor R2, a floating rail circuit, an enabling circuit, and a load capacitor. The floating rail circuit includes a Zener diode and a third resistor, and provides a floating low power rail VFLOAT with a stable difference from the input voltage for EA and BUFFER through the reverse-biased breakdown voltage of the Zener diode; the BUFFER circuit splits the low-frequency pole composed of the high output resistance of EA and the large gate parasitic capacitance of the power tube into two high-frequency poles through its characteristics of low output impedance and low input parasitic capacitance, thereby ensuring the loop stability of the high-voltage LDO.

[0026] Figure 2 A circuit implementation schematic diagram of a high-voltage LDO with off-chip capacitors is given. Figure 1 A specific transistor-level circuit diagram, the circuit comprising:

[0027] The first P-type DEMOS tube;

[0028] an error amplifier EA composed of a first N-type DEMOS tube, a second N-type DEMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a fourth NMOS tube, a fifth NMOS tube, an eleventh NMOS tube, and a twelfth NMOS tube;

[0029] A buffer circuit BUFFER composed of a ninth PMOS tube, a third NMOS tube, and a sixth NMOS tube;

[0030] An enabling circuit EN composed of a third N-type DEMOS tube, a fourth N-type DEMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, and a first inverter;

[0031] An output voltage dividing sampling resistor circuit composed of a first resistor and a second resistor;

[0032] A floating rail circuit consisting of a third resistor and a Zener diode;

[0033] Load capacitance.

[0034] The gate of the first P-type DEMOS tube is connected to the drain of the eighth PMOS tube, the source of the third NMOS tube and the drain of the sixth NMOS tube, the source of the first P-type DEMOS tube is connected to the input voltage VIN, and the drain of the first P-type DEMOS tube is connected to the output voltage VOUT, the upper end of the first resistor and the upper plate of the load capacitor; the gate of the first N-type DEMOS tube is connected to the pre-bias voltage VPRE and the gate of the second N-type DEMOS tube, the source of the first P-type DEMOS tube is connected to the drain of the first NMOS tube, and the drain of the second PMOS tube is connected to the gate of the second N-type DEMOS tube. The gate of the second N-type DEMOS tube is connected to VPRE and the gate of the first N-type DEMOS tube, the source of the second NMOS tube is connected to the drain of the second NMOS tube, and the drain of the third P The gate and drain of the MOS tube and the gate of the fourth PMOS tube and the gate of the fifth PMOS; the gate of the third N-type DEMOS tube is connected to VPRE and the gate of the fourth N-type DEMOS tube, its source is connected to the drain of the ninth NMOS tube, and its drain is connected to the floating power rail VFLOAT; the gate of the fourth N-type DEMOS tube is connected to VPRE and the gate of the third N-type DEMOS tube, its source is connected to the drain of the tenth NMOS tube, and its drain is connected to the gate of the sixth PMOS tube and the gate and drain of the seventh PMOS tube and the gate of the eighth PMOS; the gate of the first PMOS tube is connected to the drain of the first N-type DEMOS tube and the gate and drain of the second PMOS tube, and its source is connected to V IN, its drain is connected to the gate and drain of the fourth NMOS tube and the gate of the fifth NMOS tube and the gate of the sixth NMOS tube; the gate and drain of the second PMOS tube are connected to the drain of the first N-type DEMOS tube and the gate of the first PMOS tube, and its source is connected to VIN; the gate and drain of the third PMOS tube are connected to the drain of the second N-type DEMOS tube and the gate of the fourth PMOS tube and the gate of the fifth PMOS, and its source is connected to VIN; the gate of the fourth PMOS tube is connected to the drain of the second N-type DEMOS tube and the gate and drain of the third PMOS tube and the gate of the fifth PMOS, and its source is connected to VIN, and its drain is connected to the gate of the third NMOS tube and the gate of the fifth NMOS tube drain; the gate of the fifth PMOS tube is connected to the drain of the second N-type DEMOS tube, the gate and drain of the third PMOS tube, and the gate of the fourth PMOS, its source is connected to VIN, and its drain is connected to the gate and drain of the seventh NMOS tube and the gate of the eighth NMOS tube; the gate of the sixth PMOS tube is connected to the drain of the fourth N-type DEMOS, the gate and drain of the seventh PMOS tube, and the gate of the eighth PMOS, its source is connected to VIN, and its drain is connected to the gate of the ninth PMOS tube and the drain of the eighth NMOS tube; the gate and drain of the seventh PMOS tube are connected to the drain of the fourth N-type DEMOS, the gate of the sixth PMOS tube, and the gate of the eighth PMOS, and its source is connected to VIN;The gate of the eighth PMOS is connected to the drain of the fourth N-type DEMOS, the gate of the sixth PMOS tube, and the gate and drain of the seventh PMOS tube, its source is connected to VIN, and its drain is connected to the gate of the first P-type DEMOS tube, the source of the third NMOS tube, and the drain of the sixth NMOS tube; the gate of the ninth PMOS tube is connected to the drain of the sixth PMOS tube and the drain of the eighth NMOS tube, its source is connected to VIN, and its drain is connected to the drain of the third NMOS; the gate of the first NMOS tube is connected to the input reference voltage VREF, its source is connected to the source of the second NMOS tube and the drain of the twelfth NMOS tube, and its drain is connected to the source of the first N-type DEMOS tube; the gate of the second NMOS tube is connected to the feedback sampling The voltage VFB and the lower end of the first resistor and the upper end of the second resistor, the source of which is connected to the source of the first NMOS tube and the drain of the twelfth NMOS tube, and the drain of which is connected to the source of the second N-type DEMOS tube; the gate of the third NMOS tube is connected to the drain of the fourth PMOS tube and the drain of the fifth NMOS tube, the source of which is connected to the gate of the first P-type DEMOS tube, the drain of the eighth PMOS tube and the drain of the sixth NMOS tube, and the drain of which is connected to the drain of the ninth PMOS tube; the gate and drain of the fourth NMOS tube are connected to the drain of the first PMOS tube, the gate of the fifth NMOS tube and the gate of the sixth NMOS tube, and the source of which is connected to VFLOAT; the gate of the fifth NMOS tube is connected to the drain of the first PMOS tube The gate and drain of the fourth NMOS tube and the gate of the sixth NMOS tube, the source of which is connected to VFLOAT, and the drain of which is connected to the drain of the fourth PMOS tube and the gate of the third NMOS tube; the gate of the sixth NMOS tube is connected to the drain of the first PMOS tube, the gate and drain of the fourth NMOS tube and the gate of the fifth NMOS tube, the source of which is connected to VFLOAT, and the drain of which is connected to the source of the third NMOS tube, the gate of the first P-type DEMOS tube and the drain of the eighth PMOS tube; the gate and drain of the seventh NMOS tube are connected to the drain of the fifth PMOS tube and the gate of the eighth PMOS, and the source of which is connected to VFLOAT; the gate of the eighth NMOS tube is connected to the gate and drain of the seventh NMOS tube and the gate of the The drain of the fifth PMOS tube, the source of which is connected to VFLOAT, the drain of which is connected to the drain of the sixth PMOS tube and the gate of the ninth PMOS tube; the gate of the ninth NMOS tube is connected to the enable signal EN and the input end of the first inverter, the source of which is connected to the drain of the thirteenth NMOS tube, and the drain of which is connected to the source of the third N-type DEMOS tube; the gate of the tenth NMOS tube is connected to the output end of the first inverter, the source of which is connected to the drain of the fourteenth NMOS tube, and the drain of which is connected to the source of the fourth N-type DEMOS tube; the gate and drain of the eleventh NMOS tube are connected to the bias current IBIAS and the gate of the twelfth NMOS tube, the gate of the thirteenth NMOS tube, and the gate of the fourteenth NMOS tube, and the source of which is grounded GND;The gate of the twelfth NMOS tube is connected to IBIAS, the gate and drain of the eleventh NMOS tube, the gate of the thirteenth NMOS tube, and the gate of the fourteenth NMOS tube, its source is connected to GND, and its drain is connected to the source of the first NMOS tube and the source of the second NMOS tube; the gate of the thirteenth NMOS tube is connected to IBIAS, the gate and drain of the eleventh NMOS tube, the gate of the twelfth NMOS tube, and the gate of the fourteenth NMOS tube, its source is connected to GND, and its drain is connected to the source of the ninth NMOS tube; the gate of the fourteenth NMOS tube is connected to IBIAS, the gate and drain of the eleventh NMOS tube, the gate of the twelfth NMOS tube, and the gate of the thirteenth NMOS tube, its source is connected to GND, and its drain is connected to the source of the tenth NMOS tube. The source of the MOS tube; the upper end of the first resistor is connected to VOUT, the drain of the first P-type DEMOS tube and the upper plate of the load capacitor, and its lower end is connected to VFB, the gate of the second NMOS tube and the upper end of the second resistor; the upper end of the second resistor is connected to VFB, the gate of the second NMOS tube and the lower end of the first resistor, and its lower end is connected to GND; the upper end of the third resistor is connected to VIN, and its lower end is connected to the cathode of the Zener diode; the anode of the Zener diode is connected to GND, and its cathode is connected to the lower end of the third resistor; the input end of the first inverter is connected to EN and the gate of the ninth NMOS, and its output end is connected to the gate of the tenth NMOS; the upper plate of the load capacitor is connected to VOUT, the upper end of the first resistor and the drain of the first P-type DEMOS tube, and its lower plate is connected to GND.;

[0035] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A high voltage LDO circuit with an off-chip capacitor, characterized in that: include: Error amplifier EA, first resistor R1, second resistor R2, third resistor R3, buffer circuit BUFFER, enable circuit EN, first P-type DEMOS tube PDE1, load capacitor CL1, Zener diode DZ1; The positive input terminal of the error amplifier EA is connected to the reference voltage VREF, the negative input terminal thereof is connected to the lower end of the first resistor R1 and the upper end of the second resistor R2, the output terminal thereof is connected to the input end of the buffer circuit BUFFER, the high power rail thereof is connected to the input voltage VIN, and the low power rail thereof is connected to the floating power rail VFLOAT; The output end of the buffer circuit BUFFER is connected to the gate of the first P-type DEMOS tube PDE1, the high power rail thereof is connected to the input voltage VIN, and the low power rail thereof is connected to the floating power rail VFLOAT; The source of the first P-type DEMOS tube PDE1 is connected to the input voltage VIN, and the drain thereof is connected to the output voltage VOUT, the upper end of the first resistor R1 and the upper plate of the load capacitor CL1; The lower end of the second resistor R2 and the lower plate of the load capacitor CL1 are grounded GND; The upper end of the third resistor R3 is connected to the input voltage VIN, and the lower end thereof is connected to the cathode of the Zener diode DZ1; The anode of the Zener diode DZ1 is connected to one end of the enable circuit EN and the floating power rail VFLOAT; The other end of the enabling circuit EN is connected to the ground GND.

2. A high-voltage LDO circuit with off-chip capacitor according to claim 1, characterized in that: include: The Zener diode DZ1 and the third resistor R3 form a floating rail circuit, and the floating rail circuit provides a floating low power rail VFLOAT having a stable difference with the input voltage for the error amplifier EA and the buffer circuit BUFFER through the reverse bias breakdown voltage of the Zener diode DZ1.

3. A high-voltage LDO circuit with off-chip capacitor according to claim 1, characterized in that: include: The buffer circuit BUFFER splits the low-frequency pole composed of the high output resistance of the error amplifier EA and the large gate parasitic capacitance of the power tube into two high-frequency poles through its characteristics of low output impedance and low input parasitic capacitance, thereby ensuring the loop stability of the high-voltage LDO.

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