Absorption circuit for multi-path parallel flyback switching power supply MOS (Metal Oxide Semiconductor) tube

Abstract

The invention discloses an absorption circuit for a multi-path parallel flyback switching power supply MOS (Metal Oxide Semiconductor) tube, which is used for controlling voltage between a drain electrode and a source electrode of the MOS tube and comprises a first flyback circuit, a second flyback circuit and an absorption circuit, and the first flyback circuit and the second flyback circuit are connected in parallel and are connected to an output end of the absorption circuit; and the high-frequency capacitors C101 and C103 respectively form a loop with the primary side leakage inductance Lm of the transformer in the first flyback circuit and the second flyback circuit, so that the voltage amplitude generated by resonance of the leakage inductance Lm and the parasitic capacitance Coss of the MOS tube is reduced. Meanwhile, fast recovery diodes D102 and D104 are conducted, so that a high-frequency capacitor C102 absorbs voltage energy, a transient voltage suppression diode D101 performs voltage clamping, and terminal voltage of an MOS tube in the flyback circuit is controlled. The circuit is verified by an actual multi-path parallel flyback switching power supply, the work is stable and reliable, the stress control effect of the MOS tube is good, and the cost is relatively low.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supply circuits, and particularly relates to a snubber circuit for a MOS transistor of a multi-parallel flyback switching power supply. Background Art

[0002] When a flyback switching power supply operates, the flyback MOS transistor is in a state of high-frequency repeated on and off switching. Due to the existence of the leakage inductance Lm of the flyback transformer and the parasitic capacitance of the MOS transistor, the on and off state switching of the flyback MOS transistor will cause a large VDS voltage (the sum of the bus voltage, the secondary emission voltage, and the transformer leakage inductance spike voltage), which is very likely to exceed the maximum voltage that the flyback MOS transistor itself can withstand, resulting in breakdown and damage of the flyback MOS transistor. At the same time, the stress spikes caused by the high-frequency switching state switching will generate strong noise pollution, forming electromagnetic interference that affects the operation of the whole machine.

[0003] The snubber circuits of traditional flyback switching power supplies each set a corresponding snubber circuit for each branch MOS transistor, and all use RCD snubbing. This RCD snubber circuit will cause a large power consumption and affect the working efficiency of the circuit. At the same time, each branch has a corresponding snubber circuit, which will result in a large PCB layout space and high cost. Summary of the Invention

[0004] In view of this, it is necessary to provide a snubber circuit for a MOS transistor of a multi-parallel flyback switching power supply with a small PCB layout space, low cost, and low power consumption.

[0005] A snubber circuit for a MOS transistor of a multi-parallel flyback switching power supply, used to control the voltage between the drain and source of the MOS transistor, includes a first flyback circuit, a second flyback circuit, and a snubber circuit. The first flyback circuit and the second flyback circuit are connected in parallel and connected to the output end of the snubber circuit; the first flyback circuit and the second flyback circuit each include a transformer and a MOS transistor connected in series. The snubber circuit includes a fast recovery diode, a high-frequency capacitor, and a transient voltage suppression diode. When the MOS transistors in the first flyback circuit and the second flyback circuit are turned off, the drain voltage of the MOS transistor charges the high-frequency capacitor through the fast recovery diode. The high-frequency capacitor absorbs energy. When the voltage of the high-frequency capacitor is full and the voltage continues to rise to reach the clamping voltage of the transient voltage suppression diode, the transient voltage suppression diode clamps the voltage between the drain and source of the MOS transistor within a predetermined range.

[0006] Preferably, the first flyback circuit includes a first transformer T1, a first MOS transistor Q1, a first Schottky diode D103, and a first electrolytic capacitor CE1; a first end of the primary side T1-A of the first transformer T1 is connected to the circuit input terminal VDC, a second end of the primary side T1-A of the first transformer T1 is connected to the drain of the first MOS transistor Q1, and the source of the first MOS transistor Q1 is grounded to GND; a first end of the secondary side T1-B of the first transformer T1 is connected to the anode of the first Schottky diode D103, the cathode of the first Schottky diode D103 is connected to the positive electrode of the first electrolytic capacitor CE1, and a second end of the secondary side T1-B of the first transformer T1 is connected to the negative electrode of the first electrolytic capacitor CE1; the positive electrode of the first electrolytic capacitor CE1 is connected to the output terminal OUT1 of the first flyback circuit, and the negative electrode of the first electrolytic capacitor CE1 is grounded to GND.

[0007] Preferably, the second flyback circuit includes a second transformer T2, a second MOS transistor Q2, a second Schottky diode D105, and a second electrolytic capacitor CE2; a first end of the primary side T2-A of the second transformer T2 is connected to the circuit input terminal VDC, a second end of the primary side T2-A of the second transformer T2 is connected to the drain of the second MOS transistor Q2, and the source of the second MOS transistor Q2 is grounded to GND; a second end of the secondary side T2-B of the second transformer T2 is connected to the anode of the second Schottky diode D105, the cathode of the second Schottky diode D105 is connected to the positive electrode of the second electrolytic capacitor CE2, and a second end of the secondary side T2-B of the second transformer T2 is connected to the negative electrode of the second electrolytic capacitor CE2; the positive electrode of the second electrolytic capacitor CE2 is connected to the output terminal OUT2 of the second flyback circuit, and the negative electrode of the second electrolytic capacitor CE2 is grounded to GND.

[0008] Preferably, the absorption circuit includes a transient voltage suppression diode D101, a first high-frequency capacitor C101, a second high-frequency capacitor C102, a third high-frequency capacitor C103, a first fast-recovery diode D102, a second fast-recovery diode D104, and a bead inductor L101; both ends of the first high-frequency capacitor C101 are connected in parallel to both ends of the primary side T1-A of the first transformer T1, and the connection point between the first high-frequency capacitor C101, the second end of the primary side T1-A of the first transformer T1, and the drain of the first MOS transistor Q1 is connected to the anode of the first fast-recovery diode D102; both ends of the third high-frequency capacitor C103 are connected in parallel to both ends of the primary side T2-A of the second transformer T2, and the connection point between the third high-frequency capacitor C103, the second end of the primary side T2-A of the second transformer T2, and the drain of the second MOS transistor Q2 is connected to the anode of the second fast-recovery diode D104; the cathode of the first fast-recovery diode D102 is connected to the cathode of the second fast-recovery diode D104 and is simultaneously connected to the first end of the second high-frequency capacitor C102, and the second end of the second high-frequency capacitor C102 is grounded to GND; the anode of the transient voltage suppression diode D101 is connected to the circuit input terminal VDC, and the cathode of the transient voltage suppression diode D101 is connected to the connection point between the cathode of the first fast-recovery diode D102, the cathode of the second fast-recovery diode D104, and the first end of the second high-frequency capacitor C102 through the bead inductor L101.

[0009] In the above absorption circuit for the MOS transistors of the multi-path parallel flyback switching power supply, the high-frequency capacitors C101 and C103 respectively form loops with the primary side leakage inductance Lm of the transformers in the first flyback circuit and the second flyback circuit, reducing the voltage amplitude generated by the resonance of the leakage inductance Lm and the MOS transistor parasitic capacitance Coss. At the same time, the fast-recovery diodes D102 and D104 conduct, enabling the high-frequency capacitor C102 to absorb voltage energy, and the transient voltage suppression diode D101 performs voltage clamping to control the terminal voltage of the MOS transistor in the flyback circuit. In this technical solution, only one transient voltage suppression diode, high-frequency capacitor, and fast-recovery diode effectively solve the problem of MOS transistor voltage stress in the multi-path parallel flyback switching power supply. The circuit is verified by an actual multi-path parallel flyback switching power supply, operates stably and reliably, has a good MOS transistor stress control effect, and has a low cost. The circuit structure of the present invention is simple, easy to implement, has a low cost, and is convenient for popularization. Description of the Drawings

[0010] Figure 1 It is a schematic structural diagram of the absorption circuit for the MOS transistors of the multi-path parallel flyback switching power supply in an embodiment of the present invention.

[0011] Figure 2It is a schematic diagram of the current direction when the MOS transistor in the absorption circuit of the MOS transistor of the multi-parallel flyback switching power supply in the embodiment of the present invention is conducting.

[0012] Figure 3 It is a schematic diagram of the current direction when the MOS transistor in the absorption circuit of the MOS transistor of the multi-parallel flyback switching power supply in the embodiment of the present invention is turned off. Specific embodiments

[0013] In this embodiment, taking the absorption circuit of the MOS transistor of the multi-parallel flyback switching power supply as an example, the present invention will be described in detail below in conjunction with specific embodiments and drawings.

[0014] Please refer to Figure 1 、 Figure 2 and Figure 3 , which shows an absorption circuit for the MOS transistor of a multi-parallel flyback switching power supply provided by an embodiment of the present invention, used to control the voltage between the drain and source of the MOS transistor, including a first flyback circuit, a second flyback circuit, and an absorption circuit. The first flyback circuit and the second flyback circuit are connected in parallel and connected to the output end of the absorption circuit; the first flyback circuit and the second flyback circuit respectively include a transformer and a MOS transistor connected in series. The absorption circuit includes a fast recovery diode, a high-frequency capacitor, and a transient voltage suppression diode. When the MOS transistors in the first flyback circuit and the second flyback circuit are turned off, the drain voltage of the MOS transistor charges the high-frequency capacitor through the fast recovery diode, and the high-frequency capacitor absorbs energy. When the voltage of the high-frequency capacitor is full and the voltage continues to rise to reach the clamping voltage of the transient voltage suppression diode, the transient voltage suppression diode clamps the voltage between the drain and source of the MOS transistor within a predetermined range.

[0015] Preferably, the first flyback circuit includes a first transformer T1, a first MOS transistor Q1, a first Schottky diode D103, and a first electrolytic capacitor CE1; the first end of the primary side T1-A of the first transformer T1 is connected to the circuit input terminal VDC, the second end of the primary side T1-A of the first transformer T1 is connected to the drain of the first MOS transistor Q1, and the source of the first MOS transistor Q1 is grounded to GND; the first end of the secondary side T1-B of the first transformer T1 is connected to the anode of the first Schottky diode D103, the cathode of the first Schottky diode D103 is connected to the positive electrode of the first electrolytic capacitor CE1, and the second end of the secondary side T1-B of the first transformer T1 is connected to the negative electrode of the first electrolytic capacitor CE1; the positive electrode of the first electrolytic capacitor CE1 is connected to the output terminal OUT1 of the first flyback circuit, and the negative electrode of the first electrolytic capacitor CE1 is grounded to GND.

[0016] Preferably, the second flyback circuit includes a second transformer T2, a second MOS transistor Q2, a second Schottky diode D105, and a second electrolytic capacitor CE2; a first end of the primary side T2-A of the second transformer T2 is connected to the circuit input terminal VDC, a second end of the primary side T2-A of the second transformer T2 is connected to the drain of the second MOS transistor Q2, and the source of the second MOS transistor Q2 is grounded to GND; a second end of the secondary side T2-B of the second transformer T2 is connected to the anode of the second Schottky diode D105, the cathode of the second Schottky diode D105 is connected to the positive electrode of the second electrolytic capacitor CE2, and a second end of the secondary side T2-B of the second transformer T2 is connected to the negative electrode of the second electrolytic capacitor CE2; the positive electrode of the second electrolytic capacitor CE2 is connected to the output terminal OUT2 of the second flyback circuit, and the negative electrode of the second electrolytic capacitor CE2 is grounded to GND.

[0017] Preferably, the absorption circuit includes a transient voltage suppression diode D101, a first high-frequency capacitor C101, a second high-frequency capacitor C102, a third high-frequency capacitor C103, a first fast-recovery diode D102, a second fast-recovery diode D104, and a bead inductor L101; both ends of the first high-frequency capacitor C101 are connected in parallel across both ends of the primary side T1-A of the first transformer T1, and a connection point between the first high-frequency capacitor C101, the second end of the primary side T1-A of the first transformer T1, and the drain of the first MOS transistor Q1 is connected to the anode of the first fast-recovery diode D102; both ends of the third high-frequency capacitor C103 are connected in parallel across both ends of the primary side T2-A of the second transformer T2, and a connection point between the third high-frequency capacitor C103, the second end of the primary side T2-A of the second transformer T2, and the drain of the second MOS transistor Q2 is connected to the anode of the second fast-recovery diode D104; the cathode of the first fast-recovery diode D102 is connected to the cathode of the second fast-recovery diode D104 and is simultaneously connected to the first end of the second high-frequency capacitor C102, and the second end of the second high-frequency capacitor C102 is grounded to GND; the anode of the transient voltage suppression diode D101 is connected to the circuit input terminal VDC, and the cathode of the transient voltage suppression diode D101 is connected to a connection point between the cathode of the first fast-recovery diode D102, the cathode of the second fast-recovery diode D104, and the first end of the second high-frequency capacitor C102 through the bead inductor L101.

[0018] When the circuit is operating, when the first MOS transistor Q1 and the second MOS transistor Q2 are turned on, the cathode voltage of the transient voltage suppression diode D101 is substantially the same as the bus voltage; the first fast-recovery diode D102 and the second fast-recovery diode D104 are turned off. At this time, the current direction in the circuit is asFigure 2 as shown

[0019] When the first MOS transistor Q1 and the second MOS transistor Q2 are turned off, since the VDS voltage of the MOS transistor cannot change suddenly, the current will charge the parasitic capacitance Coss at both ends of the MOS transistor. At this time, the parasitic capacitance Coss at both ends of the MOS transistor resonates with the leakage inductance Lm of the transformer, resulting in a VDS spike voltage across the MOS transistor.

[0020] At this time, under the action of the absorption circuit, the first high-frequency capacitor C101 and the third high-frequency capacitor C103 respectively form a loop with the leakage inductance Lm of the primary side T1-A of the first transformer T1 and the primary side T2-A of the second transformer T2, reducing the energy of the leakage inductance Lm, thereby reducing the voltage amplitude generated by the resonance of the leakage inductance Lm and the MOS transistor parasitic capacitance Coss. At the same time, the first fast-recovery diode D102 and the second fast-recovery diode D104 are respectively turned on, so that the second high-frequency capacitor C102 can absorb voltage energy. When the voltage reaches the operating voltage of the transient voltage suppression diode D101, the transient voltage suppression diode D101 acts to achieve voltage clamping, clamping the voltage to the sum of the bus voltage and the operating voltage of the transient voltage suppression diode D101, thereby controlling the voltage stress of the flyback MOS transistor. At this time, the current direction in the circuit is as Figure 3 as shown

[0021] In the above absorption circuit for the MOS transistors of the multi-path parallel flyback switching power supply, the high-frequency capacitors C101 and C103 respectively form a loop with the primary-side leakage inductance Lm of the transformers in the first flyback circuit and the second flyback circuit, reducing the voltage amplitude generated by the resonance of the leakage inductance Lm and the MOS transistor parasitic capacitance Coss. At the same time, the fast-recovery diodes D102 and D104 are turned on, so that the high-frequency capacitor C102 absorbs voltage energy, and the transient voltage suppression diode D101 performs voltage clamping to control the terminal voltage of the MOS transistor in the flyback circuit. In this technical solution, only one transient voltage suppression diode, high-frequency capacitor, and fast-recovery diode effectively solve the problem of the voltage stress of the MOS transistors in the multi-path parallel flyback switching power supply. The circuit is verified by an actual multi-path parallel flyback switching power supply, and it works stably and reliably, has a good MOS transistor stress control effect, and a low cost. The circuit structure of the present invention is simple, easy to implement, low in cost, and convenient for popularization.

[0022] It should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An absorption circuit for a multi-channel parallel flyback switching power supply MOS tube, used for controlling the voltage between the drain and the source of the MOS tube, comprising a first flyback circuit, a second flyback circuit and an absorption circuit, wherein the first flyback circuit and the second flyback circuit are connected in parallel and connected to the output end of the absorption circuit; the first flyback circuit and the second flyback circuit respectively comprise a transformer and a MOS tube connected in series, the absorption circuit comprises a fast recovery diode, a high-frequency capacitor and a transient voltage suppression diode, when the MOS tubes in the first flyback circuit and the second flyback circuit are turned off, the drain voltage of the MOS tube charges the high-frequency capacitor through the fast recovery diode, the high-frequency capacitor absorbs energy, the high-frequency capacitor voltage is fully charged, and when the voltage continues to rise and reaches the clamping voltage of the transient voltage suppression diode, the transient voltage suppression diode clamps the voltage between the drain and the source of the MOS tube within a predetermined range.

2. The absorption circuit for multi-channel parallel flyback switching power supply MOS tubes as claimed in claim 1, characterized in that: The first flyback circuit includes a first transformer T1, a first MOS transistor Q1, a first Schottky diode D103 and a first electrolytic capacitor CE1; a first end of the primary side T1-A of the first transformer T1 is connected to a circuit input end VDC, a second end of the primary side T1-A of the first transformer T1 is connected to a drain of the first MOS transistor Q1, and a source of the first MOS transistor Q1 is grounded GND; a first end of the secondary side T1-B of the first transformer T1 is connected to an anode of the first Schottky diode D103, a cathode of the first Schottky diode D103 is connected to a positive electrode of the first electrolytic capacitor CE1, and a second end of the secondary side T1-B of the first transformer T1 is connected to a negative electrode of the first electrolytic capacitor CE1; a positive electrode of the first electrolytic capacitor CE1 is connected to an output end OUT1 of the first flyback circuit, and a negative electrode of the first electrolytic capacitor CE1 is grounded GND.

3. The absorption circuit for multi-channel parallel flyback switching power supply MOS tubes as claimed in claim 2, characterized in that: The second flyback circuit includes a second transformer T2, a second MOS transistor Q2, a second Schottky diode D105 and a second electrolytic capacitor CE2; a first end of the primary side T2-A of the second transformer T2 is connected to the circuit input terminal VDC, a second end of the primary side T2-A of the second transformer T2 is connected to the drain of the second MOS transistor Q2, and a source of the second MOS transistor Q2 is grounded GND; a second end of the secondary side T2-B of the second transformer T2 is connected to the anode of the second Schottky diode D105, a cathode of the second Schottky diode D105 is connected to the positive electrode of the second electrolytic capacitor CE2, and a second end of the secondary side T2-B of the second transformer T2 is connected to the negative electrode of the second electrolytic capacitor CE2; the positive electrode of the second electrolytic capacitor CE2 is connected to the output terminal OUT2 of the second flyback circuit, and the negative electrode of the second electrolytic capacitor CE2 is grounded GND.

4. The absorption circuit for multi-channel parallel flyback switching power supply MOS tubes as claimed in claim 3, characterized in that: The absorption circuit includes a transient voltage suppression diode D101, a first high-frequency capacitor C101, a second high-frequency capacitor C102, a third high-frequency capacitor C103, a first fast recovery diode D102, a second fast recovery diode D104, and a magnetic bead inductor L101; the two ends of the first high-frequency capacitor C101 are connected in parallel to the two ends of the primary side T1-A of the first transformer T1, and the connection point between the first high-frequency capacitor C101 and the second end of the primary side T1-A of the first transformer T1 and the drain of the first MOS tube Q1 is connected to the anode of the first fast recovery diode D102; the two ends of the third high-frequency capacitor C103 are connected in parallel to the two ends of the primary side T2-A of the second transformer T2, and the third high-frequency capacitor C103 and the second transformer T2 are connected to the anode of the first fast recovery diode D102. The connecting point between the second end of the primary side T2-A of the transistor T2 and the drain of the second MOS transistor Q2 is connected to the anode of the second fast recovery diode D104; the cathode of the first fast recovery diode D102 is connected to the cathode of the second fast recovery diode D104, and is also connected to the first end of the second high-frequency capacitor C102, and the second end of the second high-frequency capacitor C102 is grounded GND; the anode of the transient voltage suppression diode D101 is connected to the circuit input terminal VDC, and the cathode of the transient voltage suppression diode D101 is connected to the cathode of the first fast recovery diode D102, the cathode of the second fast recovery diode D104 and the connecting point between the first end of the second high-frequency capacitor C102 through the magnetic bead inductor L101.

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