System and method for automatically recording reasons for abnormal restart of CPU (Central Processing Unit) and storing logs and data

Abstract

The invention provides a system and a method for automatically recording CPU abnormal restart reasons and storing logs and data, the system comprises a reset trigger module, a reset reason recording module, a data and log recording module and a reset execution module, each module circuit uses a discrete device, an FPGA or CPLD chip does not need to be used, the cost is saved, and the system reliability is improved. According to the method, restart reasons which can be automatically recorded comprise the condition of active restart or passive restart caused by program exception, the condition of manual operation of a reset key and the condition of sudden temporary failure of a power supply, and meanwhile, important data, state information and log information can be quickly stored through a memory by a CPU (Central Processing Unit) through a design mechanism before restart; and after restarting, the data is transferred to the nonvolatile storage device, so that data loss is prevented, and deep reasons of abnormal restarting can be further analyzed.

Description

Technical Field

[0001] The present invention belongs to the field of CPU system exception protection, and particularly relates to a method for automatically recording the reasons for abnormal CPU restarts and effectively saving restart logs and important data. Background Art

[0002] With the progress of technology, the CPU systems of highly reliable devices such as relay protection devices, switches, and battery system management units are becoming increasingly complex. During the long-term operation of the devices, after the CPU system experiences an abnormal restart due to accidental factors, it is very difficult to reproduce the same problem subsequently, which brings difficulties to the equipment manufacturer in analyzing the problem causes and subsequent optimization.

[0003] Currently, there are some methods for auxiliary monitoring or control of the CPU through FPGA or CPLD. However, on the one hand, these methods introduce incremental costs, and on the other hand, the monitoring program itself also has a probability of problems in theory, which reduces the stability of the entire system to a certain extent. And it is very difficult for external monitoring to timely obtain and save the key information inside the CPU. There is an urgent need for an external circuit to reliably and automatically record the reasons for reset when the CPU restarts, and at the same time, through a designed mechanism, the CPU itself can try to "protect the scene" and quickly save important data or log information. On the one hand, it can prevent the loss of important data, and on the other hand, it helps to further analyze the reasons for abnormal restarts subsequently. Summary of the Invention

[0004] To solve the deficiencies in the prior art, the present invention provides a system method for automatically recording the reasons for abnormal CPU restarts and saving restart logs and important data.

[0005] The present invention adopts the following technical solutions. In the first aspect of the present invention, a system for automatically recording the reasons for abnormal CPU restarts and effectively saving restart logs and important data is provided, which is characterized by including: a reset trigger module, a reset reason recording module, a data and log recording module, and a reset execution module;

[0006] When the CPU system is running normally, the CPU regularly writes the set content into the memory unit or non-volatile storage unit of the data and log recording module; when the CPU system runs abnormally, the reset trigger module is used to provide an interrupt signal exclusive to the program exception event and / or an interrupt signal exclusive to the reset button event, and send them to the CPU, the reset reason recording set module, and the reset execution module; the reset trigger module also provides a power supply monitoring reset signal and sends it to the reset reason recording set module and the reset execution module;

[0007] The reset reason recording module records the reset reason according to the interrupt signal or the power supply monitoring reset signal;

[0008] The reset execution module performs a delay reset function when triggered by an interrupt signal, delaying the CPU reset time; if the CPU can still respond to the interrupt signal, the interrupt signal triggers the data and log recording module to work, and during the delay reset period, the set content is saved to the memory and / or non-volatile storage unit in real time; if the CPU can no longer respond to the interrupt signal, the interrupt signal does not trigger the data and log recording module to work, and the CPU waits to restart immediately after the delay reset ends, and the set content is saved by the last regular save operation before the exception occurs; the reset execution module performs an immediate restart operation of the CPU when triggered by a power monitoring reset signal.

[0009] Preferably, the reset trigger module includes: a reset button circuit, a watchdog circuit, and a power monitoring circuit;

[0010] The output end of the reset button circuit is the first output end of the reset trigger module, and is respectively connected to the first input end of the reset reason recording module, the first input end of the reset execution module, and the CPU;

[0011] The input end of the watchdog circuit is the input end of the reset trigger module, which is used to receive the dog feeding signal output by the CPU to the watchdog on time. The output end of the watchdog circuit is the second output end of the reset trigger module, and is respectively connected to the second input end of the reset reason recording module, the first input end of the reset execution module, and the CPU;

[0012] The output end of the power monitoring circuit is the third output end of the reset trigger module, and is connected to the third input end of the reset reason recording module and the second input end of the reset execution module.

[0013] Preferably, the reset button circuit includes a tri-state gate device, so that its signal output is an open-drain output; the reset signal output of the watchdog chip is an open-drain output; the watchdog reset signal and the reset button signal are in wired-AND logic and are connected to the first input end of the reset execution module. When any signal is at a low level, the result is at a low level;

[0014] The POWERGOOD signals of the multi-channel power chips are in wired-AND logic to generate a power monitoring reset signal. When any one of the power supplies has an abnormality, the power monitoring reset signal can be triggered to change from a high level to a low level.

[0015] Preferably, the reset reason recording module includes: at least three flip-flop circuits and the corresponding number of inverters;

[0016] The input end of the first inverter is connected to the output end of the power monitoring circuit of the reset trigger module. The output end of the first inverter is connected to the CP end of the first flip-flop. The Q end of the first flip-flop is connected to the CPU;

[0017] The input terminal of the second inverter is connected to the output terminal of the watchdog circuit of the reset trigger module. The output terminal of the second inverter is connected to the CP terminal of the second flip-flop. The Q terminal of the second flip-flop is connected to the CPU.

[0018] The input terminal of the third inverter is connected to the output terminal of the reset button circuit of the reset trigger module. The output terminal of the third inverter is connected to the CP terminal of the third flip-flop. The Q terminal of the third flip-flop is connected to the CPU.

[0019] Preferably, the data and log recording module includes: a memory unit, a fourth flip-flop, and a non-volatile storage unit.

[0020] In the normal operating state after each startup of the CPU, first set the memory controller to automatically enter the self-refresh state when it detects that the memory is in the idle state.

[0021] The CP terminal of the fourth flip-flop is connected to the CPU. The Q terminal is logically ORed with the reset signal of the CPU for the memory and then sent to the memory reset input terminal.

[0022] Preferably, the reset execution module includes: a delay reset circuit and a normal reset circuit.

[0023] The input terminal of the delay reset circuit is the first input terminal of the reset execution module and is connected to the output terminal of the watchdog circuit and the output terminal of the reset button circuit. The output terminal of the delay reset circuit is connected to the input terminal of the normal reset circuit, and the input terminal of the normal reset circuit is the second input terminal of the reset execution module.

[0024] Preferably, the delay reset signal and the power supply monitoring reset signal are in wire-AND logic. When any signal is at a low level, the result is low. When the delay reset signal changes from high to low or the power supply monitoring reset signal changes from high to low at the end of the delay, it will trigger the normal reset circuit to act and immediately reset the CPU.

[0025] The second aspect of the present invention provides a method for automatically recording the reasons for abnormal restart of the CPU and effectively saving the restart log and important data. Based on the system for automatically recording the reasons for abnormal restart of the CPU and effectively saving the restart log and important data, it includes the following steps:

[0026] Step 1, the CPU starts and maintains the normal operating state. The CPU regularly outputs a watchdog feeding signal to the watchdog and regularly writes the set content into the memory and / or the non-volatile storage unit.

[0027] Step 2: Determine whether a reset event occurs. If no reset event occurs, return to Step 1, where the CPU continues to output a watchdog feeding signal on time and periodically writes the set content into the memory or non-volatile storage unit. If a reset event occurs, continue to determine whether the reset source is power monitoring. If the reset is caused by power monitoring, execute Step 4; otherwise, execute Step 3.

[0028] Step 3: The reset trigger module provides an interrupt signal exclusive to the program exception event and / or an interrupt signal exclusive to the reset button event, and sends them to the CPU, the reset cause record set module, and the reset execution module. The CPU responds or does not respond to the interrupt signal according to the degree of exception. The reset cause record set module records the reset cause, and the reset execution module executes the delayed reset function under the trigger of the interrupt signal, delaying the CPU reset time. If the CPU can still respond to the interrupt signal, the interrupt signal triggers the data and log record module to work, and during the delayed reset period, the set content is saved to the memory and / or non-volatile storage unit in real time. If the CPU can no longer respond to the interrupt signal, the interrupt signal does not trigger the data and log record module to work, and the CPU waits to restart immediately after the delayed reset ends. The set content is saved by the last regular save operation before the exception occurs.

[0029] Step 4: The reset execution module executes the operation of immediately restarting the CPU under the trigger of the power monitoring reset signal. The set content is saved by the last regular save operation before the exception occurs.

[0030] Preferably, Step 1 includes:

[0031] Step 1.1: When the CPU starts, whether it is a cold start or a warm start, make the memory exit the self-refresh state and enter the auto-refresh state, and the CPU provides a refresh command for the memory.

[0032] Step 1.2: The CPU reads the output value of the trigger in the reset cause record module, saves the result to a memory variable, records it as the reset cause information for other modules in the program to call, and resets the trigger in the reset cause record module to the initial state for use in the next reset.

[0033] Step 1.3: According to the result of Step 1.2, the CPU writes the set content into the data and log record module according to whether this start is a cold start or a warm start for future retrieval and analysis.

[0034] Step 1.4: The CPU starts and maintains a normal running state. The CPU outputs a watchdog feeding signal on time and periodically writes the set content into the data and log record module.

[0035] Preferably, Step 3 includes Step 3.A and Step 3.B that occur almost simultaneously and have no sequential logical order.

[0036] Step 3.A, when the watchdog reset signal changes from high level to low level, it will provide an interrupt signal exclusive to the program exception event for the CPU; or when the key reset signal changes from high level to low level, it will provide an interrupt signal exclusive to the reset key event for the CPU.

[0037] Step 3.B, the watchdog reset signal and the reset key signal in the reset trigger module are in wired-AND logic. When any signal is at low level, the result is low level, triggering the delay reset circuit in the reset execution module to start delay reset.

[0038] Compared with the prior art, the beneficial effects of the present invention at least include: the reset trigger module, the reset reason recording module, the data and log recording module, and the reset execution module circuits all use discrete devices, without the need to use FPGA or CPLD chips, saving costs and improving system reliability. The present invention can automatically record the reasons for restarting, including: the situation of active or passive restart caused by program exception, the situation of manually operating the reset key, and the situation of sudden temporary power failure. At the same time, through the designed mechanism, the CPU can quickly save important data, status information, and log information through the memory before restarting, and transfer the above data to the non-volatile storage device after restarting to prevent data loss, and is helpful for further analyzing the deep reasons for abnormal restart. Description of the Drawings

[0039] Figure 1 is the schematic diagram of the method for automatically recording the reasons for abnormal restart of the CPU and saving the restart log and important data in the present invention;

[0040] Figure 2 is the flowchart of the method for automatically recording the reasons for abnormal restart of the CPU and saving the restart log and important data in the present invention. Detailed Embodiment

[0041] To make the purpose, technical solution, and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. The embodiments described in this application are only a part of the embodiments of the present invention, not all embodiments. Based on the spirit of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0042] As Figure 1 shown, Embodiment 1 of the present invention provides a system for automatically recording the reasons for abnormal restart of the CPU and saving the restart log and important data, including: a reset trigger module, a reset reason recording module, a data and log recording module, and a reset execution module.

[0043] When the CPU system is running normally, the CPU periodically writes relevant important data, status information, log information, etc. into the memory unit or non-volatile storage unit of the data and log recording module. When the CPU system runs abnormally, the reset trigger module is used to provide an interrupt signal exclusive to the program exception event and an interrupt signal exclusive to the reset button event, and send them to the CPU, the reset reason recording set module, and the reset execution module; the reset trigger module also provides a power monitoring reset signal and sends it to the reset reason recording set module and the reset execution module.

[0044] The reset reason recording module records the reset reason according to the interrupt signal or the power monitoring reset signal.

[0045] The interrupt signal triggers the delayed reset function of the reset execution module, delaying the CPU reset time; if the degree of CPU program exception is relatively light and the CPU can still respond to the interrupt signal, it can have the ability to save important data and log information, that is, the interrupt signal will trigger the data and log recording module to start working. During the delayed reset period, the data and log recording module can save important data, status information, log information, etc. to the memory and non-volatile storage unit in real time. If the degree of CPU program exception is relatively serious and the CPU can no longer respond to the interrupt signal, the data and log recording module will not be triggered, and the CPU will quietly wait for a restart. And the relevant important data, status information, log information, etc. can be properly saved by the last regular save operation before the exception occurs. After the delayed reset ends, the CPU is immediately reset. The reset execution module performs an immediate restart operation of the CPU when triggered by the power monitoring reset signal.

[0046] The reset trigger module includes: a reset button circuit, a watchdog circuit, and a power monitoring circuit.

[0047] The output end of the reset button circuit is the first output end of the reset trigger module, and is respectively connected to the first input end of the reset reason recording module, the first input end of the reset execution module, and the CPU;

[0048] The reset button circuit generates and outputs a button reset signal. When a human operation presses the reset button, the button reset signal changes from high level to low level. It should be noted that the button reset signal changing from high to low provides an interrupt signal exclusive to the reset button event for the reset reason recording module, the reset execution module, and the CPU respectively. That is, after the button is pressed, the falling edge generated by the level changing from high to low is the interrupt signal. After the CPU captures the falling edge, it triggers an interrupt event. Furthermore, the reset reason recording module records the CPU restart action caused by the reset button being pressed manually, and the reset execution module triggers the delayed reset function to delay the CPU reset time.

[0049] Preferably, the reset button circuit should include a tri-state gate device so that its signal output is an open-drain output.

[0050] The input end of the watchdog circuit is the input end of the reset trigger module, which is used to receive the dog-feeding signal output by the CPU on time to the watchdog. The output end of the watchdog circuit is the second output end of the reset trigger module, which is respectively connected to the second input end of the reset cause recording module, the first input end of the reset execution module, and the CPU.

[0051] The watchdog circuit receives the dog-feeding signal output by the CPU on time and generates a watchdog reset signal. A high level of the watchdog reset signal indicates that the CPU is running normally, and a low level indicates that the CPU program has an exception, resulting in an active restart or a passive restart. Specifically, when the CPU program has an exception and causes an active restart or a passive restart, the CPU will stop outputting the dog-feeding signal to the watchdog, the watchdog timing will time out, and the watchdog reset signal will change from a high level to a low level. It should be noted that when the watchdog reset signal changes from high to low, it provides an interrupt signal exclusive to the program exception event for the reset cause recording module, the reset execution module, and the CPU respectively. Furthermore, the reset cause recording module records the CPU restart action caused by the exception of the CPU program, and the reset execution module triggers the delay reset function to postpone the CPU reset time.

[0052] Preferably, the reset signal output of the watchdog chip should be an open-drain output.

[0053] During the delay reset period, if the degree of the CPU program exception is relatively light and it can still respond to the interrupt signal, it can have the ability to save important data and log information. The interrupt signal exclusive to the reset button event or the program exception event will trigger the data and log recording module to start working, and can save important data, status information, log information, etc. in real time. If the degree of the CPU program exception is relatively serious and it can no longer respond to the interrupt signal, the data and log recording module will not be triggered, and the CPU will wait quietly for restart. And the relevant important data, status information, log information, etc. can be properly saved by the last regular save operation before the exception occurs. After the delay reset ends, the CPU is immediately reset.

[0054] Preferably, during the reset delay period, the CPU needs to write the required important data, status information, and log information into the memory within a limited delay period for analysis or transfer to a non-volatile memory after restart. If the data volume is small and time permits, it can also write and save to non-volatile memories such as EEPROM, NOR FLASH, NAND FLASH, eMMC, SSD at the same time.

[0055] Preferably, the CPU should enable DMA to perform write operations to multiple memories simultaneously.

[0056] The watchdog reset signal and the reset button signal in the reset trigger module are in wired-AND logic and are connected to the first input terminal of the reset execution module. When any signal is at a low level, the result is at a low level. Therefore, when the button reset signal or the watchdog reset signal changes from a high level to a low level, it will trigger the reset execution module to start the delay reset.

[0057] The output terminal of the power monitoring circuit is the third output terminal of the reset trigger module and is connected to the third input terminal of the reset reason recording module and the second input terminal of the reset execution module; the power monitoring circuit generates and outputs a power monitoring reset signal. The power monitoring circuit performs real-time detection on each power supply of the board. When a certain power supply fails and is detected by the power monitoring circuit, the power monitoring reset signal changes from a high level to a low level. It should be noted that when the power monitoring reset signal changes from high to low, it provides corresponding trigger signals for the reset reason recording module and the reset execution module respectively. Furthermore, the reset reason recording module forms a record of the power supply failure situation, and the reset execution module does not trigger the delay reset function but directly triggers the normal reset function, so that the CPU is immediately reset to prevent the CPU from performing unexpected operations in the power abnormal state.

[0058] Preferably, the power monitoring reset signal can be realized by the wired-AND logic of the POWERGOOD signals of multiple power supply chips. When any one of the power supplies is abnormal, it can trigger the power monitoring reset signal to change from a high level to a low level.

[0059] The reset reason recording module includes: at least three trigger circuits and the corresponding number of inverters. Specifically,

[0060] The input terminal of the first inverter is connected to the output terminal of the power monitoring circuit of the reset trigger module. The output terminal of the first inverter is connected to the CP terminal of the first trigger. The Q terminal of the first trigger is connected to the CPU;

[0061] The input terminal of the second inverter is connected to the output terminal of the watchdog circuit of the reset trigger module. The output terminal of the second inverter is connected to the CP terminal of the second trigger. The Q terminal of the second trigger is connected to the CPU;

[0062] The input terminal of the third inverter is connected to the output terminal of the reset button circuit of the reset trigger module. The output terminal of the third inverter is connected to the CP terminal of the third trigger. The Q terminal of the third trigger is connected to the CPU;

[0063] The CPU is also connected to the RD terminals of the first trigger, the second trigger, and the third trigger, and is used to reset the first trigger, the second trigger, and the third trigger after reading the status for the next use.

[0064] Specifically, when a short-term power failure of a certain power supply is detected by the power supply monitoring circuit, the power supply monitoring reset signal changes from high to low. Through the first inverter, the level of the CP terminal of the first flip-flop is inverted, causing the level of the Q terminal of the first flip-flop to change and be maintained, enabling the reset cause recording module to record the operation of the power supply monitoring circuit;

[0065] When an exception occurs in the CPU program, resulting in an active restart or a passive restart, the watchdog reset signal changes from high to low. Through the second inverter, the level of the CP terminal of the second flip-flop is inverted, causing the level of the Q terminal of the second flip-flop to change and be maintained, enabling the reset cause recording module to record the restart operation caused by the exception in the program;

[0066] When a human operation presses the reset button in the reset trigger module, the button reset signal changes from high to low. Through the third inverter, the level of the CP terminal of the third flip-flop is inverted, causing the level of the Q terminal of the third flip-flop to change and be maintained, enabling the reset cause recording module to record the restart operation caused by the human pressing of the reset button.

[0067] Preferably, the reset cause recording module is independently powered, using a different power supply from other modules to ensure its independence.

[0068] Preferably, the flip-flops in the reset cause recording module use D flip-flops.

[0069] The data and log recording module includes: a memory unit, a fourth flip-flop, and a non-volatile storage unit.

[0070] To ensure that the data in the memory can be continuously saved without loss during the CPU reset process, during the normal operation state after each startup of the CPU, the memory controller needs to be set to automatically enter the self-refresh state when it detects that the memory is in the idle state. When an exception occurs in the CPU program, the memory will be able to enter the self-refresh state. In this state, when the CPU is unable to provide a refresh command to the memory, the memory can perform self-refresh to ensure that the stored data is not lost.

[0071] To ensure that the memory can remain in the self-refresh state and will not be reset during the initialization of the memory after the CPU restarts, during the normal operation state after each startup of the CPU, use the combination of the fourth flip-flop and the OR gate in the data and log recording module to keep the reset signal of the memory at a high level and unable to be pulled low by the CPU's memory reset signal. Before and after the CPU restart process and before actively exiting the self-refresh state of the memory, the memory can continuously maintain the self-refresh state, thus ensuring that the data stored in the memory is not lost at all.

[0072] Preferably, a pull-down resistor should be connected to the CKE signal of the memory so that the CKE signal can be reliably maintained at a low level during the reset of the CPU chip to ensure the stability of the self-refresh state.

[0073] After the CPU starts or restarts, regardless of whether the memory is in the self-refresh state or not, the program will cause the memory to exit the self-refresh state. If the memory is not in the self-refresh state at this time, there will be no impact. If the memory is in the self-refresh state at this time, it will exit the self-refresh state. Then, read the output value of the flip-flop in the reset reason recording module, save the result to a memory variable, record it as the reset reason information for other modules in the program to call. Reset the flip-flop in the reset reason recording module to the initial state for use in the next reset.

[0074] The CPU can determine whether this startup is a cold startup or a warm startup through the information in the reset reason recording module. If it is a warm startup, the program will cause the memory to exit the self-refresh state, then read the output value of the flip-flop in the reset reason recording module as the reset reason information record, and then reset the flip-flop to the initial state. For the important data, status information, and log information saved before the reset stored in the memory or non-volatile memory, after the CPU makes a validity judgment on these data or information, it reads and uses them as needed, such as saving the above information in the memory completely to the non-volatile memory for future retrieval and analysis.

[0075] The CP terminal of the fourth flip-flop is connected to the CPU, and the Q terminal is logically ORed with the CPU's reset signal for the memory and then sent to the memory reset input terminal; in the normal operating state after each startup of the CPU, the CPU flips the level of the CP terminal of the fourth flip-flop, causing the level of the Q output terminal of the fourth flip-flop to change and be maintained. After being logically ORed with the CPU's reset signal for the memory, the output of the fourth flip-flop causes the reset signal of the memory to remain high during the CPU reset period and after the CPU restarts and initializes the memory, so that the memory will not be reset, the self-refresh state is maintained, and the data in the memory will be reliably saved.

[0076] Preferably, the fourth flip-flop in the data and log recording module uses a D flip-flop.

[0077] The reset execution module includes: a delay reset circuit and a normal reset circuit.

[0078] The input terminal of the delay reset circuit is the first input terminal of the reset execution module, which is connected to the output terminals of the watchdog circuit and the reset button circuit. The output terminal of the delay reset circuit is connected to the input terminal of the normal reset circuit, and the input terminal of the normal reset circuit is the second input terminal of the reset execution module.

[0079] When the delayed reset circuit receives the watchdog reset signal changing from high to low, it performs a set delay, reserves a certain amount of time for the CPU to save data and logs, and then resets the CPU. During the reset delay period, the CPU needs to write the required important data, status information, and log information into the memory within the limited delay period, so as to be retrieved for analysis or transferred to the non-volatile memory after restart.

[0080] After the delay ends, the delayed reset signal generated by the delayed reset circuit changes from high level to low level, which will trigger the operation of the normal reset circuit and immediately reset the CPU. The delayed reset signal and the power supply monitoring reset signal are in wire-AND logic, and the result is low level when any signal is low level. Therefore, when the power supply monitoring reset signal becomes low level, it will trigger the operation of the normal reset circuit and immediately reset the CPU, preventing the CPU from performing unexpected operations in the abnormal power supply state.

[0081] Furthermore, the operation of the power supply monitoring circuit in the reset trigger module only triggers the operation of the reset cause recording module and does not trigger the operation of the data and log recording module. However, it will reset the flip-flop in the data and log recording module to the initial state, enabling the CPU to regain control of the memory reset right, and the memory can be reset during the memory initialization operation after restart.

[0082] Preferably, the delayed reset function can be implemented using a power supply timing control chip to obtain a relatively accurate delay time.

[0083] Preferably, the normal reset circuit is implemented using a reset chip.

[0084] It should be noted that based on the above technical solutions, the reset cause recording module and the data and log recording module can automatically record the restart actions caused by program exceptions, the restart actions caused by the manual pressing of the reset button, and the restart actions caused by the power supply monitoring circuit.

[0085] As Figure 2 shown, Embodiment 2 of the present invention provides a method for automatically recording the reasons for abnormal restart of the CPU and effectively saving the restart logs and important data, including the following steps:

[0086] Step 1, the CPU starts and maintains a normal running state. The CPU outputs a watchdog feeding signal to the watchdog on time and regularly writes relevant important data, status information, log information, etc. into the memory and / or non-volatile storage unit.

[0087] In a preferred but non-limiting embodiment of the present invention, Step 1 specifically includes:

[0088] Step 1.1, the CPU starts. Whether the CPU starts for the first time after power-on (cold start) or restarts without power-on (hot start), the program will make the memory exit the self-refresh state. If the memory is not in the self-refresh state at this time, there will be no impact. If the memory is in the self-refresh state at this time, it will exit the self-refresh state and enter the auto-refresh state, and the CPU will provide the refresh command for the memory.

[0089] Specifically, to ensure that the data in the memory can be continuously saved and not lost during the CPU reset process, the memory controller needs to be set to automatically enter the self-refresh state when it detects that the memory is in the idle state during the normal operation state after each CPU start. When an exception occurs in the CPU program, the memory can automatically enter the self-refresh state. In this state, when the CPU is unable to provide the refresh command for the memory, the memory can perform self-refresh to ensure that the stored data is not lost.

[0090] To ensure that the memory can remain in the self-refresh state and not be reset during the initialization of the memory after the CPU restarts, during the normal operation state after each CPU start, the CP terminal level of the fourth flip-flop in the data and log recording module needs to be inverted, so that the output Q terminal level of the fourth flip-flop changes and remains unchanged, and performs a logical OR with the CPU's reset signal for the memory. The output of the fourth flip-flop makes the memory's reset signal remain high during the CPU reset period and after the CPU restarts and initializes the memory, so that the memory will not be reset, the self-refresh state is maintained, and the data in the memory will be reliably saved.

[0091] Step 1.2, the CPU reads the output value of the flip-flop in the reset reason recording module, saves the result to a memory variable, records it as the reset reason information, and makes it available for other modules in the program to call. The flip-flop in the reset reason recording module is reset to the initial state for use in the next reset.

[0092] Step 1.3, based on the result of Step 1.2, the CPU can know whether this start is a cold start or a hot start. If it is a hot start, important data, status information, and log information saved before the reset should be stored in the memory or non-volatile memory. After the CPU makes a validity judgment on these data or information, it can read and use them as needed, such as saving the above information in the memory to the non-volatile memory completely for future retrieval and analysis.

[0093] Step 1.4, the CPU starts and maintains the normal operation state. The CPU outputs a watchdog feeding signal on time and regularly writes relevant important data, status information, log information, etc. to the memory or non-volatile storage unit. The watchdog feeding signal path is as Figure 1 shown.

[0094] Step 2: Determine whether a reset event occurs. If no reset event occurs, return to Step 1, where the CPU continues to output a watchdog feeding signal on time and regularly writes relevant important data, status information, log information, etc. to the memory or non-volatile storage unit. If a reset event occurs, continue to determine whether the reset source is power monitoring. If the reset is caused by power monitoring, execute Step 4; otherwise, execute Step 3.

[0095] Step 3: The reset trigger module provides an interrupt signal exclusive to the program exception event and / or an interrupt signal exclusive to the reset button event, and sends them to the CPU, the reset reason recording set module, and the reset execution module. The CPU responds or does not respond to the interrupt signal according to the degree of exception. The reset reason recording set module records the reset reason, and the reset execution module executes a delayed reset function under the trigger of the interrupt signal, delaying the CPU reset time. If the CPU can still respond to the interrupt signal, the interrupt signal triggers the data and log recording module to work, and during the delayed reset period, the set content is saved to the memory and / or non-volatile storage unit in real time. If the CPU can no longer respond to the interrupt signal, the interrupt signal does not trigger the data and log recording module to work, and the CPU waits to restart immediately after the delayed reset ends. The set content is saved by the last regular save operation before the exception occurs.

[0096] Specifically, when an exception occurs in the CPU program or an active reset is performed, the watchdog timer in the reset trigger module times out, and the watchdog reset signal changes from high to low. Through the second inverter, the level of the CP terminal of the second flip-flop is inverted, causing the level of the Q terminal output by the second flip-flop to change and remain. The reset reason recording module records the action of the watchdog.

[0097] Or when the reset button in the reset trigger module is pressed, the button reset signal changes from high to low. Through the third inverter, the level of the CP terminal of the third flip-flop is inverted, causing the level of the Q terminal output by the third flip-flop to change and remain. The reset reason recording module records the action of the reset button being pressed.

[0098] Step 3 includes Step 3.A and Step 3.B that occur almost simultaneously and have no sequential logical order.

[0099] Step 3.A: When the watchdog reset signal changes from high level to low level, it provides a program exception event exclusive interrupt signal for the CPU; or when the button reset signal changes from high level to low level, it provides a reset button event exclusive interrupt signal for the CPU.

[0100] When the degree of CPU program exception is relatively light and the CPU can still respond to the interrupt signal, it can have the ability to save important data and log information. Any interrupt signal will trigger the data and log recording module to start working, and important data, status information, log information, etc. can be saved in real time.

[0101] If the abnormal degree of the CPU program is relatively serious and it is no longer able to respond to the interrupt signal, the data and log recording module will not be triggered, and the CPU will quietly wait for a restart. Relevant important data, status information, log information, etc. can be properly saved by the last regular save operation before the exception occurs.

[0102] Step 3.B, the watchdog reset signal and the reset button signal in the reset trigger module are in wire-AND logic. When any signal is at a low level, the result is at a low level, triggering the operation of the delay reset circuit in the reset execution module to start delay reset.

[0103] During the reset delay period, the CPU needs to write the required important data, status information, and log information into the memory within the limited delay period, and can also write data and information into non-volatile memories such as EEPROM, NOR FLASH, NAND FLASH, eMMC, and SSD at the same time.

[0104] When the reset delay ends, the delay reset signal becomes low. Specifically, the delay reset signal and the power supply monitoring reset signal are in wire-AND logic. When any signal is at a low level, the result is at a low level. Therefore, after the reset delay ends, when the delay reset signal becomes low, it will trigger the operation of the normal reset circuit, causing the CPU to be immediately reset.

[0105] Step 4, the reset execution module performs an immediate restart operation of the CPU triggered by the power supply monitoring reset signal, and the set content is saved by the last regular save operation before the exception occurs.

[0106] Specifically, the power supply monitoring circuit in the reset trigger module performs real-time detection on the power supplies of each circuit board. When any power supply is detected to be abnormal, the power supply monitoring reset signal changes from high to low, causing the level of the CP terminal of the third flip-flop to flip through the third inverter, causing the level of the Q terminal output of the third flip-flop to change and remain, enabling the reset cause recording module to record the operation of the power supply monitoring circuit.

[0107] The operation of the power supply monitoring circuit in the reset trigger module only triggers the operation of the reset cause recording module and does not trigger the operation of the data and log recording module.

[0108] Therefore, it directly jumps to Step 4. When the power supply monitoring reset signal becomes low, it will trigger the operation of the normal reset circuit, causing the CPU to be immediately reset, preventing the CPU from performing unexpected operations in the power abnormal state.

[0109] After the CPU is started or restarted, the above operation steps are repeated starting from Step 1.

Claims

1. A system that automatically records the cause of abnormal CPU restart and saves logs and data, characterized in that: include: Reset trigger module, reset reason recording module, data and log recording module and reset execution module; When the CPU system operates normally, the CPU periodically writes the set contents into the memory unit or non-volatile storage unit of the data and log recording module; When the CPU system runs abnormally, the reset trigger module is used to provide an interrupt signal exclusive to the program abnormal event and / or an interrupt signal exclusive to the reset key event, which is sent to the CPU, the reset cause record set module and the reset execution module; the reset trigger module also provides a power monitoring reset signal, which is sent to the reset cause record set module and the reset execution module; The reset reason recording module records the reset reason according to the interrupt signal or the power monitoring reset signal; The reset execution module executes the delayed reset function when triggered by the interrupt signal, and postpones the CPU reset time; if the CPU can still respond to the interrupt signal, the interrupt signal triggers the data and log recording module to work, and during the delayed reset period, the set content is saved in real time to the memory and / or non-volatile storage unit; if the CPU can no longer respond to the interrupt signal, the interrupt signal does not trigger the data and log recording module to work, and the CPU waits for the delayed reset to end and then restarts immediately, and the set content is saved by the last periodic save operation before the exception occurs; the reset execution module executes the CPU immediate restart operation when triggered by the power monitoring reset signal.

2. The system for automatically recording the cause of abnormal CPU restart and saving logs and data as claimed in claim 1, characterized in that: The reset trigger module includes: a reset button circuit, a watchdog circuit and a power monitoring circuit; The output end of the reset button circuit is the first output end of the reset trigger module, and is connected to the first input end of the reset cause recording module, the first input end of the reset execution module and the CPU respectively; The input end of the watchdog circuit is the input end of the reset trigger module, which is used to receive the dog feeding signal output by the CPU to the watchdog on time. The output end of the watchdog circuit is the second output end of the reset trigger module, which is connected to the second input end of the reset cause recording module, the first input end of the reset execution module and the CPU respectively; The output end of the power monitoring circuit is the third output end of the reset trigger module, and is connected to the third input end of the reset cause recording module and the second input end of the reset execution module.

3. The system for automatically recording the cause of abnormal CPU restart and saving logs and data as claimed in claim 2, characterized in that: The reset button circuit includes a three-state gate device, so that its signal output is an open-drain output; the reset signal output of the watchdog chip is an open-drain output; the watchdog reset signal and the reset button signal are wired-AND logic, connected to the first input terminal of the reset execution module, and the result is a low level when any signal is low level; The POWERGOOD signals of multiple power supply chips are wired and logic-generated into a power monitoring reset signal. If any power supply is abnormal, the power monitoring reset signal can be triggered to change from a high level to a low level.

4. The system for automatically recording the cause of abnormal CPU restart and saving logs and data as claimed in claim 2, characterized in that: The reset cause recording module includes: at least three trigger circuits and a corresponding number of inverters; The input end of the first inverter is connected to the output end of the power monitoring circuit of the reset trigger module, the output end of the first inverter is connected to the CP end of the first trigger, and the Q end of the first trigger is connected to the CPU; The input end of the second inverter is connected to the output end of the watchdog circuit of the reset trigger module, the output end of the second inverter is connected to the CP end of the second trigger, and the Q end of the second trigger is connected to the CPU; The input end of the third inverter is connected to the output end of the reset button circuit of the reset trigger module, the output end of the third inverter is connected to the CP end of the third trigger, and the Q end of the third trigger is connected to the CPU.

5. The system for automatically recording the cause of abnormal CPU restart and saving logs and data as claimed in claim 3, characterized in that: The data and log recording module includes: a memory unit, a fourth trigger, and a non-volatile storage unit; In the normal operation state after each CPU startup, the memory controller is first set to automatically enter the self-refresh state when it detects that the memory is in an idle state; The CP terminal of the fourth trigger is connected to the CPU, and the Q terminal performs a logic OR operation with the CPU on the reset signal of the memory and then sends the result to the reset input terminal of the memory.

6. The system for automatically recording the cause of abnormal CPU restart and saving logs and data as claimed in claim 3, characterized in that: The reset execution module includes: a delayed reset circuit and a normal reset circuit; The input end of the delayed reset circuit is the first input end of the reset execution module, which is connected to the output end of the watchdog circuit and the output end of the reset button circuit. The output end of the delayed reset circuit is connected to the input end of the common reset circuit, and the input end of the common reset circuit is the second input end of the reset execution module.

7. The system for automatically recording the cause of abnormal CPU restart and saving logs and data as claimed in claim 3, characterized in that: The delayed reset signal and the power monitoring reset signal are wired AND logic. When any signal is at a low level, the result is a low level. When the delay ends, the delayed reset signal changes from high to low or the power monitoring reset signal changes from high to low, which will trigger the normal reset circuit to reset the CPU immediately.

8. A method for automatically recording the cause of abnormal CPU restart and saving logs and data, based on the system for automatically recording the cause of abnormal CPU restart and saving logs and data as described in any one of claims 1 to 7, characterized in that: The following steps are involved: Step 1, the CPU starts, starts and maintains normal operation, the CPU outputs a feeding signal to the watchdog on time, and regularly writes the set content into the memory and / or non-volatile storage unit; Step 2, determine whether a reset event occurs. If no reset event occurs, return to step 1 and continue to output a dog feeding signal to the watchdog by the CPU on time, and write the set content into the memory or non-volatile storage unit regularly; If a reset event occurs, continue to determine whether the reset source is power monitoring. If power monitoring causes reset, execute step 4; otherwise, execute step 3. Step 3, the reset trigger module provides an interrupt signal exclusive to the program exception event and / or an interrupt signal exclusive to the reset button event, and sends it to the CPU, the reset cause record set module and the reset execution module; the CPU responds or does not respond to the interrupt signal according to the degree of abnormality; the reset cause record set module records the reset cause, and the reset execution module performs a delayed reset function under the trigger of the interrupt signal to postpone the CPU reset time; if the CPU can still respond to the interrupt signal, the interrupt signal triggers the data and log recording module to work, and during the delayed reset period, the set content is saved in real time to the memory and / or non-volatile storage unit; if the CPU can no longer respond to the interrupt signal, the interrupt signal does not trigger the data and log recording module to work, and the CPU waits for the delayed reset to end and then restarts immediately, and the set content is saved by the last periodic save operation before the abnormality occurs; Step 4: The reset execution module executes an immediate CPU restart operation triggered by the power monitoring reset signal, and the set content is saved by the last periodic save operation before the abnormality occurs.

9. The method for automatically recording the cause of abnormal CPU restart and saving logs and data as claimed in claim 8, characterized in that: Step 1 includes: Step 1.1, CPU starts, no matter the CPU is cold started or hot started, the memory exits the self-refresh state and enters the automatic refresh state, and the CPU provides a refresh command to the memory; Step 1.2, the CPU reads the output value of the trigger in the reset reason recording module, saves the result into a memory variable, records it as reset reason information, and provides it for other modules in the program to call; and resets the trigger in the reset reason recording module to an initial state for use in the next reset; Step 1.3, according to the result of step 1.2, the CPU writes the set content to the data and log recording module according to whether the current startup is a cold start or a hot start, for future retrieval and analysis. Step 1.4, the CPU starts and maintains normal operation, the CPU outputs a feeding signal to the watchdog on time, and periodically writes the set content into the data and log recording module.

10. The method for automatically recording the cause of abnormal CPU restart and saving logs and data as claimed in claim 9, characterized in that: Step 3 includes Step 3.A and Step 3.B, which occur almost simultaneously and in no logical order. Step 3.A, when the watchdog reset signal changes from high level to low level, an interrupt signal dedicated to a program abnormal event is provided to the CPU; or when the key reset signal changes from high level to low level, an interrupt signal dedicated to a reset key event is provided to the CPU; Step 3.B, the watchdog reset signal and the reset button signal in the reset trigger module are wired AND logic, and when any signal is at a low level, the result is a low level, triggering the delayed reset circuit in the reset execution module to start the delayed reset.

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