Clustering-based clock tree synthesis method and system

Abstract

The invention discloses a clock tree synthesis method and system based on clustering, and the method comprises the steps: carrying out the preliminary grouping of registers through employing a K-means clustering method, generating the position of a first-stage buffer under the condition that the maximum fan-out number limitation constraint, the maximum RC constraint and the position overlapping constraint are satisfied, and generating a second-stage buffer based on the position, and then constructing a subsequent clock tree by adopting a DME algorithm. The problem of clock signal distribution in large-scale integrated circuit design is solved, clock delay, clock skew and the number of buffers can be reduced, and the comprehensive quality of the clock tree is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design and electronic design automation, and in particular to a clock tree synthesis method and system based on clustering. Background Art

[0002] In recent years, the development of the integrated circuit (IC) field has been increasingly rapid, and the demand for chip design has continued to increase. With the advancement of integrated circuit manufacturing technology, the number of transistors in the chip has increased year by year, and the number of logic gates contained in the chip has increased dramatically. A very large scale integrated circuit (VLSI) chip integrates tens of millions or even billions of transistors, and thousands of wire nets need to be connected; at the same time, each wire net has hundreds of or even more wiring schemes, which makes the wiring problem extremely complicated. When designing a chip, Clock Tree Synthesis (CTS) is a very important step in the physical design process. It interconnects the modules, standard cells, and input and output units distributed in the chip core according to logical relationships, and the clock network formed by the interconnection must meet the design rules. The quality of the CTS result directly affects the function, performance, and stability of the entire chip.

[0003] Traditional CTS algorithms often fail to balance the goals of running time and CTS quality, and the final CTS solution determined does not avoid short circuits and violates design rules, so it is difficult to solve the CTS problem of multiple instantiation modules. Existing CTS algorithms can be roughly divided into three categories: CTS algorithms based on heuristic algorithms, such as L-shaped pattern routing in the shortest path, although they run faster, they will miss many better CTS strategies due to the greed of the heuristic algorithm itself, which may lead to large clock delays or uneven clock skew; CTS algorithms based on search algorithms, such as maze algorithms, although they can discretize the problem space, but because they ignore the concurrency of CTS strategies, they are not only prone to repeated searches for a large number of similar strategies, but also still need to search for a large number of redundant paths under multiple endpoints, resulting in too many buffers being inserted; CTS algorithms based on graph theory algorithms, such as network flow and Steiner tree algorithms, although they have seemingly more systematic and sophisticated theoretical systems, they do not make full use of the geometric information in the CTS process, making CTS not flexible enough. In summary, existing methods are difficult to strike a balance between clock skew, clock delay, and the number of buffer insertions. Summary of the invention

[0004] Purpose of the invention: The purpose of the present invention is to provide a clock tree synthesis method and system based on clustering, which obtains the optimal clock tree insertion scheme by adding constraints such as clock delay, clock offset, and the number of buffers to the K-means clustering method and its variants, and solves the problems of high computational complexity, path redundancy, short circuit and design rule violation of the traditional CTS algorithm when processing large-scale designs.

[0005] Technical solution: The clustering-based clock tree synthesis method of the present invention comprises the following steps: (1) Read the size, number and location of registers in the circuit; (2) storing the coordinates of the register into a coordinate set, clustering the coordinate set to generate a number of clusters to be processed, and clearing the coordinate set; making adjustments in each cluster to be processed according to the constraint conditions until the constraint conditions are met, and using the position of the cluster center in each cluster to be processed as the position of the first-level buffer to be inserted; The constraints include the maximum fan-out limit constraint and the maximum RC constraint. For the clusters to be processed that do not meet the constraints, the buffer farthest from the cluster center is removed and reallocated to the cluster to be processed. If it cannot be allocated, the coordinates of the buffer are stored in the coordinate set. The maximum RC constraint is: Calculate , if it is not greater than the maximum RC limit, then the maximum RC constraint is satisfied, is the Manhattan distance between the buffer and the cluster center, r and c are the resistance and capacitance of the line between the buffer and the cluster center, respectively; (3) storing the coordinates of the first-level buffer into the coordinate set, and repeating step (2) to obtain the position of the second-level buffer; (4) constructing a clock tree for the second-level buffer using the DME algorithm until the clock tree synthesis of the circuit is completed, and obtaining the positions of the third-level to N-level buffers; (5) Output clock tree synthesis plan, including the number and location of buffers and their connection relationships.

[0006] Furthermore, step (2) also includes a position overlap constraint, and if the buffer and the register overlap, the position of the buffer is moved, which specifically includes the following steps: Register for size The first rectangle of the buffer is of size The second rectangle is expanded outward based on the vertex of the preset direction of the first rectangle to form a second rectangle with a size of A third rectangle, the third rectangle includes the first rectangle and coincides with a first vertex angle of the first rectangle, and the first vertex angle is located at a diagonal position of a preset direction of the first rectangle; Determine whether the vertex of the second rectangle in the preset direction is inside the third rectangle. If it is inside the third rectangle, the register and the buffer overlap, and move the vertex of the second rectangle in the preset direction to the safety line segment on the third rectangle; The method for selecting the safety line segment on the third rectangle is: Determine whether there are other registers around the register. The third rectangle formed by the register is called the target third rectangle, and the third rectangle formed by other registers around the register is called the neighboring third rectangle. If they intersect, determine whether there are other registers around the register. On the boundary of the third rectangle, remove the part that intersects with the neighboring third rectangle, and remove the part that overlaps with the first rectangle to obtain a safety line segment.

[0007] Furthermore, in step (2), if the number of coordinates in the coordinate set is greater than the maximum fan-out number, the MinibatchKmeans clustering algorithm is used for clustering, otherwise the K-means clustering algorithm is used for clustering.

[0008] Furthermore, in the Minibatch Kmeans clustering algorithm, the K value in the cluster is: ; in is the total number of coordinates in the coordinate set, is the maximum fan-out number.

[0009] Furthermore, the elbow method is used to determine the K value in the K-means clustering algorithm.

[0010] Furthermore, in step (4), it is determined whether the position of the buffer satisfies the position overlap constraint. After the position overlap constraint is satisfied, it is determined whether the maximum RC constraint is satisfied. If not, the buffer is inserted continuously, and the position overlap constraint and the maximum RC constraint are continuously checked until the constraint is satisfied.

[0011] The clustering-based clock tree integration system of the present invention comprises:

[0012] A data reading unit, used to read the size, number and position of registers in the circuit; The first-level buffer insertion unit is used to store the coordinates of the register into a coordinate set, cluster the coordinate set to generate a number of clusters to be processed, and clear the coordinate set; make adjustments in each cluster to be processed according to the constraint conditions until the constraint conditions are met, and use the position of the cluster center in each cluster to be processed as the position of the first-level buffer to be inserted; The constraints include the maximum fan-out limit constraint and the maximum RC constraint. For the clusters to be processed that do not meet the constraints, the buffer farthest from the cluster center is removed and reallocated to the cluster to be processed. If it cannot be allocated, the coordinates of the buffer are stored in the coordinate set. The maximum RC constraint is: Calculate , if it is not greater than the maximum RC limit, then the maximum RC constraint is satisfied, is the Manhattan distance between the buffer and the cluster center, r and c are the resistance and capacitance of the line between the buffer and the cluster center, respectively; A second-level buffer insertion unit is used to store the coordinates of the first-level buffer into the coordinate set, and repeat the first-level buffer insertion unit to obtain the position of the second-level buffer; A subsequent buffer insertion unit is used to construct a clock tree for the second-level buffer by using a DME algorithm until the clock tree synthesis of the circuit is completed to obtain the positions of the third-level to N-th-level buffers; The clock tree synthesis solution output unit is used to output the clock tree synthesis solution, including the number and location of the buffers and their connection relationship.

[0013] Further, in the first-level buffer insertion unit, if the number of coordinates in the coordinate set is greater than the maximum fan-out number, the Minibatch Kmeans clustering algorithm is used for clustering, otherwise the K-means clustering algorithm is used for clustering; In the Minibatch Kmeans clustering algorithm, the K value in the cluster is:

[0014] ; in is the total number of coordinates in the coordinate set, is the maximum fan-out number; The elbow method is used to determine the K value in the K-means clustering algorithm.

[0015] The electronic device described in the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded into the processor, the clustering-based clock tree synthesis method is implemented.

[0016] The computer-readable storage medium of the present invention stores a computer program, and when the computer program is executed by a processor, the clock tree synthesis method based on clustering is implemented.

[0017] Beneficial effects: Compared with the prior art, the advantages of the present invention are: (1) Improve the comprehensive quality of the clock tree: Registers are grouped by the K-means clustering method and its variants, and the clock tree is constructed from the bottom up in combination with the DME algorithm. The Manhattan distance between adjacent points can be effectively calculated and the rectangular area can be extended along the 45-degree direction to determine the overlapping line segments to balance the clock offset of the previous level, thereby reducing the clock delay and clock offset as a whole and ensuring the stability and synchronization of the clock signal. The number of clusters is dynamically adjusted during the clustering process to ensure that the fan-out within each cluster does not exceed the maximum allowed value, and the distribution of clusters is further optimized through post-processing methods, so that the insertion position of the buffer is more reasonable, thereby reducing the number of buffers used and reducing the complexity and power consumption of the circuit; (2) Improve algorithm efficiency and applicability: Use the MiniBatch K-means clustering method to perform preliminary clustering of large-scale registers, which significantly reduces the computational cost. This is especially suitable for scenarios with limited memory or excessive data volume, and improves the applicability of the algorithm in large-scale integrated circuit design. In the initial clustering stage, use the MiniBatch K-means clustering method with a faster clustering speed to ensure clustering accuracy; in the subsequent stage, switch to K-means clustering with the elbow method, without fixing the K value, and use the elbow method to obtain the most appropriate K value, further optimize the clustering results, balance the clustering time and clustering accuracy, and improve the efficiency and effectiveness of the algorithm; (3) Optimize design constraints: In each step of the clustering process, constraints such as clock delay, clock offset, and the number of buffers are added, and the clustering results are judged and optimized through post-processing methods, such as maximum fan-out constraints, maximum RC constraints, and position overlap constraints, to ensure that the final generated clock tree meets all design constraints and avoids problems such as short circuits and violations of design rules. By dynamically adjusting the number and position of clusters, and making constraint and position overlap judgments when building each level of the clock tree, the construction of the clock tree is more flexible and can better adapt to different design requirements and scenarios; (4) Lay the foundation for subsequent design: The output optimized design information includes register location information, buffer insertion location information, and net connection relationship information, which is stored in the form of a text file, providing a reliable basis for the verification and adjustment of subsequent digital circuit design, and helping to improve the efficiency and quality of the entire chip design. The clock tree solution generated by this method not only performs well in the CTS stage, but also provides a solid foundation for subsequent physical design, promotes the connection and overall optimization of the design process, and has broad application prospects and practical value. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a flow chart of the clock tree synthesis method of the present invention.

[0019] Figure 2 Flowchart for generating buffer locations via Kmeans clustering.

[0020] Figure 3 Schematic diagram of position overlap in an embodiment of the present invention.

[0021] Figure 4 4 is a schematic diagram of the position overlap determination principle in an embodiment of the present invention.

[0022] Figure 5 It is a schematic diagram of the first-level buffer insertion result in an embodiment of the present invention.

[0023] Figure 6 Schematic diagram of a buffer inserted through DME in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0025] like Figure 1 As shown, the clustering-based clock tree synthesis method includes the following steps.

[0026] S1: Write an input file reading program in C++ language.

[0027] Use C++ program to read input and constraint files to obtain the register connection information and signal topology of the circuit. The content obtained from the input file includes unit, floorplan, coordinates of clock source CLK, sizes of register (FF) and buffer (buffer) FF_cell and buffer_cell, and all register coordinates FF_instance; the content obtained from the constraint file includes resistance value r per unit length net, capacitance value c, maximum rc value limit, maximum fanout limit Max_fanout, and delay data of a single buffer. Finally, visualize the extracted information to verify whether the circuit information is accurately extracted.

[0028] S2: Perform Kmeans clustering on the FF coordinates and insert them into the first-level buffer.

[0029] like Figure 2 As shown, to perform step S2, three key data sets need to be constructed first, namely the coordinate set, the cluster set to be processed, and the clustering result set. The coordinate information of all registers in the circuit is completely entered into the coordinate set. Subsequently, the scale of the coordinate set is judged. If the number of coordinates it contains exceeds the preset maximum fan-out limit, the Minibatch Kmeans clustering algorithm is immediately started to perform clustering tasks for all coordinates in the coordinate set. After the clustering is completed, the obtained clustering results (i.e., multiple clusters) are uniformly stored in the cluster set to be processed. At the same time, all coordinate data in the coordinate set are cleared for subsequent operations.

[0030] Next, each cluster in the processing cluster set is carefully examined. The number of coordinates in each cluster is checked in particular. For those clusters whose number of coordinates in the cluster still exceeds the maximum fan-out limit, a post-processing method based on a priority queue is used for optimization. Specifically, based on the Manhattan distance, the register farthest from the cluster center is selected from each over-limit cluster in turn, and an attempt is made to find a new accommodating cluster for it. If a suitable new cluster is successfully found, the register is moved into the new cluster; if a suitable new cluster cannot be found after traversing all possibilities, the register is put back into the coordinate set. During the entire process of register moving out or in, the cluster center position of the relevant cluster is updated in real time to ensure that the number of coordinates in each cluster does not exceed the constraint limit of the maximum fan-out number.

[0031] After completing the above post-processing, enter the maximum RC constraint judgment phase. For each cluster in the processing cluster set, calculate its RC value and compare it with the preset maximum RC value. If the RC value of the cluster is less than or equal to the maximum RC value, it means that the cluster meets the design requirements, and it is removed from the processing cluster set and stored in the cluster result set; on the contrary, if the RC value of the cluster exceeds the maximum RC value, it is necessary to remove the point farthest from the cluster center Manhattan distance from the cluster, put it back into the coordinate set, and then update the cluster center of the cluster, and calculate and judge whether the RC value of the cluster meets the constraint again.

[0032] When the RC value meets the conditions, it is necessary to determine and correct the position overlap of the cluster center of the cluster. Figure 3 A buffer with overlapping positions is selected as the effect demonstration. The red color is the initial position of the overlapping buffer. After position overlap determination and correction, the buffer insertion position is transferred to the green position without overlap. Figure 4 As shown, in the overlap determination process, all the registers and the rectangles with determined buffer sizes can be determined to overlap by comparing the relative positions of a vertex of the rectangle. In the following discussion, the lower left vertex is used. The register shapes are all like rectangle A. 1 B 1 C 1 D 1 , its length is recorded as a, and its width is recorded as c. The shape of the buffer is like rectangle EFGH, its length is recorded as b, and its width is recorded as c. That is, the register and buffer have the same width. First, determine whether they overlap. Rectangle A 1 B 1 C 1 D 1 It is already available, with B 1 The position of the point, move horizontally to the left by b, and then move horizontally upward by c to get vertex I 1 . 1The position of the point, move horizontally to the left by b, and then move horizontally downward by c to get the vertex J 1 . Make a rectangle I 1 J 1 K 1 D 1 At this time, we only need to determine whether the position of the lower left vertex of the buffer is within the rectangle I 1 J 1 K 1 D 1 Inside, the overlap needs to be moved. In order to minimize the moving distance and reduce the deviation, choose rectangle I as much as possible. 1 J 1 K 1 D 1 The position of the safe line segment that will not cause overlap in the edge. At this time, we need to find the position of the safe line segment in rectangle A. 1 B 1 C 1 D 1 Other registers that may exist nearby. 1 The position of the point is moved horizontally to the left by a, and then horizontally upward by c to obtain the vertex L. 1 The position of point is moved horizontally to the left by a, and then horizontally downward by c to obtain vertex M. 1 The position of the point, horizontally move right by b, and then horizontally move upward by c to get the vertex O. 1 The position of the point is moved horizontally to the right by b, and then horizontally downward by c to obtain vertex N. First, find all the registers whose lower left vertices are inside the rectangle LMNO, such as A 2 B 2 C 2 D 2 Then make a similar rectangle in the same way. 1 J 1 K 1 D 1 Rectangle, such as I 2 J 2 K 2 D 2 , then rectangle I 2 J 2 K 2 D 2 With rectangle I 1 J 1 K 1 D 1 The intersecting line segments are the locations where the placement is not allowed. By judging all the registers inside the rectangle LMNO, we can get the rectangle I 1 J 1 K 1 D 1When the lower left vertex of the buffer moves to the safety segment, the non-overlapping condition is met. In order to minimize the deviation, a point on the safety segment with the smallest distance from the original position after the move is selected for placement. 1 J 1 K 1 D 1 If none of them are satisfied, another nearest register is selected and the same operation is performed until a safe position is found that does not cause overlap.

[0033] Since the Minibatch Kmeans clustering algorithm has significant advantages in processing large-scale point sets, in the later stage of preliminary clustering, when the number of registers remaining in the coordinate set is small, in order to further improve the clustering accuracy, it is necessary to switch the clustering method. The present invention adopts K-means clustering combined with the elbow method as the subsequent clustering algorithm. The judgment criteria for switching the clustering method are: when the number of coordinates remaining in the coordinate set is greater than the maximum fan-out limit, continue to use Minibatch Kmeans clustering; when the number of coordinates is less than or equal to the maximum fan-out limit, switch to K-means clustering with the elbow method. After the clustering method is switched, except for the differences in the clustering algorithm itself, the rest of the post-processing process (such as optimization operations based on priority queues) and position overlap judgment operations are consistent with the previous ones, ensuring the consistency and stability of the entire clustering process. The insertion result of the first-level buffer of this example is shown as follows. Figure 5 shown.

[0034] S3: Perform Kmeans clustering on the first-level buffer coordinates and insert them into the second-level buffer.

[0035] This step is basically the same as S2, except that the points initially stored in the coordinate set are changed to the first-level buffer coordinates.

[0036] S4: Build a subsequent clock tree for the obtained second-level buffer using the DME algorithm.

[0037] Get the coordinates of the second-level buffer. The delay deviation from different registers to clk in direct clustering may be large. The DME algorithm balances the two buffers. First, use the greedy algorithm to classify the coordinates of the second-level buffer, then use the DME algorithm to get the possible placement positions, and then make overlapping judgments and moves for the possible positions. Under the premise of non-overlapping, reduce the error of delay offset as much as possible. Detect the maximum RC constraint. If it is not met, insert an additional buffer. The inserted buffer will divide the original length d into two segments e and f. e+f=d, and the two lines d 1 and d 2 The distances between e and f will affect the total delay. The selected position is expected to be e 1 2+f 1 2 The delay caused by the addition of its corresponding upper delay and e 2 2 +f 2 2 The delay caused by adding the delay of its corresponding upper level is as small as possible. Then check whether there is overlap, repeat the overlap detection and RC constraint determination steps until all conditions are met. Figure 6 As shown, the blue rectangle is the second-level buffer and the green rectangle is the location of the next-level buffer.

[0038] S5: Output the optimal clock tree solution.

[0039] After completing the optimization process, the system will output the optimized circuit clock tree comprehensive information to the file, including register location information, buffer insertion location information, and optimized signal topology structure and net connection relationship and other key parts. These output information has good readability and standardization, which can provide detailed data support for subsequent circuit verification work, and also facilitate designers to carry out iterative design and further optimize circuit performance.

[0040] The clustering-based clock tree integration system of the present invention comprises: A data reading unit, used to read the size, number and position of registers in the circuit; The first-level buffer insertion unit is used to store the coordinates of the register into a coordinate set, cluster the coordinate set to generate a number of clusters to be processed, and clear the coordinate set; make adjustments in each cluster to be processed according to the constraint conditions until the constraint conditions are met, and use the position of the cluster center in each cluster to be processed as the position of the first-level buffer; The constraints include the maximum fan-out limit constraint and the maximum RC constraint. For the clusters to be processed that do not meet the constraints, the buffer farthest from the cluster center is removed and reallocated to the cluster to be processed. If it cannot be allocated, the coordinates of the buffer are stored in the coordinate set. The maximum RC constraint is: Calculate , if it is not greater than the maximum RC limit, then the maximum RC constraint is satisfied, Manhattan distance between the buffer and the cluster center, r and c are the resistance and capacitance of the line between the buffer and the cluster center, respectively; A second-level buffer insertion unit is used to store the coordinates of the first-level buffer into the coordinate set, and repeat the first-level buffer insertion unit to obtain the position of the second-level buffer; A subsequent buffer insertion unit is used to construct a clock tree for the second-level buffer by using a DME algorithm until the clock tree synthesis of the circuit is completed to obtain the positions of the third-level to N-th-level buffers; The clock tree synthesis solution output unit is used to output the clock tree synthesis solution, including the number and location of the buffers and their connection relationship.

[0041] The electronic device described in the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded into the processor, the clustering-based clock tree synthesis method is implemented.

[0042] The computer-readable storage medium of the present invention stores a computer program, and when the computer program is executed by a processor, the clock tree synthesis method based on clustering is implemented.

[0043] The computer-readable storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, or any other medium that can be used to store program code in the form of instructions or data structures and that can be accessed by a computer.

[0044] The processor is used to execute the computer program stored in the memory to implement each step of the method involved in the above embodiment.

Claims

1. A clock tree synthesis method based on clustering, characterized in that: The steps include: (1) Read the size, number and location of registers in the circuit; (2) storing the coordinates of the register into a coordinate set, clustering the coordinate set to generate a number of clusters to be processed, and clearing the coordinate set; In each to-be-processed cluster, adjustments are made according to the constraint conditions until the constraint conditions are satisfied, and the position of the cluster center in each to-be-processed cluster is used as the position of the first-level buffer to be inserted; The constraints include the maximum fan-out limit constraint and the maximum RC constraint. For the clusters to be processed that do not meet the constraints, the buffer farthest from the cluster center is removed and reallocated to the cluster to be processed. If it cannot be allocated, the coordinates of the buffer are stored in the coordinate set. The maximum RC constraint is: Calculate , if it is not greater than the maximum RC limit, then the maximum RC constraint is satisfied, is the Manhattan distance between the buffer and the cluster center, r and c are the resistance and capacitance of the line between the buffer and the cluster center, respectively; (3) storing the coordinates of the first-level buffer into the coordinate set, and repeating step (2) to obtain the position of the second-level buffer; (4) constructing a clock tree for the second-level buffer using the DME algorithm until the clock tree synthesis of the circuit is completed, and obtaining the positions of the third-level to N-level buffers; (5) Output clock tree synthesis plan, including the number and location of buffers and their connection relationships.

2. The clustering-based clock tree synthesis method according to claim 1, characterized in that: Step (2) also includes a position overlap constraint. If the buffer and the register position overlap, the position of the buffer is moved. Specifically, the following steps are included: Register for size The first rectangle of the buffer is of size The second rectangle is expanded outward based on the vertex of the preset direction of the first rectangle to form a second rectangle with a size of A third rectangle, the third rectangle includes the first rectangle and coincides with a first vertex angle of the first rectangle, and the first vertex angle is located at a diagonal position of a preset direction of the first rectangle; Determine whether the vertex of the second rectangle in the preset direction is inside the third rectangle. If it is inside the third rectangle, the register and the buffer overlap, and move the vertex of the second rectangle in the preset direction to the safety line segment on the third rectangle; The method for selecting the safety line segment on the third rectangle is: Determine whether there are other registers around the register. The third rectangle formed by the register is called the target third rectangle, and the third rectangle formed by other registers around the register is called the neighboring third rectangle. If they intersect, determine whether there are other registers around the register. On the boundary of the third rectangle, remove the part that intersects with the neighboring third rectangle, and remove the part that overlaps with the first rectangle to obtain a safety line segment.

3. The clustering-based clock tree synthesis method according to claim 1, characterized in that: In step (2), if the number of coordinates in the coordinate set is greater than the maximum fan-out number, the Minibatch Kmeans clustering algorithm is used for clustering; otherwise, the K-means clustering algorithm is used for clustering.

4. The clustering-based clock tree synthesis method according to claim 3, characterized in that: In the MinibatchKmeans clustering algorithm, the K value in the cluster is: ； in is the total number of coordinates in the coordinate set, is the maximum fan-out number.

5. The clustering-based clock tree synthesis method according to claim 3, characterized in that: The elbow method is used to determine the K value in the K-means clustering algorithm.

6. The clustering-based clock tree synthesis method according to claim 2, characterized in that: In step (4), determine whether the position of the buffer satisfies the position overlap constraint. After satisfying the position overlap constraint, determine whether the maximum RC constraint is satisfied. If not, continue to insert the buffer and continue to check the position overlap constraint and the maximum RC constraint until the constraints are satisfied.

7. A clustering-based clock tree synthesis system, characterized in that: include: A data reading unit, used to read the size, number and position of registers in the circuit; A first-level buffer insertion unit is used to store the coordinates of the register into a coordinate set, cluster the coordinate set to generate a number of clusters to be processed, and clear the coordinate set; In each to-be-processed cluster, adjustments are made according to the constraint conditions until the constraint conditions are satisfied, and the position of the cluster center in each to-be-processed cluster is used as the position of the first-level buffer to be inserted; The constraints include the maximum fan-out limit constraint and the maximum RC constraint. For the clusters to be processed that do not meet the constraints, the buffer farthest from the cluster center is removed and reallocated to the cluster to be processed. If it cannot be allocated, the coordinates of the buffer are stored in the coordinate set. The maximum RC constraint is: Calculate , if it is not greater than the maximum RC limit, then the maximum RC constraint is satisfied, is the Manhattan distance between the buffer and the cluster center, r and c are the resistance and capacitance of the line between the buffer and the cluster center, respectively; A second-level buffer insertion unit is used to store the coordinates of the first-level buffer into the coordinate set, and repeat the first-level buffer insertion unit to obtain the position of the second-level buffer; A subsequent buffer insertion unit is used to construct a clock tree for the second-level buffer by using a DME algorithm until the clock tree synthesis of the circuit is completed to obtain the positions of the third-level to N-th-level buffers; The clock tree synthesis solution output unit is used to output the clock tree synthesis solution, including the number and location of the buffers and their connection relationship.

8. The clustering-based clock tree integration system according to claim 7, characterized in that: In the first-level buffer insertion unit, if the number of coordinates in the coordinate set is greater than the maximum fan-out number, the Minibatch Kmeans clustering algorithm is used for clustering, otherwise the K-means clustering algorithm is used for clustering; In the Minibatch Kmeans clustering algorithm, the K value in the cluster is: ； in is the total number of coordinates in the coordinate set, is the maximum fan-out number; The elbow method is used to determine the K value in the K-means clustering algorithm.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the computer program is loaded into a processor, the clustering-based clock tree synthesis method according to any one of claims 1 to 6 is implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the clustering-based clock tree synthesis method according to any one of claims 1 to 6 is implemented.

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