Implementation method and device based on EtherCAT master station system without operating system

Abstract

The invention relates to an implementation method and device for an EtherCAT master station system based on a non-operating system, and the method comprises the steps: achieving the adaptation of an SOEM protocol stack to a hardware abstraction layer of an EtherCAT master station through the byte order processing based on a bit mask and a staged shift strategy and the EtherCAT frame receiving and transmitting control based on annular buffer area index management; on the basis of non-real-time task priority scheduling processing of a hardware timer, main circulation driven by a single-thread event and overtime monitoring of a blocking communication synchronization mechanism in combination with the timer, adaptation of an SOEM protocol stack to an EtherCAT master station operating system abstraction layer is achieved; through network scanning and communication parameter configuration, a memory management mechanism based on CoE standard mapping and a periodic position mode of a slave station, adaptation of an EtherCAT master station application layer is realized. According to the invention, through optimization and adaptation of the SOEM protocol stack, operation-system-free and microsecond-level communication jitter of the EtherCAT master station system is realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of industrial Internet, and specifically relates to a method and device for implementing an EtherCAT master station system based on a non-operating system. Background Art

[0002] With the rapid development of Industry 4.0 and intelligent manufacturing technology, industrial automation systems have put forward higher requirements for real-time communication performance. As a new generation of industrial communication solutions, industrial Ethernet technology has significantly improved communication performance while maintaining the low-cost advantage of Ethernet by introducing Ethernet technology into the field of industrial control. Among them, the EtherCAT (Ethernet for Control Automation Technology) protocol has become an important solution in the field of industrial Ethernet with its unique technical advantages. The protocol adopts a master-slave communication architecture and supports a variety of network topologies such as linear, tree, and star. Its innovative "flying read and write" data processing mechanism and distributed clock synchronization technology can achieve microsecond communication cycles and nanosecond synchronization accuracy, fully meeting the needs of high-real-time application scenarios such as industrial motion control.

[0003] The main problems with existing EtherCAT master station technology can be summarized as follows: 1. Commercial solutions are expensive and have technical limitations: Commercial EtherCAT master station systems represented by TwinCAT have expensive dedicated controllers and supporting software, and their core technologies are controlled by foreign manufacturers, which is not conducive to their promotion and application in key industrial fields. 2. Insufficient real-time performance of open source solutions: Due to the non-real-time characteristics of Windows / Linux systems, open source EtherCAT master station solutions based on general operating systems have inherent defects in task scheduling, interrupt response, memory management, etc., resulting in large communication cycle jitter, making it difficult to meet the real-time requirements of high-precision industrial control scenarios. Summary of the invention

[0004] In order to realize an EtherCAT master station system without an operating system, a first aspect of the present invention provides an implementation method of an EtherCAT master station system without an operating system, comprising: implementing the adaptation of the SOEM protocol stack to the hardware abstraction layer of the EtherCAT master station through byte order processing based on a bit mask and a phased shift strategy, and EtherCAT frame transceiver control based on a ring buffer index management; implementing the adaptation of the SOEM protocol stack to the EtherCAT master station operating system abstraction layer based on a hardware timer-based non-real-time task priority scheduling processing, a single-threaded event-driven main loop, and a blocking communication synchronization mechanism combined with a timer timeout monitoring; and implementing the adaptation of the EtherCAT master station application layer through network scanning and communication parameter configuration, a memory management mechanism based on CoE standard mapping, and a periodic position mode of a slave station.

[0005] In some embodiments of the present invention, the byte order processing based on the bit mask and phased shift strategy includes: for 16-bit data conversion: using a method combining bit mask and shift operation to perform an AND operation on the original data and 0xFF00, and then shift right 8 bits, and merge the results through an OR operation; for 32-bit data conversion: performing a 24 / 16 / 8-bit phased shift combination; for 64-bit data conversion: splitting the 64-bit data into two 32-bit data, performing 32-bit data conversion on each 32-bit data, and then merging the conversion results.

[0006] In some embodiments of the present invention, the non-real-time task priority scheduling process includes: dividing the master station tasks into high-real-time periodic communication tasks and event-driven non-real-time tasks; periodic communication tasks are used for real-time data exchange and precise motion control, and non-real-time tasks are used for instruction calculation, status monitoring and fault handling.

[0007] In some embodiments of the present invention, the blocking communication synchronization mechanism combined with the timer timeout monitoring includes: based on the blocking communication mechanism, the main station immediately enters the receiving waiting state after sending the data frame; while continuously detecting the return frame, the waiting time is monitored, and the waiting time is terminated when the waiting exceeds a preset threshold.

[0008] In some embodiments of the present invention, the memory management mechanism based on CoE standard mapping includes: dividing a byte space of fixed bits in the slave station memory, and the byte space is used to store the process data of the slave station; constructing a mapping configuration instruction based on the CoE protocol standard; configuring the PDO mapping table of the slave station through mailbox communication, and establishing a mapping relationship between the master station memory space and the slave station memory space; determining whether the slave station device is in a safe operating state, and verifying whether the mapping relationship is correct.

[0009] In some embodiments of the present invention, the periodic position mode of the slave station includes: setting the interpolation period of the position instruction; the master station sends a new position instruction to the servo drive every other interpolation period; ensuring that the period of the automatic reload register is consistent with the interpolation period.

[0010] The second aspect of the present invention provides an EtherCAT master station system implementation device based on a non-operating system, including: a first implementation module, which is used to implement the adaptation of the SOEM protocol stack to the hardware abstraction layer of the EtherCAT master station through byte order processing based on bit mask and phased shift strategy, and EtherCAT frame transceiver control based on ring buffer index management; a second implementation module, which is used to implement the adaptation of the SOEM protocol stack to the EtherCAT master station operating system abstraction layer based on non-real-time task priority scheduling processing based on hardware timer, a single-threaded event-driven main loop, and a blocking communication synchronization mechanism combined with timer timeout monitoring; a third implementation module, which is used to implement the adaptation of the EtherCAT master station application layer through network scanning and communication parameter configuration, a memory management mechanism based on CoE standard mapping, and a periodic position mode of the slave station.

[0011] The third aspect of the present invention provides an electronic device, comprising: one or more processors; a storage device for storing one or more programs, when the one or more programs are executed by the one or more processors, the one or more processors implement the EtherCAT master station system implementation method based on no operating system provided in the first aspect of the present invention.

[0012] A fourth aspect of the present invention provides a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method for implementing an EtherCAT master station system based on a non-operating system provided in the first aspect of the present invention.

[0013] The beneficial effects of the present invention are: by adopting the open source protocol stack to realize the complete EtherCAT master station function, the technical barriers of foreign manufacturers in the field of high-end industrial control are broken through, and the core technology is independently controllable. Compared with imported solutions, this solution can reduce system costs and provide an economically feasible technical path for the localization of industrial control equipment.

[0014] The innovative use of a non-operating system architecture reduces the communication jitter caused by factors such as task scheduling, interrupt response, and memory management in traditional operating systems, and achieves high real-time and low jitter performance of EtherCAT communication. According to actual measurements, the communication cycle jitter of this solution is controlled within 1μs, meeting the stringent requirements of high-precision industrial control scenarios.

[0015] A precise cycle control method based on hardware timer is proposed, which achieves microsecond-level communication cycle accuracy by directly operating hardware registers, significantly improving the timing determinism of the system. This method not only ensures the strict punctuality of the communication cycle, but also provides a reliable time reference for multi-axis synchronous control.

[0016] A flexible and efficient slave network management and control mechanism is designed to support the application requirements of various industrial control scenarios. This solution can be widely used in high-precision control fields such as motion control, industrial robots, CNC machine tools, etc., and has good market prospects and promotion value.

[0017] Through the implementation of the present invention, not only can my country's independent innovation capability in the field of industrial communication protocols be enhanced, but also reliable technical support can be provided for the localization substitution of industrial control equipment, which will effectively promote technological progress and industrial upgrading in the field of industrial automation in my country. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A basic flow chart of a method for implementing an EtherCAT master station system without an operating system in some embodiments of the present invention; Figure 2 The following is a design diagram of an EtherCAT master station system architecture based on a non-operating system in some embodiments of the present invention; Figure 3 A schematic diagram of a network driver logic structure in some embodiments of the present invention; Figure 4 is a logic block diagram of Ethernet driver in some embodiments of the present invention; Figure 5 Design diagrams for periodic tasks in some embodiments of the present invention; Figure 6 Schematic diagram of a linear topological structure in some embodiments of the present invention; Figure 7 is an application flow in some embodiments of the present invention; Figure 8 A schematic diagram of memory space mapping between a master station and a slave station in some embodiments of the present invention; Fig. 9 A schematic diagram of communication cycle and jitter verification in some embodiments of the present invention; Fig.10 It is a structural schematic diagram of an implementation device of an EtherCAT master station system based on a non-operating system in some embodiments of the present invention; Fig.11 It is a schematic diagram of the structure of an electronic device in some embodiments of the present invention. DETAILED DESCRIPTION

[0019] The principles and features of the present invention are described below in conjunction with the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0020] refer to Figure 1 and Figure 2 In the first aspect of the present invention, a method for implementing an EtherCAT master station system without an operating system is provided, comprising: S100. Adapting the SOEM protocol stack to the hardware abstraction layer of the EtherCAT master station through byte order processing based on bit mask and phased shift strategy, and EtherCAT frame transceiver control based on ring buffer index management; S200. Adapting the SOEM protocol stack to the operating system abstraction layer of the EtherCAT master station through non-real-time task priority scheduling processing based on hardware timer, single-threaded event-driven main loop, and blocking communication synchronization mechanism combined with timer timeout monitoring; S300. Adapting the application layer of the EtherCAT master station through network scanning and communication parameter configuration, memory management mechanism based on CoE standard mapping, and periodic position mode of slave stations.

[0021] It should be noted that in this embodiment, the mainstream domestic embedded platform, Rockchip RK3568, is selected as the hardware platform, making full use of its multi-core CPU and Ethernet driver (Media Access Controller, MAC) hardware resources to achieve efficient protocol processing and data transmission to realize the EtherCAT master station. As the core development framework, the system uses the SOEM open source protocol stack, which has excellent cross-platform compatibility. It is not only compatible with multiple operating systems such as Windows, Linux and INtime, but also supports the realization of complete EtherCAT communication functions on embedded hardware platforms without operating systems.

[0022] Specifically, the present invention focuses on the following tasks: first, for the RK3568 hardware platform, the adaptation of the hardware abstraction layer (OSHW) is realized, including the development of core functions such as network driver, byte order conversion and direct memory access (DMA) transmission, to ensure the efficient sending and receiving of EtherCAT frames; second, the operating system abstraction layer (OSAL) is realized in an operating system-free environment, and high-precision time management and task scheduling functions are provided through precise timer management and interrupt control; finally, a complete EtherCAT master station control framework is constructed, and application layer programs are developed to realize specific control functions such as network scanning, data interaction, real-time monitoring and cyclic synchronous position mode (CSP).

[0023] In step S100 of some embodiments of the present invention, the byte order processing based on the bit mask and phased shift strategy includes: for 16-bit data conversion: S101. Use a method combining bit mask and shift operation to perform an AND operation on the original data and 0xFF00, then shift right 8 bits, and merge the results through an OR operation; S102. For 32-bit data conversion: perform a 24 / 16 / 8-bit phased shift combination; for 64-bit data conversion: S103. Split the 64-bit data into two 32-bit data, perform 32-bit data conversion on each 32-bit data, and then merge the conversion results.

[0024] Specifically, the hardware abstraction layer is the interactive interface between the SOEM protocol stack and the underlying hardware, and is mainly responsible for the implementation of network communication services. When porting the protocol stack on the RK3568 platform, the adaptation of OSHW is the core work content, which includes two core functional modules: the byte order processing module, which is responsible for implementing the byte order conversion between the master station and the network; the network driver module, which is used to manage the underlying network communication, including Ethernet DMA transmission control and EtherCAT data frame sending and receiving processing and other functions.

[0025] The byte order processing module provides key conversion services. Since the RK3568 platform adopts the little-endian byte storage mode, that is, the low-order bytes of the data are stored at the low address of the memory, and the network transmission adopts the big-endian byte standard, that is, the low-order bytes of the data are stored at the high address of the memory, this difference requires the master station to perform byte order conversion during data transmission. Therefore, in the process of transplanting the hardware abstraction layer, it is necessary to focus on implementing the API interface related to byte order conversion to ensure the correct conversion of data between different storage modes.

[0026] For the conversion of 16-bit data, a method combining bit mask and shift operation is used to perform an AND operation on the original data and 0xFF00 and then shift it right by 8 bits. At the same time, an AND operation is performed on the original data and 0x00FF and then shifted left by 8 bits. Finally, the results are combined through an OR operation.

[0027] For the conversion of 32-bit data, a phased shift strategy is adopted: 24-bit, 16-bit, and 8-bit shift operations are performed in sequence, and the results of each stage are combined through OR operations.

[0028] The conversion of 64-bit data extends this method, using segmented processing to divide the data into high 32 bits and low 32 bits, convert them separately, and then merge them. The specific implementation includes: little-endian to big-endian conversion, converting local little-endian byte order data to network big-endian byte order, such as 0x12345678→0x78563412 conversion; big-endian to little-endian conversion, converting received network big-endian byte order data to local little-endian byte order, such as 0x78563412→0x12345678.

[0029] refer to Figure 3 and Figure 4 In step S100 of some embodiments of the present invention, the EtherCAT frame transceiver control based on the ring buffer index management is implemented to adapt the SOEM protocol stack to the hardware abstraction layer of the EtherCAT master station.

[0030] Specifically, as the core component of OSHW, the network driver module focuses on the implementation of physical layer communication services and does not involve the protocol parsing and encapsulation of EtherCAT frames. Figure 2 As shown in the figure, the buffer management mechanism needs to be implemented in the network driver module to configure the capacity of the send and receive buffers. When executing the frame sending operation, the system first allocates an idle index (idx) in the send buffer, completes the frame data loading, and sends it through the MAC controller at the physical layer; the receiving end needs to use the same index to achieve accurate mapping of the receive buffer to ensure the timing consistency of the send frame and the receive frame.

[0031] In addition, the network driver module directly interacts with the underlying network data transmission module to build a complete physical layer communication channel to realize the sending and receiving of EtherCAT frames. It abstracts four interfaces that need to be provided: initializing network ports, closing network ports, sending EtherCAT frames, and receiving EtherCAT frames.

[0032] Figure 3Describe the logic block diagram of the Ethernet controller on the RK3568 hardware platform. In this embodiment, the implementation steps of network port initialization are as follows: Pin initialization: initialize the relevant pins according to the standard transmission protocol (MII / RMII / GMII / RGMII), configure the multiplexing function of the IO pins, and ensure the correct transmission of the physical layer signal; Physical layer (Ethernet Physical Layer, PHY) chip configuration: configure the transmission mode and rate of the external PHY chip (such as 10 / 100 / 1000Mbps), complete the initialization of the control register and status register address mapping of the PHY chip, and establish a stable underlying communication link; MAC initialization: set the MAC clock and interface mode, configure the MAC address, and ensure that the MAC layer can correctly identify and process data frames; First In First Out queue (First In First Out queue) Out, FIFO) initialization: initialize the MAC's FIFO memory, set the capacity of the send and receive buffers, and clear the buffers to ensure that the memory area is in a known, clean state before use; DMA configuration: build a receive ring descriptor queue, define the source address, destination address, transmission direction and data length of the data, configure the physical address mapping of the head and tail pointer registers, activate the circular addressing mechanism of the descriptor queue, and establish a zero-copy transmission channel between the MAC and the system memory.

[0033] The implementation steps of the network port shutdown function are as follows: Disable MAC: turn off the clock gating signal of MAC, set the transmission enable disable bit and the reception enable disable bit of the MAC control register, trigger the forced stop mechanism of the transmission engine and the reception engine, and ensure the complete closure of the physical layer data frame transmission channel; DMA resource recovery: clear the address mapping of the current descriptor pointer register, reset the descriptor head and tail pointer registers to the initial state, and release the memory resources of the ring buffer; memory recovery: recycle the memory space occupied by the receive ring descriptor queue and the transmit ring descriptor queue associated with MAC, clear the related data structure, and release the occupied system resources; hardware register reset: write 0x00000001 to the MAC software reset register, start the synchronous reset sequence of the MAC internal state machine, write the hardware reset instruction (Bit15=1) to the basic control register of the PHY chip, and restore the hardware resources to the default state; pin reset: reset the multiplexed IO pins, restore the default configuration, and ensure that the hardware resources can be reused by other modules.

[0034] The implementation steps of the EtherCAT frame sending function are as follows: Data acquisition: automatically obtain the starting address and length field of the EtherCAT frame to be sent from the send ring descriptor queue in the system memory to ensure the integrity of the data frame; DMA copy: activate the DMA chain transmission engine, and write the data frame from the zero-copy ring buffer directly to the MAC send FIFO to ensure the efficiency of data transmission; physical layer transmission: call the MAC layer frame sending function in the HAL library of RK3568, set the send enable bit of the MAC control register, start the MII / RMII / GMII / RGMII interface clock synchronization, transfer the data frame from the send FIFO to the external PHY, and complete the physical layer frame transmission.

[0035] The implementation steps of the EtherCAT frame receiving function are as follows: Frame reception: Call the MAC layer frame receiving function in the HAL library of RK3568 to receive data frames from the external PHY and store them in the receiving FIFO; Data integrity check: Automatically discard error frames (CRC check failure / overlength frame / fragmented frame) through receiving filtering, obtain the starting address and data length of the correct data frame in the receiving FIFO, and ensure the integrity of the data frame; DMA copy: Trigger the data transfer request of the DMA controller, update the receiving descriptor status bit to mark the valid data area, and copy the data frame from the receiving FIFO to the system memory for further processing by the upper layer protocol stack. Through the above steps, the hardware abstraction layer realizes efficient network communication services and provides stable and reliable underlying support for the EtherCAT master station. This design not only ensures the efficient transmission of data frames, but also significantly reduces the CPU load and improves the overall performance of the system through the optimized use of DMA and FIFO.

[0036] refer to Figure 5 and Figure 6 In step S200 of some embodiments of the present invention, the non-real-time task priority scheduling processing based on the hardware timer, the main loop driven by the single-threaded event, and the blocking communication synchronization mechanism combined with the timer timeout monitoring are used to achieve the adaptation of the SOEM protocol stack to the EtherCAT master station operating system abstraction layer. Specifically, the operating system abstraction layer defines a unified interface specification, including basic data types, time management structures, and core functional interfaces such as time / timer operation APIs and thread control APIs. The main task of the operating system abstraction layer is to provide an abstract interface that is independent of the operating system for the upper protocol stack, ensuring the portability and real-time performance of the system on different platforms.

[0037] Time and timer related interfaces are the core components for implementing EtherCAT communication functions. Since SOEM uses a blocking communication mechanism, the master station immediately enters the receiving waiting state after sending the data frame, and the frame reception can usually be completed within microseconds. To ensure the reliability of communication, the system implements a timeout control mechanism, that is, while continuously detecting the return frame, the waiting time is monitored, and the waiting time is immediately terminated when the preset threshold is exceeded. The implementation of this mechanism depends on accurate time management API. In addition, the EtherCAT distributed clock synchronization function also requires accurate system time support.

[0038] To this end, in this embodiment, the 32-bit general timer counter TIMER4 of RK3568 is used to implement the system time management function. The timer frequency is set to 1MHz, that is, the timing period is 1 microsecond, and the maximum count value of the timer counter is 4294967295, which means that the timer will return to zero once every 4295 seconds (about 71.6 minutes). This configuration fully meets the needs of EtherCAT communication for high-precision time management.

[0039] Unlike the time management API, the thread-related API is an optional implementation component. The present invention is based on the RK3568 platform, divides the master station tasks into high-real-time periodic communication tasks and event-driven non-real-time tasks, and adopts a task management mechanism without an operating system architecture. Among them, the periodic communication tasks are mainly responsible for real-time data exchange and precise motion control, while the non-real-time tasks focus on operations such as instruction calculation, state monitoring and fault handling. In view of this task division feature, the present embodiment integrates non-real-time tasks into the main event loop for unified management, avoiding the system overhead caused by multi-task scheduling. This design ensures that there is no task scheduling and context switching other than periodic communication during the EtherCAT communication process, and realizes exclusive access to hardware resources, thereby achieving the performance goals of high real-time performance and low jitter.

[0040] It should be noted that in order to adapt to the operating environment without an operating system, this study has carried out targeted optimization of the protocol stack: Streamlining the thread management mechanism: In view of the fact that the system does not rely on a multi-threaded architecture, the thread management components related to the POSIX Thread specification are removed, including core functions such as thread creation, destruction and synchronization. At the same time, concurrency control mechanisms such as mutexes and semaphores are streamlined to achieve a lightweight design of the protocol stack; Optimizing the task communication architecture: The original thread call mechanism is reconstructed at the architectural level, and the atomic event flag group is used to replace the traditional message queue communication mode to ensure that the system can still maintain efficient inter-task communication and task scheduling after removing the thread management function; High-precision periodic task control: The 32-bit programmable timer counter TIMER5 is used to manage periodic communication tasks. The timer frequency is set to 24MHz, that is, the timing period is 41.67 nanoseconds, and the automatic reload register is set to support dynamic adjustment of the load value to achieve a programmable period of 50μs-10ms. In addition, in high-real-time periodic communication tasks, the present invention designs an exclusive access mechanism based on interrupt masking to mask non-essential interrupts during the execution of critical communication tasks, ensuring the atomicity and real-time responsiveness of core operations, and effectively avoiding timing jitter caused by task switching.

[0041] It can be understood that after completing the hardware abstraction and operating system abstraction of the SOEM protocol stack on the RK3568 hardware platform, the next step is to develop the EtherCAT master application layer program to realize specific control functions. The application layer is the core part of the EtherCAT master system, responsible for data interaction with slave devices and executing corresponding control logic.

[0042] In step S300 of some embodiments of the present invention, the network scanning and communication parameter configuration includes: using the RK3568 development board as the EtherCAT master station, and selecting two sets of TSVB-EtherCAT servo drivers and their matching Huada servo motors produced by Wuhan Jiutong Intelligent Technology Co., Ltd. as slave devices. Figure 5 As shown in the figure, the system adopts a linear topology. Two EtherCAT servo drives are connected in series via a network cable. The one directly connected to the master is slave 1, and the second drive is slave 2. All drives are running in cyclic synchronous position mode (CSP) to verify the EtherCAT communication function and performance of the master. The EtherCAT master application layer program needs to implement network scanning and configuration, data interaction management, and execution control logic. The application layer program flow chart is shown in the figure below. Figure 7 As shown, the specific implementation steps are as follows: After the master station is started, the EtherCAT network is first scanned to identify the connected slave devices and initialize the configuration parameters of the slaves. This process includes: Network topology discovery and device identification: The master station sends the ETG.1000 standard topology discovery broadcast frame, captures all slave response frames, parses the device physical address, and assigns a logical address to each slave; Parameter initialization: According to the type of slave device, the slave configuration register is initialized through the mailbox communication protocol, and its operating parameters (such as communication cycle, operation mode, etc.) are initialized; Status check: Ensure that all slave devices are in the pre-operational state (Pre-OperationalState) to prepare for subsequent data interaction.

[0043] refer to Figure 7 and Figure 8 In step S300 of some embodiments of the present invention, the memory management mechanism based on CoE standard mapping includes: S301. Dividing a byte space of fixed bits in the slave memory, and the byte space is used to store the process data of the slave; S302. Constructing a mapping configuration instruction based on the CoE protocol standard; configuring the PDO mapping table of the slave through mailbox communication, and establishing a mapping relationship between the master memory space and the slave memory space; S303. Determining whether the slave device is in a safe operating state, and verifying whether the mapping relationship is correct.

[0044] Specifically, after completing the network scan, the process data object (PDO) mapping of the slave station is required to realize the mapping relationship between the master station memory space and the slave station memory space. Figure 7 As shown, a 64-byte memory space is opened in the master station, and the slave station process data structure is divided in it. Through the mapping configuration instructions of the CoE (CANopen over EtherCAT) standard, the specific steps include: memory allocation: divide 64 bytes of space in the master station memory to store the slave station process data; PDO mapping: construct a mapping configuration instruction that complies with the CoE protocol standard, configure the slave station's PDO mapping table through the mailbox communication method, and establish the mapping relationship between the master station memory space and the slave station memory space; Mapping Verification: Ensure that all slave devices are in a safe operating state (Safe-Operational State) and verify whether the mapping relationship is correct. If there is an abnormality, the program will exit abnormally, otherwise continue to execute subsequent operations.

[0045] In step S300 of some embodiments of the present invention, the periodic position mode of the slave station includes: setting the interpolation period of the position instruction; the master station sends a new position instruction to the servo driver every other interpolation period; after determining that the mapping relationship is verified, the operation mode of the slave station device is set to the periodic synchronous position mode. In this mode, the master station needs to send a new position instruction to the servo driver every other interpolation period, so that the motor runs to the specified position. The specific implementation steps are as follows: Interpolation cycle setting: The selection of the interpolation cycle is related to the processing power of the master station. The shorter the interpolation cycle, the higher the position control accuracy. In this embodiment, a master station implementation scheme based on a non-operating system is used. There is no task scheduling and context switching during the EtherCAT communication process, and exclusive access to hardware resources is achieved, thereby supporting shorter interpolation cycle settings. Specifically, compared with the conventional 1ms, 500μs or 200μs cycle, this embodiment selects 100μs as the interpolation cycle; Timer configuration: Set the automatic reload register of the programmable timer counter TIMER5, and the interrupt cycle is consistent with the set interpolation cycle to ensure accurate triggering of the interpolation task; Interrupt service function: In the timer interrupt service function, the master performs periodic data exchange: writes the new period command position data to the driver, and reads the actual position data of the previous period, completing the synchronous update of the process data. Ensure that the cycle of the automatic reload register is consistent with the interpolation cycle.

[0046] refer to Fig. 9 , for the communication jitter performance evaluation of the EtherCAT master station solution proposed in the present invention, under the test condition that the interpolation period is set to 100μs, an analysis method combining multi-signal general purpose input / output (GPIO) level flipping and oscilloscope waveform capture is adopted. The specific implementation steps are as follows: Timing marking strategy: Set the GPIO pin level flipping operation at the three key nodes of periodic process data processing (trigger before data sending, trigger after data sending / before receiving, trigger after data receiving) to build a complete communication process timing marking chain. Test system configuration: Based on the hardware platform of RK3568 multi-core processor, the strict timing alignment of GPIO trigger signal and EtherCAT communication task is ensured by the precision clock synchronization module, and a 4-channel digital oscilloscope (sampling rate ≥ 2GS / s) is used for waveform acquisition and time analysis. Jitter quantification analysis: such as Fig. 9As shown in the figure, by statistically analyzing the waveform data of 1000 consecutive cycles captured by the oscilloscope, the root mean square value and the maximum deviation value of the time difference of each trigger signal in adjacent cycles are calculated. The experimental data show that under the condition of 100μs interpolation period, the time jitter of the periodic data read and write operation implemented by this scheme is effectively controlled within the range of ±1μs.

[0047] By developing an EtherCAT master application, this embodiment implements a design and implementation of an EtherCAT master system based on a non-operating system, and verifies its communication and control performance in a periodic synchronous position mode. This method not only implements the EhterCAT master function on a non-operating system platform, but also provides a high real-time, low-jitter EtherCAT master solution for the field of industrial automation.

[0048] The present invention proposes a design and implementation method of an EtherCAT master station based on a non-operating system platform, which has a shorter communication frame period and higher system stability compared to an EtherCAT master station based on a non-real-time operating system such as Windows / Linux. The achievement of this highly deterministic communication performance is mainly due to the design of the non-operating system architecture, which reduces the interference of non-real-time factors such as task scheduling, context switching, and memory management on communication performance. Through the precise control of the hardware timer and the optimized protocol stack implementation, the system can achieve a communication cycle of 100μs and suppress the communication jitter to within ±1μs. This high real-time, low-jitter communication performance provides reliable technical support for high-precision control applications such as precision motion control and multi-axis synchronization in industrial automation scenarios, and meets the stringent requirements of modern industrial control for high reliability and high real-time performance.

[0049] Example 2 refer to Fig.10 According to a second aspect of the present invention, there is provided an implementation device for an EtherCAT master station system without an operating system, comprising: a first implementation module, for implementing the adaptation of the SOEM protocol stack to the hardware abstraction layer of the EtherCAT master station through byte order processing based on a bit mask and a phased shift strategy, and EtherCAT frame transceiver control based on a ring buffer index management; a second implementation module, for implementing the adaptation of the SOEM protocol stack to the EtherCAT master station operating system abstraction layer based on a hardware timer-based non-real-time task priority scheduling processing, a single-threaded event-driven main loop, and a blocking communication synchronization mechanism combined with a timer timeout monitoring; a third implementation module, for implementing the adaptation of the EtherCAT master station application layer through network scanning and communication parameter configuration, a memory management mechanism based on CoE standard mapping, and a periodic position mode of the slave station.

[0050] Furthermore, the third implementation module includes: a division unit, used to divide a fixed-bit byte space in the slave station memory, and the byte space is used to store the process data of the slave station; a mapping unit, used to construct a mapping configuration instruction based on the CoE protocol standard; through the mailbox communication method, the PDO mapping table of the slave station is configured, and the mapping relationship between the master station memory space and the slave station memory space is established; a determination unit, used to determine whether the slave station device is in a safe operating state, and to verify whether the mapping relationship is correct.

[0051] Example 3 refer to Fig.11 According to a third aspect of the present invention, an electronic device is provided, comprising: one or more processors; a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the EtherCAT master station system implementation method based on a non-operating system according to the first aspect of the present invention.

[0052] The electronic device 500 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 501, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 502 or a program loaded from a storage device 508 into a random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the electronic device 500 are also stored. The processing device 501, the ROM 502, and the RAM 503 are connected to each other via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0053] Typically, the following devices may be connected to the I / O interface 505: an input device 506 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 507 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 508 including, for example, a hard disk, etc.; and a communication device 509. The communication device 509 may allow the electronic device 500 to communicate with other devices wirelessly or by wire to exchange data. Although Fig.11 The electronic device 500 is shown with various devices, but it should be understood that it is not required to implement or possess all the devices shown. More or fewer devices may be implemented or possessed instead. Fig.11 Each block shown in the figure may represent one device, or may represent multiple devices as required.

[0054] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through a communication device 509, or installed from a storage device 508, or installed from a ROM 502. When the computer program is executed by the processing device 501, the above functions defined in the method of the embodiment of the present disclosure are executed. It should be noted that the computer-readable medium described in the embodiment of the present disclosure can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection with one or more conductors, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In an embodiment of the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, an apparatus, or a device. In an embodiment of the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in combination with an instruction execution system, an apparatus, or a device. The program code embodied on the computer readable medium may be transmitted using any appropriate medium, including but not limited to: wire, optical cable, RF (radio frequency), etc., or any suitable combination of the foregoing.

[0055] The computer-readable medium may be included in the electronic device, or may exist independently without being installed in the electronic device. The computer-readable medium carries one or more computer programs. When the one or more programs are executed by the electronic device, the electronic device: Computer program code for performing the operations of embodiments of the present disclosure may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, Python, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on a user's computer, partially on a user's computer, as a separate software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0056] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0057] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for implementing an EtherCAT master station system without an operating system, characterized in that: include: The SOEM protocol stack is adapted to the hardware abstraction layer of the EtherCAT master station through byte order processing based on bit mask and phased shift strategy, and EtherCAT frame transmission and reception control based on ring buffer index management; Based on the hardware timer's non-real-time task priority scheduling, the single-threaded event-driven main loop, and the blocking communication synchronization mechanism combined with the timer's timeout monitoring, the SOEM protocol stack is adapted to the EtherCAT master station operating system abstraction layer; Through network scanning and communication parameter configuration, memory management mechanism based on CoE standard mapping, and periodic position mode of slave stations, the adaptation of the EtherCAT master station application layer is achieved.

2. According to the method for implementing an EtherCAT master station system without an operating system in claim 1, the byte order processing based on a bit mask and a phased shift strategy comprises: For 16-bit data conversion: use a bit mask and shift operation to perform an AND operation on the original data and 0xFF00, then shift right 8 bits, and combine the results through an OR operation; For 32-bit data conversion: perform 24 / 16 / 8-bit phased shift combinations; For 64-bit data conversion: split the 64-bit data into two 32-bit data, perform 32-bit data conversion on each 32-bit data, and then merge the conversion results.

3. According to the method for implementing an EtherCAT master station system without an operating system in claim 1, the non-real-time task priority scheduling process comprises: Divide the master station tasks into high-real-time periodic communication tasks and event-driven non-real-time tasks; Periodic communication tasks are used for real-time data exchange and precise motion control, and non-real-time tasks are used for instruction calculation, status monitoring, and fault handling.

4. According to the method for implementing an EtherCAT master station system without an operating system in claim 1, the blocking communication synchronization mechanism combined with the timer timeout monitoring comprises: Based on the blocking communication mechanism, the master station immediately enters the receiving waiting state after sending the data frame; The waiting time is monitored while continuously detecting the return frame, and the waiting time is terminated when the waiting time exceeds a preset threshold.

5. According to the method for implementing an EtherCAT master station system without an operating system as claimed in claim 1, the memory management mechanism based on CoE standard mapping comprises: Allocating a byte space of fixed bits in the slave memory, the byte space being used to store process data of the slave; Construct mapping configuration instructions based on the CoE protocol standard; Through the mailbox communication method, configure the PDO mapping table of the slave station and establish the mapping relationship between the master station memory space and the slave station memory space; Determine whether the slave device is in a safe operating state and verify whether the mapping relationship is correct.

6. According to the method for implementing an EtherCAT master station system without an operating system as claimed in claim 1, the periodic position mode of the slave station comprises: Set the interpolation cycle of the position command; every other interpolation cycle, the master station sends a new position command to the servo drive; Make sure the cycle of auto-reload register is consistent with the interpolation cycle.

7. An EtherCAT master station system implementation device based on no operating system, characterized in that: include: The first implementation module is used to realize the adaptation of the SOEM protocol stack to the hardware abstraction layer of the EtherCAT master station through byte order processing based on bit mask and phased shift strategy, and EtherCAT frame transceiver control based on ring buffer index management; The second implementation module is used for non-real-time task priority scheduling based on hardware timer, single-threaded event-driven main loop, and blocking communication synchronization mechanism combined with timer timeout monitoring to achieve the adaptation of SOEM protocol stack to the EtherCAT master station operating system abstraction layer; The third implementation module is used to achieve the adaptation of the EtherCAT master application layer through network scanning and communication parameter configuration, memory management mechanism based on CoE standard mapping, and periodic position mode of the slave.

8. The device for realizing an EtherCAT master station system without an operating system according to claim 7, characterized in that: The third implementation module includes: A division unit, used for dividing a byte space of fixed bits in the slave station memory, wherein the byte space is used for storing process data of the slave station; The mapping unit is used to construct a mapping configuration instruction based on the CoE protocol standard; configure the PDO mapping table of the slave station through the mailbox communication method, and establish a mapping relationship between the master station memory space and the slave station memory space; The determination unit is used to determine whether the slave device is in a safe operating state and to verify whether the mapping relationship is correct.

9. An electronic device, comprising: one or more processors; A storage device for storing one or more programs, when the one or more programs are executed by the one or more processors, the one or more processors implement the method for implementing the EtherCAT master station system based on no operating system as described in any one of claims 1 to 6.

10. A computer readable medium having a computer program stored thereon, wherein: When the computer program is executed by a processor, the method for implementing an EtherCAT master station system based on a non-operating system as claimed in any one of claims 1 to 6 is implemented.

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