Semiconductor structure and manufacturing method thereof, memory, storage system and electronic equipment

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, a memory, a storage system and electronic equipment, relates to the technical field of semiconductors, and aims to increase the trap density of a charge trapping layer in the semiconductor structure so as to enlarge a memory window of the semiconductor structure and improve the charge storage characteristic of the semiconductor structure. The semiconductor structure comprises a stacked structure and a channel structure penetrating through the stacked structure. The channel structure comprises a functional layer and a channel layer which are stacked in the radial direction of the channel structure. Wherein the functional layer comprises a charge trapping layer, and the charge trapping layer contains carbon elements. The semiconductor structure can be applied to a memory to realize data reading and writing operations.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof, a memory, a storage system, and an electronic device. Background Art

[0002] NAND memory is a type of non-volatile memory that does not require power to retain stored data. The growing demand for consumer electronics, cloud computing, and big data has led to a continued demand for NAND memory with larger capacity and better performance.

[0003] As conventional two-dimensional (2D) NAND memory approaches its physical limit, three-dimensional (3D) NAND memory is now playing an important role.

[0004] The three-dimensional (3D) NAND memory architecture includes a memory array and a peripheral device for controlling signals entering and exiting the memory array. How to increase the storage window of the memory and improve its data retention capability is a problem that has been studied in the field.

[0005] It should be noted that the above information disclosed in the background technology section is only used to enhance the understanding of the background technology of the technology described in this article. Therefore, the background technology may contain certain information that does not form the prior art known in this country for those skilled in the art. Summary of the invention

[0006] The embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, a memory, a storage system, and an electronic device, which are intended to increase the trap density of the charge capture layer in the semiconductor structure, thereby increasing the memory window of the semiconductor structure and improving the charge storage characteristics of the semiconductor structure.

[0007] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0008] In one aspect, a semiconductor structure is provided, comprising a stacked structure and a channel structure penetrating the stacked structure, wherein the channel structure comprises a functional layer and a channel layer stacked along a radial direction of the channel structure.

[0009] The functional layer includes a charge capture layer, and the charge capture layer contains carbon elements.

[0010] The semiconductor structure provided by the above-mentioned embodiment of the present disclosure includes carbon in the charge trapping layer, which can increase the trap density in the charge trapping layer, increase the storage window of the semiconductor structure, and thus ensure that the semiconductor structure has good performance. On the other hand, the carbon element also helps to eliminate shallow energy level traps, improve the data retention ability of the semiconductor structure, and improve the charge storage characteristics.

[0011] In some embodiments, the charge trapping layer includes a carbon-doped silicon nitride layer.

[0012] In some embodiments, the charge capture layer further includes a silicon nitride layer. The carbon-doped silicon nitride layer and the silicon nitride layer are stacked along the radial direction of the channel structure. Since the electron affinity of the carbon-doped silicon nitride layer is higher than that of the silicon nitride layer, and the band gap of the carbon-doped silicon nitride layer is lower than that of the silicon nitride layer, a potential well can be formed in the charge capture layer, which plays a role in gathering electrons, making it difficult for the electrons in the potential well to escape from the charge capture layer, which is beneficial to improving the data retention performance of the semiconductor structure.

[0013] In some embodiments, the trap density in the carbon-doped silicon nitride layer is greater than the trap density in the silicon nitride layer.

[0014] In some embodiments, the charge trapping layer includes at least one carbon-doped silicon nitride layer and at least one silicon nitride layer.

[0015] In some embodiments, the charge trapping layer includes a carbon-doped silicon nitride layer and two silicon nitride layers, wherein the carbon-doped silicon nitride layer is located between the two silicon nitride layers.

[0016] In some embodiments, the charge trapping layer includes a carbon-doped silicon nitride layer and a silicon nitride layer, wherein the carbon-doped silicon nitride layer is closer to the channel layer than the silicon nitride layer.

[0017] In some embodiments, the charge trapping layer includes a carbon-doped silicon nitride layer and a silicon nitride layer, wherein the silicon nitride layer is closer to the channel layer than the carbon-doped silicon nitride layer.

[0018] In some embodiments, the carbon content of the carbon-doped silicon nitride layer is less than or equal to 5%.

[0019] In some embodiments, in adjacent carbon-doped silicon nitride layers and silicon nitride layers, a portion of the silicon nitride layer close to the carbon-doped silicon nitride layer contains carbon elements, and along the direction from the carbon-doped silicon nitride layer to the silicon nitride layer, the concentration of carbon elements in the portion of the silicon nitride layer close to the carbon-doped silicon nitride layer gradually decreases.

[0020] In some embodiments, the functional layer further comprises a blocking layer and a tunneling layer. The charge trapping layer is located between the blocking layer and the tunneling layer, and the tunneling layer is closer to the channel layer than the charge trapping layer.

[0021] In some embodiments, the barrier layer includes a silicon oxide layer. The tunneling layer includes at least one nitrogen-doped silicon oxide layer and at least one silicon oxide layer.

[0022] On the other hand, a method for manufacturing a semiconductor structure is provided, comprising: forming a stack structure; and forming a channel structure penetrating the stack structure.

[0023] The channel structure includes a functional layer and a channel layer stacked along the radial direction of the channel structure, the functional layer includes a charge capture layer, and the charge capture layer contains carbon elements.

[0024] In some embodiments, forming a channel structure penetrating the stack structure includes: forming a charge trapping layer.

[0025] Forming a charge trapping layer includes: using a first deposition process to form a carbon-doped silicon nitride layer.

[0026] In some embodiments, the raw material in the first deposition process includes triethylamine.

[0027] In some embodiments, forming the charge trapping layer further includes: forming a silicon nitride layer using a second deposition process.

[0028] The carbon-doped silicon nitride layer and the silicon nitride layer are stacked along the radial direction of the channel structure.

[0029] In another aspect, a memory is provided, comprising: the semiconductor structure as described above and a peripheral circuit. The peripheral circuit is coupled to the semiconductor structure.

[0030] In another aspect, a storage system is provided, comprising: the storage as described above and a controller. The controller is electrically connected to the storage.

[0031] In another aspect, an electronic device is provided, comprising: a processor, and the storage system as described above. The processor is coupled to the storage system.

[0032] It can be understood that the beneficial effects that can be achieved by the semiconductor structure manufacturing method, memory, storage system and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor structure above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0034] Figure 1 A structural diagram of an electronic device provided according to some embodiments;

[0035] Figure 2 A structural diagram of a storage system provided according to some embodiments;

[0036] Figure 3 A structural diagram of a memory provided according to some embodiments;

[0037] Figure 4 for Figure 3 A magnified view of the structure of AA in the middle area;

[0038] Figure 5 A structural diagram of a functional layer provided according to some embodiments;

[0039] Figure 6 The spectrum obtained by EPR test for carbon-doped silicon nitride layer;

[0040] Figure 7 is another structural diagram of a functional layer provided according to some embodiments;

[0041] Figure 8 is another structural diagram of a functional layer provided according to some embodiments;

[0042] Fig. 9 is another structural diagram of a functional layer provided according to some embodiments;

[0043] Fig.10 is another structural diagram of a functional layer provided according to some embodiments;

[0044] Fig.11 A structural diagram of a charge trapping layer provided according to some embodiments;

[0045] Fig.12 is a flow chart of a method for manufacturing a semiconductor structure according to some embodiments;

[0046] Fig.13 for Fig.12 A structural diagram of a semiconductor structure corresponding to step S1 in the flowchart of the method for manufacturing a semiconductor structure;

[0047] Fig.14 for Fig.12 A structural diagram of a semiconductor structure corresponding to step S21 in the flowchart of the method for manufacturing a semiconductor structure;

[0048] Fig.15 for Fig.12 A structural diagram of a semiconductor structure corresponding to step S22 and step S23 in the flowchart of the method for manufacturing a semiconductor structure;

[0049] Fig.16 for Fig.12 Another structural diagram of the semiconductor structure corresponding to step S22 and step S23 in the flowchart of the method for manufacturing a semiconductor structure;

[0050] Fig.17 for Fig.12 A structural diagram of a semiconductor structure corresponding to step S3 in the flowchart of the method for manufacturing a semiconductor structure. DETAILED DESCRIPTION

[0051] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0052] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0053] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0054] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0055] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0056] In the context of this disclosure, the meanings of “on,” “above,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “above” or “over” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0057] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0058] It should be noted that, for example, 1222b / 1222 appearing in the drawings of the present disclosure indicates that component 1222b belongs to component 1222, and other similar numbers appearing in the drawings also follow the above description.

[0059] In order to facilitate the description of the various embodiments of the present disclosure, a first direction Z is introduced, and the first direction Z is the thickness direction of the semiconductor structure 1 .

[0060] like Figure 1 As shown, an embodiment of the present application provides an electronic device 1000. The electronic device 1000 may include a mobile phone, a tablet computer (pad), a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) device, an augmented reality (AR) device, etc. The embodiment of the present application does not impose any special restrictions on the specific form of the above-mentioned electronic device 1000.

[0061] In some embodiments, Figure 1 As shown, the electronic device 1000 may include a storage system 100 and a processor 200. The processor 200 is coupled to the storage system 100 to interact with the storage system 100.

[0062] Exemplarily, the processor 200 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0063] The storage system 100 is described below.

[0064] like Figure 2 As shown, the memory system 100 may include a memory 10 and a controller 20. The memory 10 and the controller 20 are electrically connected.

[0065] Exemplarily, the storage system 100 may be integrated into a memory card. The memory card may include, for example, a PC card (Personal Computer Memory Card International Association, PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), or any one of UFS.

[0066] The storage system 100 described above can also be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or Embedded Multi Media Card (eMMC) package). That is, the storage system 100 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., mobile phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0067] The storage system 100 may also be integrated into a solid state drive (SSD).

[0068] Exemplarily, the controller 20 in the storage system 100 can be configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0069] The controller 20 may also be configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, notebooks, and enterprise storage arrays.

[0070] Exemplarily, the controller 20 may be configured to manage data stored in the memory 10 and communicate with an external device (eg, a host).

[0071] The controller 20 may also be configured to control operations of the memory 10 , such as read, erase, and program operations.

[0072] The controller 20 may also be configured to manage various functions regarding data stored or to be stored in the memory 10 , including at least one of bad block management, garbage collection, logical to physical address translation, and wear leveling.

[0073] The controller 20 may also be configured to process an error correction code on data read from or written to the memory 10 .

[0074] Of course, the controller 20 may also perform any other suitable functions, such as formatting the memory 10; for another example, the controller 20 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0075] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0076] The memory 10 described above will be described below.

[0077] like Figure 3 As shown, the memory 10 may include a semiconductor structure 1 and a peripheral circuit 2. The peripheral circuit 2 is coupled to the semiconductor structure 1.

[0078] Exemplarily, the memory 10 may be a three-dimensional memory, such as a 3D NAND memory.

[0079] Exemplarily, the peripheral circuit 2 is configured to control and sense the semiconductor structure 1. The peripheral circuit 2 may be any suitable digital, analog, and / or mixed signal control and sensing circuit for supporting the operation (or work) of the semiconductor structure 1, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuit 2 may also include any other circuit compatible with advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLDs) or storage circuits (e.g., static random access memories (SRAMs)).

[0080] In some embodiments, Figure 3 As shown, the memory 10 further includes a substrate 3. The substrate 3 is disposed on a side of the semiconductor structure 1 away from the peripheral circuit 2.

[0081] Exemplarily, the substrate 3 may be a semiconductor substrate, such as a silicon (Si) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, a germanium (Ge) substrate or a silicon germanium (SiGe) substrate.

[0082] The substrate 3 may also be an insulating substrate, such as a silicon-on-insulator (SOI) substrate.

[0083] The substrate 3 may also be a conductive substrate, such as a metal substrate.

[0084] The semiconductor structure 1 is described below.

[0085] Please continue reading Figure 3 The semiconductor structure 1 includes a stack structure 11 and a channel structure 12 . The channel structure 12 penetrates the stack structure 11 .

[0086] The stacked structure 11 includes a plurality of gate layers 111 and dielectric layers 112. The gate layers 111 and dielectric layers 112 are alternately stacked along a first direction Z.

[0087] Exemplarily, for the stacking structure 11, different numbers of stacking layers correspond to different stacking heights. For example, the number of stacking layers of the stacking structure 11 may be 8 layers, 32 layers, 64 layers, 128 layers, etc. The more layers of the stacking structure 11, the higher the integration, and the more storage units formed by the stacking structure 11. The number of stacking layers and the stacking height of the stacking structure 11 can be designed according to actual storage requirements, and the present disclosure does not make any specific limitation on this.

[0088] It should be noted that Figure 3 In the figure, only two channel structures 12 are included in the semiconductor structure 1 as an example for illustration. In actual manufacturing, multiple channel structures 12 that penetrate the stacked structure 11 can be formed. The number and arrangement of the channel structures 12 can be prepared according to actual storage requirements. The area corresponding to the channel structure 12 can be called the storage area of ​​the semiconductor structure 1, and the storage area can be used to realize the storage function of the semiconductor structure 1.

[0089] like Figure 4 As shown, Figure 4 for Figure 3 The channel structure 12 includes a channel layer 121 and a functional layer 122 stacked along the radial direction of the channel structure 12 . The channel layer 121 is closer to the central axis of the channel structure 12 along the first direction Z than the functional layer 122 .

[0090] By way of example, the channel layer 121 may include polysilicon. Alternatively, the channel layer 121 may also include amorphous silicon.

[0091] The functional layer 122 includes a blocking layer 1221, a charge trapping layer 1222, and a tunneling layer 1223 which are sequentially stacked along the radial direction of the channel structure 12. The tunneling layer 1223 is closer to the channel layer 121 than the blocking layer 1221.

[0092] The charge capture layer 1222 is used to store charges.

[0093] The blocking layer 1221 is located between the gate layer 111 and the charge trapping layer 1222, which can reduce the tunneling of charges between the charge trapping layer 1222 and the gate layer 111, that is, reduce the leakage of charges in the charge trapping layer 1222 to the gate layer 111, thereby reducing the programming / erasing voltage and making the semiconductor structure 1 have better anti-fatigue characteristics.

[0094] Exemplarily, the barrier layer 1221 may include one or more film layers, and the one or more film layers may include one or more materials. For example, the barrier layer 1221 may include a silicon oxide layer.

[0095] For example, the tunneling layer 1223 may include one or more film layers, and the one or more film layers may include one or more materials. Figure 4 As shown, when the tunneling layer 1223 includes multiple film layers, the multiple film layers can be nitrogen-doped silicon oxide layer 1223a and silicon oxide layer 1223b, respectively. The number of nitrogen-doped silicon oxide layer 1223a and silicon oxide layer 1223b can be one or more, and the present disclosure does not impose any specific limitation on this. Figure 4 In the figure, the tunneling layer 1223 is only taken as an example to include two nitrogen-doped silicon oxide layers 1223a and one silicon oxide layer 1223b. The two nitrogen-doped silicon oxide layers 1223a in the tunneling layer 1223 have different nitrogen concentrations. It is understandable that there may be no obvious interface between the two nitrogen-doped silicon oxide layers 1223a in the tunneling layer 1223 with different nitrogen concentrations.

[0096] For example, the charge capture layer 1222 is usually made of an insulating material film layer with a certain trap density to capture and store charges. Figure 5 As shown, the charge trapping layer 1222 may include a silicon nitride layer 1222b.

[0097] It can be understood that when the blocking layer 1221 includes a silicon oxide layer, the charge capture layer 1222 includes a silicon nitride layer 1222b, and the tunneling layer 1223 includes a silicon oxide layer 1223b, the functional layer 122 formed by the blocking layer 1221, the charge capture layer 1222 and the tunneling layer 1223 is an oxide-nitride-oxide (ONO) structure.

[0098] The inventors of the present disclosure have found through research that when the charge capture layer 1222 includes only the silicon nitride layer 1222b, the trap density of the charge capture layer 1222 is low, which is not conducive to the semiconductor structure 1 storing more charges, and after the charge capture layer 1222 and the tunneling layer 1223 are deposited through different processes, some defects, such as shallow energy level traps, may be formed at the connection interface between the charge capture layer 1222 and the tunneling layer 1223. These defects may cause charge leakage problems, changes in the voltage threshold of the storage area in the programming state, and charge retention problems, posing a threat to the reliability of the semiconductor structure 1.

[0099] Based on this, in some embodiments, the charge capture layer 1222 further includes carbon elements.

[0100] By including carbon elements in the charge capture layer 1222, on the one hand, the trap density in the charge capture layer 1222 can be increased, ensuring that the memory window of the semiconductor structure 1 is relatively large, thereby ensuring that the semiconductor structure 1 has good performance. And the carbon element helps to eliminate shallow energy level traps and improve the charge storage characteristics. Specifically, when electronic impurities (such as floating bonds of N) are inevitably present in the charge capture layer 1222, the carbon element couples with the floating bonds of N, thereby removing the electronic impurities of N. Alternatively, when oxygen impurities are present in the charge capture layer 1222, the reducing property of the carbon element can be used to remove the oxygen impurities.

[0101] It should be noted that the traps in the charge capture layer 1222 include deep energy level traps and shallow energy level traps. Since the shallow energy level traps have a weaker binding ability for charges (electrons), it is difficult to effectively store charges (electrons) in the charge capture layer 1222. By including carbon elements in the charge capture layer 1222, the trap density in the charge capture layer 1222 can be increased while the number of shallow energy level traps in the charge capture layer 1222 can be reduced, that is, the proportion of shallow energy level traps in the charge capture layer 1222 can be reduced.

[0102] For example, Figure 7 to Figure 10 As shown, the film layer containing carbon in the charge trapping layer 1222 may be a carbon-doped silicon nitride layer 1222a, wherein the trap density of the carbon-doped silicon nitride layer 1222a is greater than the trap density of the silicon nitride layer 1222b.

[0103] Taking the carbon-doped silicon nitride layer 1222 a as an example, an EPR test is performed on the carbon-doped silicon nitride layer 1222 a to detect unpaired electrons in the carbon-doped silicon nitride layer 1222 a.

[0104] It should be noted that EPR (Electron Paramagnetic Resonance) is a method used to study magnetic materials containing one or more unpaired electrons, which provides microscopic information on electrons, orbits, atomic nuclei, etc.

[0105] like Figure 6 As shown, Figure 6 The spectrum diagram is obtained by performing an EPR (electron paramagnetic resonance) test on the carbon-doped silicon nitride layer 1222a, wherein the horizontal axis represents the magnetic field intensity applied to the carbon-doped silicon nitride layer 1222a during the EPR test, and the vertical axis represents the relative intensity. Figure 6 The EPR spectrum of the carbon-doped silicon nitride layer 1222a shown in FIG. 1 has peaks and valleys. The number of unpaired electrons in the carbon-doped silicon nitride layer 1222a is characterized by the relative intensity difference between the peaks and valleys. Figure 6 The relative intensity difference between the mid-wave peak and the mid-wave trough is large, so there are a large number of unpaired electrons in the carbon-doped silicon nitride layer 1222a, that is, the carbon-doped silicon nitride layer 1222a has a large trap density, ensuring that the memory window of the semiconductor structure 1 is relatively large, thereby ensuring that the semiconductor structure 1 has good performance.

[0106] It should be noted that the above-mentioned "relative intensity" is obtained by differentiating the electromagnetic wave signal intensity obtained during the EPR test. Differentiating the signal intensity of the electromagnetic wave obtained by the EPR test can amplify the difference between the effective signal and the background noise in the EPR test, which is convenient for subsequent data analysis.

[0107] In some embodiments, Figure 7 As shown, the charge trapping layer 1222 may be a single film layer structure, namely, including a carbon-doped silicon nitride layer 1222a.

[0108] It should be noted that the above-mentioned “single film layer structure” means that the charge trapping layer 1222 includes only one film layer along the radial direction of the channel structure 12. The following description of the “single film layer structure” also follows this description and will not be repeated.

[0109] Exemplarily, the carbon content of the carbon-doped silicon nitride layer 1222a is less than or equal to 5%.

[0110] For example, the carbon content of the carbon-doped silicon nitride layer 1222a can be 5%, 4.8%, 4.5%, 4.3%, 4%, 3.9%, 3.6%, 3.3%, 3%, 2.8%, 2.5%, 2.3%, 2%, 1.8%, 1.5%, 1.2%, 1%, 0.8%, 0.5% or 0.3%.

[0111] In other embodiments, Figure 8 to Figure 10As shown, the charge trapping layer 1222 may be a composite film structure, for example, including a carbon-doped silicon nitride layer 1222 a and a silicon nitride layer 1222 b , and the carbon-doped silicon nitride layer 1222 a and the silicon nitride layer 1222 b are stacked along the radial direction of the channel structure 12 .

[0112] It should be noted that the above-mentioned “composite film layer structure” means that the charge capture layer 1222 includes multiple film layers along the radial direction of the channel structure 12. The following description of the “composite film layer structure” also follows this description and will not be repeated.

[0113] When the charge capture layer 1222 is a composite film structure, the charge capture layer 1222 includes at least one carbon-doped silicon nitride layer 1222a and at least one silicon nitride layer 1222b. The carbon-doped silicon nitride layer 1222a and the silicon nitride layer 1222b are alternately arranged.

[0114] By setting the charge capture layer 1222 to a composite film layer structure including a carbon-doped silicon nitride layer 1222a and a silicon nitride layer 1222b, since the electron affinity of the carbon-doped silicon nitride layer 1222a is higher than the electron affinity of the silicon nitride layer 1222b, and the band gap (Band gap) of the carbon-doped silicon nitride layer 1222a is lower than the band gap (Band gap) of the silicon nitride layer 1222b, a potential well can be formed in the charge capture layer 1222, which plays a role in gathering electrons, making it difficult for the electrons in the potential well to escape from the charge capture layer 1222, which is beneficial to improving the data retention performance of the semiconductor structure 1.

[0115] It should be noted that the band gap refers to the width of an energy band, and its unit is electron volt (ev). The energy levels of electrons in solids are discontinuously distributed, thus forming some discontinuous energy bands. The energy band where free electrons exist is called the conduction band. To become free electrons, bound electrons must obtain enough energy to jump from the valence band to the conduction band. The minimum value of this energy is the band gap.

[0116] Electron affinity refers to the energy value between the bottom of the semiconductor conduction band and the vacuum energy level, which is used to characterize the difficulty of electron escape. The smaller the electron affinity, the easier it is for electrons to escape.

[0117] For example, the charge trapping layer 1222 may include a carbon-doped silicon nitride layer 1222a and a silicon nitride layer 1222b. Figure 8 As shown, the carbon-doped silicon nitride layer 1222a is closer to the tunneling layer 1223 than the silicon nitride layer 1222b. Since the channel layer 121 is located on the side of the tunneling layer 1223 away from the charge capture layer 1222, that is, the channel layer 121 and the tunneling layer 1223 are located on the same side of the charge capture layer 1222, the carbon-doped silicon nitride layer 1222a is also closer to the channel layer 121 than the silicon nitride layer 1222b.

[0118] For example, Fig. 9 As shown, the silicon nitride layer 1222b is closer to the tunneling layer 1223 than the carbon-doped silicon nitride layer 1222a. Since the channel layer 121 is located on the side of the tunneling layer 1223 away from the charge capture layer 1222, that is, the channel layer 121 and the tunneling layer 1223 are located on the same side of the charge capture layer 1222, the silicon nitride layer 1222b is also closer to the channel layer 121 than the carbon-doped silicon nitride layer 1222a.

[0119] The charge trapping layer 1222 may also include a carbon-doped silicon nitride layer 1222a and two silicon nitride layers 1222b. Fig.10 As shown, the carbon-doped silicon nitride layer 1222a is located between the two silicon nitride layers 1222b.

[0120] For example, Fig.11 As shown, when the charge capture layer 1222 is a composite film structure and includes a carbon-doped silicon nitride layer 1222a and a silicon nitride layer 1222b, in the adjacent carbon-doped silicon nitride layer 1222a and the silicon nitride layer 1222b, part of the carbon element in the carbon-doped silicon nitride layer 1222a will diffuse into the silicon nitride layer 1222b, that is, the part of the silicon nitride layer 1222b close to the carbon-doped silicon nitride layer 1222a (i.e. Fig.11 The region BB) shown contains carbon.

[0121] Furthermore, in region BB, the concentration of carbon element gradually decreases along the direction from the carbon-doped silicon nitride layer 1222 a to the silicon nitride layer 1222 b .

[0122] The following is an explanation of the method for manufacturing the semiconductor structure 1 .

[0123] like Fig.12 As shown, Fig.12 FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure 1 according to some embodiments. It can be understood that: Fig.12 The method for manufacturing the semiconductor structure 1 shown in is not exclusive and may also be Fig.12 Other steps are performed before, after or between any steps in the method for manufacturing the semiconductor structure 1 shown.

[0124] The method for manufacturing the semiconductor structure 1 includes the following steps S1 to S3 .

[0125] S1: forming an initial stacking structure 11 ′.

[0126] like Fig.13 As shown, Fig.13 for Fig.12FIG. 1 is a structural diagram of the semiconductor structure 1 corresponding to step S1 in the flowchart of the method for manufacturing the semiconductor structure 1 in FIG.

[0127] Exemplarily, the initial stacked structure 11' may be formed by a deposition process. For example, the deposition process may be a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD), a sputtering process, an atomic layer deposition process (ALD), a plasma-enhanced chemical vapor deposition process (PECVD), or an organic metal chemical vapor deposition process (MOCVD).

[0128] Please continue reading Fig.13 The initial stacked structure 11 ′ includes sacrificial layers 113 and dielectric layers 112 alternately stacked along a first direction Z.

[0129] The above-mentioned “alternating stacking” means that, in the first direction Z, a plurality of dielectric layers 112 and sacrificial layers 113 are stacked and arranged in an alternating manner. For example, along the first direction Z, a dielectric layer 112 is first arranged, a sacrificial layer 113 is then arranged on the dielectric layer 112, and then another dielectric layer 112 is arranged on the sacrificial layer 113, and this cycle is repeated to form an initial stacking structure 11'.

[0130] It should be noted that Fig.13 The number of dielectric layers 112 and sacrificial layers 113 is only for illustration, and the embodiments of the present disclosure do not impose any limitation on the number of dielectric layers 112 and sacrificial layers 113 .

[0131] By way of example, the material used to form the dielectric layer 112 may be an oxide, such as silicon oxide. The material used to form the sacrificial layer 113 may be a nitride, such as silicon nitride.

[0132] After the initial stacking structure 11' is formed, the method for manufacturing the semiconductor structure 1 in this embodiment further includes:

[0133] S2 . Forming a channel structure 12 penetrating the initial stacked structure 11 ′.

[0134] The channel structure 12 includes a functional layer 122 and a channel layer 121 stacked along the radial direction of the channel structure 12. The functional layer 122 includes a charge trapping layer 1222, and the charge trapping layer 1222 contains carbon elements.

[0135] The above step S2 is described in detail below.

[0136] Please continue reading Fig.12 , and combined with Figure 14 to Figure 16 , Fig.14 for Fig.12 A structural diagram of the semiconductor structure corresponding to step S21 in the flowchart of the method for manufacturing a semiconductor structure, Fig.15 and Fig.16 for Fig.12 The structure diagram of the semiconductor structure 1 corresponding to step S22 and step S23 in the flowchart of the method for manufacturing a semiconductor structure. It should be noted that, in order to facilitate the description of the structure of the channel structure 12, Fig.15 and Fig.16 for Fig.14 Structural diagram after the channel structure 12 is formed in the middle region CC.

[0137] Step S2 in the method for manufacturing the semiconductor structure 1 includes:

[0138] S21: Fig.14 As shown, a channel hole CH is formed penetrating the initial stacked structure 11 ′.

[0139] Exemplarily, the channel hole CH may be formed by using a plasma etching process.

[0140] After forming the channel hole CH penetrating the initial stacked structure 11 ′, step S2 in this embodiment further includes:

[0141] S22 : forming the functional layer 122 of the channel structure 12 in the channel hole CH.

[0142] Please continue reading Fig.12 , and combined with Fig.15 and Fig.16 , the above step S22 specifically includes:

[0143] S221: forming a barrier layer 1221 in the channel hole CH. The barrier layer 1221 covers the sidewall of the channel hole CH.

[0144] Exemplarily, the process of forming the barrier layer 1221 includes, but is not limited to, a chemical vapor deposition process (CVD, Chemical Vapor Deposition), a physical vapor deposition process (PVD, Physical Vapor Deposition) and an atomic layer deposition process (ALD).

[0145] After forming the barrier layer 1221, step S22 in this embodiment further includes:

[0146] S222: forming a charge trapping layer 1222 in the channel hole CH. The charge trapping layer 1222 covers the surface of the blocking layer 1221.

[0147] In some embodiments, please refer to Fig.15 The charge capture layer 1222 is a single film structure, that is, it includes a carbon-doped silicon nitride layer 1222a. The step S222 of forming the charge capture layer 1222 includes:

[0148] S222a: Using a first deposition process, a carbon-doped silicon nitride layer 1222a is formed.

[0149] For example, the first deposition process may be an atomic layer deposition process (ALD). The raw material gas forms the carbon-doped silicon nitride layer 1222a through the atomic layer deposition process.

[0150] Exemplarily, the raw material gas refers to a gaseous raw material. For example, the raw material gas may include a gas obtained by gasifying a liquid raw material at room temperature and pressure, a gas that is gaseous at room temperature and pressure, and the like.

[0151] Exemplarily, the raw materials for forming the carbon-doped silicon nitride layer 1222a may include chlorosilane gas, nitriding gas, and triethylamine. The chlorosilane gas may be, for example, hexachlorodisilane (Si 2 Cl 6 , referred to as: HCDS) gas. The nitriding gas can be, for example, ammonia (NH 3 ).

[0152] It should be noted that when forming the carbon-doped silicon nitride layer 1222a, the content of carbon in the carbon-doped silicon nitride layer 1222a can be adjusted by adjusting the content of triethylamine in the raw material for forming the carbon-doped silicon nitride layer 1222a, thereby adjusting the storage performance of the carbon-doped silicon nitride layer 1222a.

[0153] In other embodiments, Fig.16 As shown, the charge capture layer 1222 is a composite film structure, that is, it includes at least one carbon-doped silicon nitride layer 1222a and at least one silicon nitride layer 1222b. The step S222 of forming the charge capture layer 1222 includes S222a and S222b.

[0154] In this embodiment, the method of forming the carbon-doped silicon nitride layer 1222a by step S222a and Fig.15 Step S222a in the illustrated embodiment is the same and will not be described again.

[0155] S222 b : using a second deposition process to form a silicon nitride layer 1222 b , the carbon-doped silicon nitride layer 1222 a and the silicon nitride layer 1222 b are stacked along the radial direction of the channel structure 12 .

[0156] It should be noted that Fig.16 In the embodiment, the method for manufacturing the charge capture layer 122 is described by taking the example that the charge capture layer 1222 includes a carbon-doped silicon nitride layer 1222a and a silicon nitride layer 1222b, and the silicon nitride layer 1222b is closer to the tunneling layer 1223 than the carbon-doped silicon nitride layer 1222a. However, the embodiments of the present disclosure are not limited thereto. For example, the charge capture layer 1222 may include a carbon-doped silicon nitride layer 1222a and a silicon nitride layer 1222b, and the carbon-doped silicon nitride layer 1222a is closer to the tunneling layer 1223 than the silicon nitride layer 1222b; for another example, the charge capture layer 1222 may also include a carbon-doped silicon nitride layer 1222a and two silicon nitride layers 1222b. The carbon-doped silicon nitride layer 1222a is located between the two silicon nitride layers 1222b.

[0157] For example, the second deposition process may be an atomic layer deposition (ALD) process. The raw material gas forms the silicon nitride layer 1222 b through the atomic layer deposition process.

[0158] Exemplarily, the raw materials for forming the silicon nitride layer 1222b may include chlorosilane gas and nitriding gas. The chlorosilane gas may be, for example, hexachlorodisilane (Si 2 Cl 6 , referred to as: HCDS) gas. The nitriding gas can be, for example, ammonia (NH 3 ). It is understood that the raw material for forming the silicon nitride layer 1222b does not contain carbon (C) element.

[0159] After forming the charge trapping layer 1222, step S22 in this embodiment further includes:

[0160] S223: forming a tunneling layer 1223 in the channel hole CH. The tunneling layer 1223 covers the surface of the charge trapping layer 1222.

[0161] Exemplarily, the process of forming the tunneling layer 1223 includes, but is not limited to, a chemical vapor deposition process (CVD, Chemical Vapor Deposition), a physical vapor deposition process (PVD, Physical Vapor Deposition) and an atomic layer deposition process (ALD).

[0162] After forming the functional layer 122 of the channel structure 12 in the channel hole CH, the above step S2 (forming the channel structure 12 penetrating the initial stacked structure 11 ′) further includes:

[0163] S23 : forming a channel layer 121 of the channel structure 12 in the channel hole CH.

[0164] After forming the channel structure 12 penetrating the stacked structure 11, please refer to Fig.12 , and combined with Fig.17 , Fig.17 for Fig.12 The semiconductor structure manufacturing method of the semiconductor structure 1 further includes:

[0165] S3: Fig.17 As shown, the sacrificial layer 113 in the initial stacked structure 11 ′ is removed, and a gate layer 112 is formed in the cavity formed after the sacrificial layer 113 is removed.

[0166] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, It is characterized in that include: Stacked structure; A channel structure running through the stacked structure, the channel structure comprising a functional layer and a channel layer stacked along a radial direction of the channel structure; Wherein, the functional layer comprises a charge capture layer, and the charge capture layer contains carbon elements.

2. The semiconductor structure according to claim 1, It is characterized in that The charge trapping layer includes a carbon-doped silicon nitride layer.

3. The semiconductor structure according to claim 2, It is characterized in that The charge trapping layer further comprises a silicon nitride layer; The carbon-doped silicon nitride layer and the silicon nitride layer are stacked along the radial direction of the channel structure.

4. The semiconductor structure according to claim 3, It is characterized in that The trap density in the carbon-doped silicon nitride layer is greater than the trap density in the silicon nitride layer.

5. The semiconductor structure according to claim 3, It is characterized in that The charge trapping layer comprises at least one carbon-doped silicon nitride layer and at least one silicon nitride layer; The carbon-doped silicon nitride layers and the silicon nitride layers are arranged alternately.

6. The semiconductor structure according to claim 5, It is characterized in that The charge trapping layer includes a carbon-doped silicon nitride layer and two silicon nitride layers; The carbon-doped silicon nitride layer is located between the two silicon nitride layers.

7. The semiconductor structure according to claim 5, It is characterized in that The charge trapping layer includes a carbon-doped silicon nitride layer and a silicon nitride layer; The carbon-doped silicon nitride layer is closer to the channel layer than the silicon nitride layer.

8. The semiconductor structure according to claim 5, It is characterized in that The charge trapping layer includes a carbon-doped silicon nitride layer and a silicon nitride layer; The silicon nitride layer is closer to the channel layer than the carbon-doped silicon nitride layer.

9. The semiconductor structure according to any one of claims 2 to 8, It is characterized in that The carbon content of the carbon-doped silicon nitride layer is less than or equal to 5%.

10. The semiconductor structure according to any one of claims 3 to 8, It is characterized in that In the adjacent carbon-doped silicon nitride layer and the silicon nitride layer, a portion of the silicon nitride layer close to the carbon-doped silicon nitride layer contains carbon elements, and along the direction from the carbon-doped silicon nitride layer to the silicon nitride layer, the concentration of carbon elements in the portion of the silicon nitride layer close to the carbon-doped silicon nitride layer gradually decreases.

11. The semiconductor structure according to any one of claims 1 to 8, It is characterized in that The functional layer also includes a barrier layer and a tunneling layer; The charge trapping layer is located between the blocking layer and the tunneling layer, and the tunneling layer is closer to the channel layer than the charge trapping layer.

12. The semiconductor structure according to claim 11, It is characterized in that The barrier layer comprises a silicon oxide layer; The tunneling layer includes at least one nitrogen-doped silicon oxide layer and at least one silicon oxide layer.

13. A method for manufacturing a semiconductor structure, It is characterized in that include: forming a stacked structure; forming a channel structure penetrating the stacked structure; The channel structure includes a functional layer and a channel layer stacked along a radial direction of the channel structure, the functional layer includes a charge capture layer, and the charge capture layer contains carbon elements.

14. The method for manufacturing a semiconductor structure according to claim 13, It is characterized in that The forming of the channel structure penetrating the stacked structure includes: forming the charge trapping layer; The forming of the charge trapping layer comprises: A first deposition process is used to form a carbon-doped silicon nitride layer.

15. The method for manufacturing a semiconductor structure according to claim 14, It is characterized in that The raw material in the first deposition process includes triethylamine.

16. The method for manufacturing a semiconductor structure according to claim 14 or 15, It is characterized in that The forming of the charge trapping layer further includes: forming a silicon nitride layer using a second deposition process; Wherein, the carbon-doped silicon nitride layer and the silicon nitride layer are stacked along the radial direction of the channel structure.

17. A memory, It is characterized in that include: The semiconductor structure according to any one of claims 1 to 12; The peripheral circuit is coupled to the semiconductor structure.

18. A storage system, It is characterized in that include: The memory as claimed in claim 17; A controller is electrically connected to the memory.

19. An electronic device, It is characterized in that include: A processor, and the storage system as claimed in claim 18, wherein the processor is coupled to the storage system.

Images