Thin film transistor, manufacturing method of thin film transistor, memory and reading method of memory
By using electrode materials with asymmetric metal work function in thin film transistors, the problem of crosstalk current in memory arrays cannot be suppressed is solved, higher read margins and storage density are achieved, and power consumption is reduced.
Patent Information
- Application Number
- CN202510211403.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2025-06-06
AI Technical Summary
When the existing thin film transistors (TFTs) form a memory array, due to the symmetry of the source and drain currents, the crosstalk current cannot be effectively suppressed during reading.
The electrode material with metal work function asymmetry is used as the source and drain of the thin film transistor. By forming energy band bending to different degrees, the potential barriers seen by carriers when passing through the electrodes in different directions are different, thereby achieving asymmetry of source and drain current.
Significantly suppress crosstalk current during read operation, improve read margin, increase array storage units, and reduce power consumption in read operation.
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Abstract
Description
Technical Field
[0001] The present application belongs to the technical field of electronic devices, and in particular, relates to a thin film transistor and a manufacturing method thereof, a memory and a reading method thereof. Background Art
[0002] In the development of modern electronic technology, thin film transistors (TFTs) have been widely used in various electronic devices due to their unique structure and electrical properties. Especially in the field of memory array related technology, thin film transistors are key components for building memory cells. However, the source-drain current of existing thin film transistors is symmetrical, that is, the currents in different directions of the source and drain have the same transfer characteristics and output characteristics, resulting in the inability to effectively suppress the crosstalk current of the memory array composed of such thin film transistors when reading. Summary of the invention
[0003] The embodiments of the present application provide a thin film transistor and a method for manufacturing the same, a memory and a method for reading the same, so as to at least solve the problem in the related art that the symmetry of the source-drain current of the thin film transistor causes the crosstalk current of the storage array based on the thin film transistor to be unable to be effectively suppressed during reading.
[0004] In a first aspect, an embodiment of the present application provides a thin film transistor, comprising: a first electrode, a first dielectric layer, and a second electrode stacked in sequence, wherein the first electrode, the first dielectric layer, and the second electrode are all arranged outside the thin film transistor;
[0005] The first electrode is made of a first metal material, and the second electrode is made of a second metal material. The first metal material and the second metal material have different work functions.
[0006] In a second aspect, an embodiment of the present application provides a method for manufacturing a thin film transistor, the method for manufacturing the thin film transistor as described in any embodiment of the first aspect, the method comprising:
[0007] A first electrode, a first dielectric layer, and a second electrode are stacked in sequence on a substrate, wherein the first electrode is made of a first metal material, and the second electrode is made of a second metal material, and the first metal material and the second metal material have different work functions;
[0008] A columnar hole is formed at the center of the first electrode, the first dielectric layer and the second electrode, wherein the bottom of the columnar hole extends to the substrate;
[0009] forming a semiconductor layer on the sidewall of the columnar hole, and electrically connecting the semiconductor layer to the first electrode and the second electrode;
[0010] A second dielectric layer is disposed along the columnar hole, the surface of the semiconductor layer and the top of the second electrode;
[0011] The columnar hole is filled with a gate column, and a gate substrate is formed on the top of the gate column, and the gate column and the gate substrate are defined as a gate.
[0012] In a third aspect, an embodiment of the present application provides a memory, wherein a memory array of the memory includes a plurality of memory cells, each of the memory cells includes: a write transistor, a read transistor, a write word line, a write bit line, a read word line, and a read bit line;
[0013] At least one of the write transistor and the read transistor is a thin film transistor as described in any embodiment of the first aspect;
[0014] The write transistor is configured to write data;
[0015] The read transistor is configured to read data.
[0016] In a fourth aspect, an embodiment of the present application provides a method for reading a memory, the method for reading the memory as described in any embodiment of the third aspect, the method comprising:
[0017] The read word line corresponding to the read transistor of the storage unit to be read in the memory is configured to be a first voltage, and the voltages of the other read word lines are maintained at a second voltage; wherein the first voltage is a ground voltage and the second voltage is a power supply voltage, or the first voltage is a power supply voltage and the second voltage is a ground voltage;
[0018] After a preset time, the voltage change on the read bit line is detected. When the voltage change on the read bit line is detected to be greater than the first difference voltage, the read data is the first stored data; when the voltage change on the read bit line is detected to be less than the first difference voltage, the read data is the second stored data; the first difference voltage is between the first voltage and the second voltage; the preset time is set to be greater than the time required for the voltage on the read bit line to read the first stored data to change to be greater than the first difference voltage, and less than the time required for the voltage on the read bit line to read the second stored data to change to be greater than the first difference voltage;
[0019] After the data is read, all read word lines and read bit lines are precharged to a second voltage.
[0020] In the thin film transistor and its manufacturing method, memory and its reading method of the embodiments of the present application, the source and drain of the vertical thin film transistor adopt electrode materials with asymmetric metal work function, which can form different degrees of band bending when in contact with the channel material, so that the potential barrier seen by the carrier when entering the source through the electrode is different from the potential barrier seen when entering the drain, that is, the transfer characteristics of the source-drain current of the transistor in different directions are different. DS -V GIt is asymmetric and the output response I DS -V DS Therefore, when the thin film transistor is used as the read transistor of the gain unit, the crosstalk current during the read operation can be significantly suppressed, a larger read margin can be achieved, and the number of array storage cells can be increased, and the power consumption of the read operation can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0022] Figure 1 is a schematic structural diagram of an exemplary thin film transistor in related art;
[0023] Figure 2 is a schematic structural diagram of a thin film transistor provided in an embodiment of the present application;
[0024] Figure 3 is a schematic diagram of a transfer characteristic curve of a vertical source-drain asymmetric thin film transistor according to an embodiment of the present application;
[0025] Figure 4 is a schematic diagram of an output characteristic curve of a vertical source-drain asymmetric thin film transistor according to an embodiment of the present application;
[0026] Figure 5 It is a schematic diagram of a process for manufacturing a thin film transistor provided in an embodiment of the present application;
[0027] Figure 6 It is a schematic flow chart of another method for manufacturing a thin film transistor provided in an embodiment of the present application;
[0028] Figure 7 is a schematic diagram of several possible storage units of a memory structure based on a thin film transistor according to an embodiment of the present application;
[0029] Figure 8 is a possible actual structural diagram of a storage unit based on a thin film transistor according to an embodiment of the present application;
[0030] Fig. 9 It is a flowchart of a method for reading a memory provided in an embodiment of the present application;
[0031] Fig. 10A A gain unit storage array structure composed of 2T0C storage units and a read operation schematic diagram provided in an embodiment of the present application;
[0032] Fig. 10BIt is another gain unit storage array structure composed of 2T0C storage units and a schematic diagram of a read operation provided in an embodiment of the present application;
[0033] Fig.11 is a schematic diagram of the suppression effect of a memory array based on a thin film transistor according to an embodiment of the present application on a crosstalk current;
[0034] Fig.12 It is a schematic diagram of the effect of increasing the number of array storage cells by a thin film transistor-based storage array according to an embodiment of the present application.
[0035] Reference numerals:
[0036] Thin film transistor 10, gate 101, gate substrate 1010, gate pillar 1011, second dielectric layer 102, second electrode 103, semiconductor layer 104, first dielectric layer 105, first electrode 106, substrate 107, connecting electrode 108, memory cell 20, memory array 21, write transistor 201, read transistor 202, write word line 203, first write word line 2031, mth write word line 203m, write bit line 204, first write bit line 2041, nth write bit line 204n, read word line 205, first read word line 2051, mth read word line 205m, read bit line 206, first read bit line 2061, nth read bit line 206n. DETAILED DESCRIPTION
[0037] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.
[0038] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.
[0039] In the development of modern electronic technology, thin film transistors (TFTs) have been widely used in various electronic devices due to their unique structure and electrical properties. Especially in the field of memory array related technology, thin film transistors are the key components for building memory cells.
[0040] Figure 1 FIG. 1 shows a schematic diagram of the structure of a thin film transistor in an exemplary related art. Figure 1 As shown, the first electrode 106' and the second electrode 103' of the thin film transistor are made of the same material, so the source-drain current of the thin film transistor is symmetrical, that is, the currents in different directions at the source and drain ends have the same transfer characteristics and output characteristics, resulting in that the crosstalk current of the 2T0C (two transistors without capacitor) storage array composed of such thin film transistors cannot be effectively suppressed during reading.
[0041] In order to solve the problems of the related art, the embodiments of the present application provide a thin film transistor and a manufacturing method thereof, a memory and a reading method thereof.
[0042] The thin film transistor provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.
[0043] refer to Figure 2 , is a schematic diagram of the structure of a thin film transistor 10 according to an embodiment of the present application. Figure 2 As shown, the thin film transistor 10 is composed of a gate 101, a first electrode 106, a second electrode 103, a semiconductor layer 104, a first dielectric layer 105 and a second dielectric layer 102. The first electrode 106, the first dielectric layer 105 and the second electrode 103 are stacked in sequence and are all arranged outside the thin film transistor 10.
[0044] Specifically, the gate 101 includes a gate substrate 1010 and a gate column 1011, wherein the gate substrate 1010 is disposed on the top of the thin film transistor 10 and does not cover the entire top, and the gate column 1011 is a column extending from the center of the gate substrate 1010 to the bottom of the thin film transistor 10; the semiconductor layer 104 surrounds the side wall of the gate column 1011 and is electrically connected to the first electrode 106 and the second electrode 103 respectively; the second dielectric layer 102 is disposed on the top of the semiconductor layer 104 and the second electrode 103 along the inner wall of the gate column 1011 and is located between the semiconductor layer 104 and the second electrode 103. The first electrode 106 and the second electrode 103 are respectively the source and drain, or the drain and the source, of the thin film transistor 10; the first electrode 106 is located outside the bottom of the thin film transistor 10, and the second electrode 103 is located outside the thin film transistor 10 and between the gate substrate 1010 and the first electrode 106, close to the gate substrate 1010; the first dielectric layer 105 is arranged between the first electrode 106 and the second electrode 103, and is used to separate the first electrode 106 and the second electrode 103.
[0045] As an optional embodiment, the first electrode 106 is made of a first metal material, and the second electrode 103 is made of a second metal material, and the first metal material and the second metal material have different work functions.
[0046] Thus, the source and drain of the thin film transistor 10 use electrode materials with asymmetric metal work functions, which can form different degrees of energy band bending while in contact with the channel material, so that the potential barrier seen by the carrier when entering the source through the electrode is different from the potential barrier seen when entering the drain.
[0047] Figure 3 FIG. 1 shows a transfer characteristic curve of the thin film transistor 10. Figure 3 As shown, taking n-type device as an example, V DS Voltage applied to the high work function electrode will cause I DS -V G The threshold voltage of the transfer characteristic is negative, and the same V DS Voltage applied to the electrode with low work function will cause I DS -V G The threshold voltage of the transfer characteristic is positive; it should be understood that this trend should be completely opposite on a p-type device, that is, when voltages (V DS ), the corresponding I DS -V G The transfer characteristics respond differently.
[0048] Furthermore, Figure 41 shows the output characteristic curve of the thin film transistor 10. Figure 4 As shown, when the same gate voltage V is applied to the transistor structure G When DS -V DS The output response is different.
[0049] That is to say, the source and drain electrodes of the thin film transistor 10 of this embodiment are made of metal materials with different work functions, so that the transfer characteristics I of the source and drain currents of the thin film transistor 10 in different directions are different. DS -V G It is asymmetric and the output response I DS -V DS It can be seen that compared with the traditional vertical thin film transistor source and drain electrodes using metal work function symmetrical electrode materials, the source (i.e., without voltage V DS The metal work function of the electrode material will substantially affect I DS -V G The threshold voltage of the transfer characteristic. Thus, other problems related to adjusting the threshold voltage, such as the negative threshold voltage of high-mobility n-type materials, can be solved. Furthermore, when the thin film transistor 10 is used as a read transistor of the gain unit memory, the crosstalk current during reading can be suppressed, the read margin can be improved, and the number of memory array units can be increased.
[0050] Furthermore, the present application also provides a method for manufacturing a thin film transistor. It should be noted that the method for manufacturing a thin film transistor can be used to manufacture the thin film transistor 10 of any of the above embodiments.
[0051] In the related art, for the manufacturing process of planar source-drain asymmetric thin film transistors, the planar source-drain asymmetric thin film transistor structure has a source and drain in the same plane. When the source and drain are made of different metals, metal plating needs to be performed twice, and the manufacturing process is more complicated than the traditional source-drain symmetric thin film transistor. Therefore, in this embodiment, a vertical source-drain asymmetric thin film transistor is used. Since its source and drain are naturally not in the same plane, no extra process steps are required. In addition, the manufacturing method of the thin film transistor in this embodiment has a low manufacturing process temperature and can be stacked. Therefore, the memory further obtained based on this manufacturing method can achieve three-dimensional integration, greatly improving the storage density.
[0052] refer to Figure 5 , is a schematic diagram of a process for manufacturing a thin film transistor according to an embodiment of the present application. Figure 5 As shown, the method for manufacturing the thin film transistor may specifically include the following steps:
[0053] S501, stacking a first electrode, a first dielectric layer, and a second electrode in sequence on a substrate, wherein the first electrode is made of a first metal material, and the second electrode is made of a second metal material, and the first metal material and the second metal material have different work functions;
[0054] S502, forming a columnar hole at the center of the first electrode, the first dielectric layer, and the second electrode, wherein the bottom of the columnar hole extends to the substrate;
[0055] S503, forming a semiconductor layer on the sidewall of the columnar hole, and electrically connecting the semiconductor layer to the first electrode and the second electrode;
[0056] S504, disposing a second dielectric layer along the columnar holes, the surface of the semiconductor layer and the top of the second electrode;
[0057] S505 , filling the columnar hole with a gate column, and forming a gate substrate on the top of the gate column, and determining the gate column and the gate substrate as a gate.
[0058] in addition, Figure 6 FIG. 2 shows a schematic flow chart of another method for manufacturing a thin film transistor. Figure 6 As shown, the manufacturing order of the various parts of the transistor is the first electrode 106, the first dielectric layer 105, the second electrode 103, the semiconductor layer 104, the second dielectric layer 102, and the gate 101.
[0059] Specifically, firstly, a first electrode 106, a first dielectric layer 105, and a second electrode 103 are sequentially formed on a substrate 107, and are stacked in order, wherein the first electrode 106 is made of a first metal material, and the second electrode 103 is made of a second metal material; then, a columnar hole is formed, and the columnar hole is located at the center of the first electrode 106, the first dielectric layer 105, and the second electrode 103, and the bottom of the columnar hole extends all the way to the substrate 107; a semiconductor layer 104 is formed on the sidewall of the columnar hole, and the semiconductor layer 104 is electrically connected to the first electrode 106 and the second electrode 103; the second dielectric layer 102 is arranged along the upper surface to separate the gate 101 to be formed last from the rest; finally, the gate 101 is formed, the gate column 1011 fills the columnar hole, and the gate base 1010 is formed on the uppermost layer.
[0060] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0061] Furthermore, the present application also provides a memory.
[0062] With the rise and rapid development of Internet of Things applications, artificial intelligence technology and cloud computing technology, the data that needs to be stored and processed is growing exponentially, and existing storage systems are facing new challenges.
[0063] With the rapid development of technology, the demand for embedded memory capacity, storage density, access speed, and power consumption continues to increase. The unit area of SRAM under TSMC's 3nm process is as high as 2200F. 2 , much higher than the 6F of stand-alone dynamic random access memory (DRAM) 2 Embedded DRAM (eDRAM) and embedded non-volatile memory (eNVM) are expected to achieve storage density far higher than SRAM at advanced process nodes and challenge its technological status.
[0064] As an alternative to SRAM, eDRAM has proposed a variety of different structures, which are mainly divided into two structures. One is the traditional unit structure consisting of one transistor and one capacitor (1T1C), and the other is a gain unit structure compatible with CMOS process. However, the 1T1C structure requires a complex capacitor manufacturing process and its destructive reading characteristics make the 1T1C structure less attractive. There are many different gain units, but when the gain unit based on the CMOS process is used as a memory, the leakage current is large, resulting in fast data leakage, requiring more frequent refresh operations, resulting in high power consumption, and the unit area is also larger than the 1T1C structure.
[0065] At present, with the deepening of research on vertical thin-film transistors, due to their low leakage current and stackable manufacturing characteristics, they have significant advantages when applied to the gain unit of the two-transistor-capacitor-free (2T0C) unit structure: first, the low leakage current allows the memory data retention time to reach the thousand-second level, greatly reducing the power consumption of the memory; second, stackable manufacturing allows the vertical thin-film transistor to be applied to the 2T0C unit, the unit feature size can theoretically reach 4F2, and supports three-dimensional integration, greatly improving the storage density.
[0066] refer to Fig. 10A and Fig. 10B , is a schematic diagram of a gain unit storage array structure and a read operation composed of 2T0C storage units. Fig. 10A As shown, the reading is done in rows. Since the 2T0C cell structure does not have a transistor with a switch-like function, there will be crosstalk current in the unselected rows when reading. The existing gain unit storage array composed of 2T0C storage cells cannot suppress the crosstalk current, resulting in a reduced reading margin and a limited array size. For example, when reading the first row of data, the first row read word line 2051 is pulled down from VDD to GND. At this time, if the data stored in the storage cell is "1", that is, the gate voltage of the read tube is high, the read tube is in the open state, and a current flows through the read tube. This current is hereinafter referred to as the read current (I read Due to the read current, the read bit line 206n of the column will be discharged. However, since the other non-read cells in the same column have no switch to control their on and off, if the data stored in the non-read cells in the same column is also "1", a current opposite to the read current will flow through the read tube of the non-read cells. This current is the crosstalk current (I ct ). The effective read current is the difference between the read current and all the crosstalk currents on the same column. The more "1" data stored in the same column, the greater the crosstalk current and the smaller the effective read current, resulting in a reduced read margin. In addition, not too many storage cells can be mounted in the same column, so the array size is also limited.
[0067] Therefore, the memory of the embodiment of the present application is intended to solve the problem that when the existing thin film transistor is applied to the gain unit memory composed of 2T0C memory cells, the read margin and the array size will be limited by the crosstalk current.
[0068] Specifically, the memory array of the memory of the embodiment of the present application includes a plurality of memory cells, each of which includes: a write transistor, a read transistor, a write word line, a write bit line, a read word line, and a read bit line. The write transistor is configured to write data; the read transistor is configured to read data.
[0069] It should be noted that at least one of the write transistor and the read transistor is a thin film transistor 10 as in any of the above embodiments. That is, the write transistor is a thin film transistor 10 as in any of the above embodiments, and the read transistor is a source-drain symmetric thin film transistor (a traditional thin film transistor with symmetric source-drain current); or, the read transistor is a thin film transistor 10 as in any of the above embodiments, and the write transistor is a source-drain symmetric thin film transistor; or, both the write transistor and the read transistor are thin film transistors 10 as in any of the above embodiments.
[0070] Optionally, the gate electrode of the write transistor is electrically connected to a write word line, the second electrode of the write transistor is electrically connected to a write bit line, and the first electrode of the write transistor is electrically connected to the gate electrode of the read transistor.
[0071] Optionally, the first electrode of the read transistor is electrically connected to the read word line, and the second electrode of the read transistor is electrically connected to the read bit line; or, the first electrode of the read transistor is electrically connected to the read bit line, and the second electrode of the read transistor is electrically connected to the read word line.
[0072] As an optional embodiment, the switch of the write transistor is controlled by the write word line.
[0073] As an optional embodiment, when the memory performs a read operation, the current flowing through the source and drain of the read transistor is determined according to the data written by the write transistor.
[0074] It should be noted that, for the current flowing through the source and drain of the read transistor, the corresponding reading direction is from the read bit line electrically connected to the read transistor to the read word line electrically connected to the read transistor; or, from the read word line electrically connected to the read transistor to the read bit line electrically connected to the read transistor.
[0075] It should be noted that, in one reading operation, only one of the reading transistors electrically connected to the same reading bit line is selected to perform the reading operation; or, only one of the reading transistors electrically connected to the same reading word line is selected to perform the reading operation. That is, in a column of reading transistors, only one read unit is read at a time, and during reading, the current direction of the read transistor of the read unit is opposite to the current direction of the read transistors of other non-read units.
[0076] When the memory is performing a read operation, the direction of the read transistor current of the read unit flows from the read bit line connected to the read transistor to the read word line connected to the read transistor, and the magnitude of this current is greater than 0, then this direction can be defined as a first read direction; when the memory is performing a read operation, the direction of the read transistor current of the read unit flows from the read word line connected to the read transistor to the read bit line connected to the read transistor, and the magnitude of this current is greater than 0, then this direction can be defined as a second read direction.
[0077] Optionally, electrodes of read transistors in the memory array that are electrically connected to the same read bit line or read word line are the same electrode.
[0078] Further, in some embodiments, when the read transistor is a thin film transistor 10 as in any of the above embodiments, when the memory performs a read operation: when the read direction corresponding to the current of the read unit is flowing from the read bit line electrically connected to the selected read transistor to the read word line electrically connected to the read transistor (that is, the current is along the first reading direction), the material work function corresponding to the electrode of the read transistor electrically connected to the read bit line is greater than the material work function corresponding to the electrode of the read transistor electrically connected to the read word line; when the read direction corresponding to the current of the read unit is flowing from the read word line electrically connected to the selected read transistor to the read bit line electrically connected to the read transistor (that is, the current is along the second reading direction), the material work function corresponding to the electrode of the read transistor electrically connected to the read word line is greater than the material work function corresponding to the electrode of the read transistor electrically connected to the read bit line.
[0079] As an optional embodiment, the memory array is composed of a first preset number of memory cells arranged in sequence along a first direction, a second preset number of memory cells arranged in sequence along a second direction, a first preset number of write bit lines and a first preset number of read bit lines along the first direction, and a second preset number of write word lines and a second preset number of read word lines along the second direction.
[0080] Among them, the gates of the write transistors in the memory cells of the memory array along the first direction are electrically connected to the same write word line, and the second electrodes of the write transistors in the memory cells of the memory array along the second direction are electrically connected to the same write bit line; the first electrodes of the read transistors in the memory cells of the memory array along the first direction are electrically connected to the same read word line, and the second electrodes of the read transistors in the memory cells of the memory array along the second direction are electrically connected to the same read bit line; or, the second electrodes of the read transistors in the memory cells of the memory array along the first direction are electrically connected to the same read word line, and the first electrodes of the read transistors in the memory cells of the memory array along the second direction are electrically connected to the same read bit line.
[0081] In addition, in some embodiments, with respect to the material requirements of the word bit line in the storage array, the resistivity of the material used for the metal line connected to the read circuit in the read word line and the read bit line electrically connected to the two electrodes of the read transistor is greater than the resistivity of the material used for the other metal line. That is, when the read bit line is connected to the read circuit, the resistivity of the material used for the read bit line is greater than the resistivity of the material used for the read word line; when the read word line is connected to the read circuit, the resistivity of the material used for the read word line is greater than the resistivity of the material used for the read bit line. This is because during the reading process, the parasitic resistance of the metal line connected to the read circuit has little effect on the reading performance.
[0082] The specific structure of the memory of this embodiment and the read and write operations applied to the memory are further described in detail below. Figure 7Several possible memory cells 20 based on the memory structure of the thin film transistor 10 in this embodiment are shown. Figure 7 As shown, the 2T0C memory cell 20 is composed of a write transistor 201, a read transistor 202, a write word line 203, a write bit line 204, a read word line 205, and a read bit line 206. Both the write transistor 201 and the read transistor 202 can use the thin film transistor 10 or a conventional source-drain symmetrical thin film transistor. The gate of the write transistor 201 is electrically connected to the write word line 203; the source of the write transistor 201 is electrically connected to the write bit line 204, and the drain is electrically connected to the gate of the read transistor 202, or the drain of the write transistor 201 is electrically connected to the write bit line 204, and the source is electrically connected to the gate of the read transistor 202. The source of the read transistor 202 is electrically connected to the read word line 205, and the drain is electrically connected to the read bit line 206, or the drain of the read transistor 202 is electrically connected to the read word line 205, and the source is electrically connected to the read bit line 206.
[0083] Specifically, data is written through the write transistor 201, and data is read through the read transistor 202. The switch of the write transistor 201 is controlled by the write word line 203, and the data to be written is written through the write bit line 204. Data is read by controlling the source-drain voltage of the read transistor 202. Depending on the different written data, the read transistor 202 will have different currents, which serves as the basis for reading.
[0084] It should be noted that the above-mentioned write transistor 201 and read transistor 202 can both be N-type transistors, or both can be P-type transistors, or the write transistor 201 can be an N-type transistor and the read transistor 202 can be a P-type transistor, or the write transistor 201 can be a P-type transistor and the read transistor 202 can be an N-type transistor. This embodiment does not make any specific limitations on this.
[0085] In this way, the thin film transistor 10 is applied to a storage cell 20 composed of two transistors and no capacitor (2T0C), that is, the storage cell 20 adopts a 2T0C structure composed of a read transistor composed of the thin film transistor 10 and a write transistor composed of a traditional vertical source-drain symmetrical thin film transistor, or two vertical thin film transistors 10 are stacked to form the actual structure of the storage cell 20, and the memory array structure based on this storage cell 20 can effectively suppress the crosstalk current during the read operation, improve the read margin and the number of array storage cells, and also reduce the power consumption of the read operation.
[0086] Figure 8 FIG. 1 shows a possible practical structural diagram of a memory cell 20 based on a thin film transistor 10. Figure 8As shown, the actual structure of the 2T0C memory cell 20 is composed of two vertical thin film transistors 10 and a connecting electrode 108. The read transistor 202 and the write transistor 201 are stacked, and the read transistor 202 is located at the bottom of the write transistor 201. The first dielectric layer 105 is filled between the read transistor 202 and the write transistor 201 to separate the read transistor 202 from the write transistor 201. The gate 101b of the read transistor 202 is electrically connected to the first electrode 106a of the write transistor 201 through the connecting electrode 108. The read bit line is the first electrode 106b of the read transistor 202, and the read word line is the second electrode 103b of the read transistor 202; or the read bit line is the second electrode 103b of the read transistor 202, and the read word line is the first electrode 106b of the read transistor 202. The write bit line is the second electrode 103a of the write transistor 201, and the write word line is the gate 101a of the write transistor 201.
[0087] Further, such as Fig. 10A As shown, the memory array 21 is composed of n memory cells 20 arranged in sequence along the x direction and m memory cells 20 arranged in sequence along the y direction, a total of n*m memory cells 20, as well as n write bit lines (2041-204n) and n read bit lines (2061-206n) along the x direction, and m write word lines (2031-203m) and m read word lines (2051-205m) along the y direction. The values of n and m may be the same or different, and this embodiment does not limit this.
[0088] As an optional embodiment, in the storage array 21, the gate of the write transistor of the storage unit 20 along the x direction is electrically connected to the same write word line, and the source or drain of the read transistor is electrically connected to the same read word line; along the y direction, the source or drain of the write transistor of the storage unit 20 is electrically connected to the same write bit line, and the source or drain of the read transistor is electrically connected to the same read bit line.
[0089] Specifically, the array structure of the memory is as follows: 2T0C memory cells 20 are sequentially arranged along the x direction and along the y direction, forming a memory array 21 composed of n*m 2T0C memory cells 20. At the same time, along the x direction, the gate 101 of the write transistor 201 in the same row of memory cells 20 is electrically connected to the same write word line 203, so that the writing of a row of memory cells 20 can be controlled by one operation. Along the x direction, the source or drain of the read transistor 202 in the same row of memory cells 20 is electrically connected to the same read word line 205, and the purpose of such configuration is to control the reading of a row of memory cells 20 or the reading of data of the same row of memory cells 20 through the same read bit word 205. Along the y direction, the source or drain of the write transistor 201 in the same column of memory cells 20 is electrically connected to the same write bit line 204, and the writing of the same column of memory cells 20 is controlled by the same write bit line 204. Along the y direction, the source or drain of the read transistor 202 in the same column of memory cells 20 is electrically connected to the same read bit line 206. The purpose of such a configuration is to be able to control the reading of a column of memory cells 20 at one time or to read the data of the same column of memory cells 20 through the same read bit line 206. The memory array is controlled by m write word lines 2031-203m, n write bit lines 2041-204n, m read word lines 2051-205m, and n read bit lines 2061-206n in total.
[0090] In this way, by applying the thin film transistor 10 to the gain unit memory of the 2T0C structure, that is, when the thin film transistor 10 is used as the read transistor of the gain unit, the crosstalk current during the read operation can be significantly suppressed to achieve a larger read margin. At the same time, the number of array storage units can also be increased, and the power consumption of the read operation can also be reduced.
[0091] Further, based on Fig. 10A and Fig. 10B , which explains the reading direction. Fig. 10A As shown, during the reading operation, the read word line of the read unit is first pulled down, so that the read bit line is discharged. At this time, the current direction of the read transistor of the read unit flows from the read bit line to the read word line, and the current magnitude is greater than 0, which is called the first reading direction; Fig. 10B As shown, during the read operation, the read word line of the read unit is first pulled up to charge the read bit line. At this time, the current direction of the read transistor of the read unit flows from the read word line to the read bit line, and the current magnitude is greater than 0, which is called the second read direction.
[0092] It should be understood that the reading direction determines how the different work function materials of the two electrodes of the reading transistor are configured. If the memory adopts the first reading direction, the work function of the material used for the electrode connected to the reading bit line should be greater than the work function of the material used for the electrode connected to the reading word line; if the memory adopts the second reading direction, the work function of the material used for the electrode connected to the reading bit line should be less than the work function of the material used for the electrode connected to the reading word line. Such a configuration can give full play to the suppression effect of the thin film transistor 10 proposed in this application on the crosstalk current during the reading process.
[0093] Furthermore, the present application also provides a method for reading a memory. It should be noted that the method for reading a memory can be used to read the memory of any of the above embodiments.
[0094] refer to Fig. 9 , is a flow chart of a method for reading a memory according to an embodiment of the present application. Fig. 9 As shown, the memory reading method may specifically include the following steps:
[0095] S901, configuring a read word line corresponding to a read transistor of a storage unit to be read in a memory to a first voltage, and maintaining voltages of other read word lines at a second voltage; wherein the first voltage is a ground voltage and the second voltage is a power supply voltage, or the first voltage is a power supply voltage and the second voltage is a ground voltage;
[0096] S902, after a preset time, detecting a voltage change on the read bit line, and when it is detected that the voltage change on the read bit line is greater than the first difference voltage, the read data is the first stored data; when it is detected that the voltage change on the read bit line is less than the first difference voltage, the read data is the second stored data;
[0097] S903 , after reading the data, precharge all read word lines and read bit lines to a second voltage.
[0098] It should be noted that the first stored data is data "1" and the second stored data is data "0", or the first stored data is data "0" and the second stored data is data "1"; the first differential voltage is between the first voltage and the second voltage; the preset time is set to be greater than the time required for the voltage of the read bit line of the first stored data to change to be greater than the first differential voltage, and less than the time required for the voltage of the read bit line of the second stored data to change to be greater than the first differential voltage.
[0099] Next, based on Fig. 10A and Fig. 10B , the read and write operations of the storage array 21 composed of the 2T0C storage unit 20 are described.
[0100] In some embodiments, the write operation includes: First of all, it should be noted that since the memory cells 20 in the same row of the array share the same write word line 203 and the memory cells 20 in the same column share the same write bit line 204, the data is written in units of rows; when no write operation is performed, the write word line 203 is at a voltage that turns off the write transistor, and the initial voltage of the write bit line 204 can be GND or VDD. During the write operation, firstly, according to the different data that need to be stored in different memory cells 20 in the same row, all the write bit lines 2041-204n are set to different voltages; then, the write word line 203 of the data write row is operated, and the write transistors 201 of all the memory cells 20 in the row are turned on, so that different data are written into the storage nodes of different memory cells 20 in the same row at the same time; finally, the write word line 203 of the data write row is operated, and the write transistors 201 of all the memory cells 20 in the row are turned off, and all the write bit lines 2041-204n are restored to the initial voltage, and the data is stored in the storage nodes.
[0101] In some embodiments, the read operation includes: First of all, it should be noted that since the storage cells 20 in the same row of the array share the same read word line 205, and the storage cells 20 in the same column share the same read bit line 206, the data is read in units of rows or columns; when the read operation is not performed, the read bit line 205 and the read word line 206 are at the same initial voltage, which can be GND or VDD. The following description is made based on the reading in units of rows. During the reading operation, the read word line 205 of the data reading row is first operated to change from the initial voltage to the opposite voltage (the initial voltage is VDD, then it changes to GND, and the initial voltage is GND, then it changes to VDD), and the other read word lines of the storage array 21 maintain the initial voltage unchanged, and all the read bit lines 2061-206n of the storage array 21 are disconnected from the electrical connection maintaining the initial voltage; if the data stored in the storage cell 20 being read can turn on the read transistor 202, a read current can be generated, and the current direction depends on the initial voltage; when the initial voltage is VDD, the read current flows from the read bit line 206 of the column where the storage cell is located to the read word line 205 of the data reading row, and the read bit line 206 of the column where the storage cell is located will be read. The current discharges, and the voltage of the read bit line 206 decreases; as the voltage of the read bit line 206 decreases, if the data stored in the non-read storage unit 20 on the same column can also turn on the read transistor 202, a crosstalk current will be generated, and the current direction flows from the read word line 205 of the storage unit to the read bit line 206 of the column where the storage unit is located, so that the read bit line 206 of the column where the storage unit is located is charged by the crosstalk current; when the initial voltage is GND, the read current direction is opposite, the read bit line 206 is charged by the read current, the voltage rises, and the crosstalk current direction is opposite, the read bit line 206 is discharged by the crosstalk current, and the voltage drops; the final data can be read according to the final voltage of the read bit line, or according to the effective read current obtained by subtracting the sum of the crosstalk currents of the column from the read current. It can be seen from the read operation of the storage array 21 that the direction of the crosstalk current is opposite to the direction of the read current. The influence of the crosstalk current on the read operation is as follows. If data is read by the final voltage of the read bit line 206, the crosstalk current will affect the swing of the read bit line voltage; and when current reading is adopted, the crosstalk current will reduce the effective read current, which will eventually affect the read margin. The larger the memory array 21 (i.e., the more memory cells 20 there are), the greater the crosstalk current will be, and thus the crosstalk current will affect the array size.
[0102] Since the currents in different directions at the source and drain ends of the thin film transistor 10 have different transfer characteristics and output characteristics, and the direction of the crosstalk current is opposite to the direction of the read current, in the array design, it is only necessary to ensure that the electrodes of the read transistors 202 electrically connected to the same read bit line 206 or read word line 205 in the array are the same electrodes, and the direction of the read current is in the direction where the source and drain current of the thin film transistor 10 is larger, and the crosstalk current is in the opposite direction, that is, in the direction where the source and drain current of the thin film transistor 10 is smaller. Such a design can achieve the suppression of the crosstalk current.
[0103] Fig.11 FIG. 1 is a schematic diagram showing the effect of suppressing crosstalk current in a memory array based on thin film transistors. Fig.11 As shown in FIG. 1 , different current directions at the source and drain terminals have different transfer characteristics, which can be regarded as different equivalent thresholds at different current directions at the source and drain terminals. Fig.11 It can be seen that the equivalent threshold difference ΔV of different current directions at the source and drain ends th The larger it is, the smaller the crosstalk current on the array is, and the crosstalk current is suppressed.
[0104] During the read operation, if the data is read based on the voltage of the read bit line 206, different stored data will cause the read bit line 206 to have different voltage swings, resulting in different final voltages of the read bit line 206. The difference between the maximum final voltage and the minimum final voltage of the read bit line 206 is the read margin. The suppression of the crosstalk current can make the voltage swing of the read bit line 206 larger, thereby widening the difference between the maximum final voltage and the minimum final voltage, so that the read margin is improved. If the data is read based on the effective read current, different stored data will have different read currents. The effective read current is the difference between the read current and the total crosstalk current caused by the remaining non-read cells in the same row or column. The difference between the maximum effective read current and the minimum effective read current caused by different stored data is the read margin. The suppression of the crosstalk current can also widen the difference between the maximum effective read current and the minimum effective read current, thereby improving the read margin. In addition, the suppression of the crosstalk current enables the VDD of the storage array to be further reduced, so the use of the thin film transistor proposed in the present application in the read transistor of the storage array can also directly reduce the power consumption of the read operation.
[0105] Fig.12 A schematic diagram showing the effect of a thin film transistor based memory array on the number of memory cells in the array. The array size is defined as the number of memory cells contained in the array. In order to ensure that data can be read correctly, a certain read margin is necessary. The larger the array, the greater the crosstalk current, the smaller the read margin, and it is difficult to ensure that data can be read correctly. Therefore, if Fig.12 As shown, the suppression of crosstalk current enables the array size to be further increased.
[0106] It should be noted that the reference to "embodiment" in this application means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments.
[0107] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", and "attached" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0108] In the embodiments of the present application, the same reference numerals represent the same components, and for the sake of brevity, detailed descriptions of the same components are omitted in different embodiments. It should be understood that the thickness, length, width and other dimensions of various components in the embodiments of the present application shown in the drawings, as well as the overall thickness, length, width and other dimensions of the integrated device are only exemplary descriptions and should not constitute any limitation to the present application.
[0109] The term "plurality" used in the present application refers to two or more (including two).
[0110] Although the present application has been described with reference to preferred embodiments, various modifications may be made thereto and parts thereof may be replaced with equivalents without departing from the scope of the present application. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there is no structural conflict. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.
[0111] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.
[0112] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.
Claims
1. A thin film transistor, characterized in that: include: A first electrode, a first dielectric layer, and a second electrode are stacked in sequence, wherein the first electrode, the first dielectric layer, and the second electrode are all arranged outside the thin film transistor; The first electrode is made of a first metal material, and the second electrode is made of a second metal material. The first metal material and the second metal material have different work functions.
2. The thin film transistor according to claim 1, characterized in that: The thin film transistor further comprises: a gate, a semiconductor layer and a second dielectric layer; The gate includes a gate substrate and a gate column, wherein the gate substrate is disposed on the top of the thin film transistor, and the gate column is a column extending from the center of the gate substrate to the bottom of the thin film transistor; The semiconductor layer surrounds the sidewall of the gate column and is electrically connected to the first electrode and the second electrode respectively; The second dielectric layer is arranged along the inner wall and the bottom of the gate column and the top of the second electrode.
3. A method for manufacturing a thin film transistor, characterized in that: The manufacturing method is used to manufacture a thin film transistor according to any one of claims 1 to 2, and the manufacturing method comprises: A first electrode, a first dielectric layer, and a second electrode are stacked in sequence on a substrate, wherein the first electrode is made of a first metal material, and the second electrode is made of a second metal material, and the first metal material and the second metal material have different work functions; A columnar hole is formed at the center of the first electrode, the first dielectric layer and the second electrode, wherein the bottom of the columnar hole extends to the substrate; forming a semiconductor layer on the sidewall of the columnar hole, and electrically connecting the semiconductor layer to the first electrode and the second electrode; A second dielectric layer is disposed along the columnar hole, the surface of the semiconductor layer and the top of the second electrode; The columnar hole is filled with a gate column, and a gate substrate is formed on the top of the gate column, and the gate column and the gate substrate are defined as a gate.
4. A memory, characterized in that: The memory array of the memory includes a plurality of memory cells, each of which includes: a write transistor, a read transistor, a write word line, a write bit line, a read word line and a read bit line; At least one of the write transistor and the read transistor is a thin film transistor as claimed in any one of claims 1 to 2; The write transistor is configured to write data; The read transistor is configured to read data.
5. The memory according to claim 4, characterized in that: The gate electrode of the write transistor is electrically connected to a write word line, the second electrode of the write transistor is electrically connected to a write bit line, and the first electrode of the write transistor is electrically connected to the gate electrode of the read transistor; The switch of the write transistor is controlled by the write word line.
6. The memory according to claim 5, characterized in that: The first electrode of the read transistor is electrically connected to the read word line, and the second electrode of the read transistor is electrically connected to the read bit line; or the first electrode of the read transistor is electrically connected to the read bit line, and the second electrode of the read transistor is electrically connected to the read word line; When the memory performs a read operation, the current flowing through the source and drain of the read transistor is determined according to the data written by the write transistor; the reading direction corresponding to the current is from the read bit line electrically connected to the read transistor to the read word line electrically connected to the read transistor; or, from the read word line electrically connected to the read transistor to the read bit line electrically connected to the read transistor.
7. The memory according to claim 6, characterized in that: In one read operation, only one of the read transistors electrically connected to the same read bit line is selected to perform the read operation; or only one of the read transistors electrically connected to the same read word line is selected to perform the read operation.
8. The memory according to claim 7, characterized in that: The electrodes of the read transistors in the memory array electrically connected to the same read bit line or read word line are the same electrode.
9. The memory according to claim 7, characterized in that: In the case where the read transistor is a thin film transistor as claimed in any one of claims 1 to 2, when the memory performs a read operation, In a case where the reading direction corresponding to the current is from the read bit line electrically connected to the selected read transistor to the read word line electrically connected to the read transistor, the material work function corresponding to the electrode of the read transistor electrically connected to the read bit line is greater than the material work function corresponding to the electrode of the read transistor electrically connected to the read word line; When the reading direction corresponding to the current is from the read word line electrically connected to the selected read transistor to the read bit line electrically connected to the read transistor, the material work function corresponding to the electrode of the read transistor electrically connected to the read word line is greater than the material work function corresponding to the electrode of the read transistor electrically connected to the read bit line.
10. The memory according to claim 7, characterized in that: The memory array is composed of a first preset number of memory cells arranged in sequence along a first direction, a second preset number of memory cells arranged in sequence along a second direction, a first preset number of write bit lines and a first preset number of read bit lines along the first direction, and a second preset number of write word lines and a second preset number of read word lines along the second direction.
11. The memory according to claim 10, characterized in that: The gates of the write transistors in the memory cells of the memory array along the first direction are electrically connected to the same write word line, and the second electrodes of the write transistors in the memory cells of the memory array along the second direction are electrically connected to the same write bit line.
12. The memory according to claim 10, characterized in that: The first electrodes of the read transistors in the memory cells of the memory array along the first direction are electrically connected to the same read word line, and the second electrodes of the read transistors in the memory cells of the memory array along the second direction are electrically connected to the same read bit line; Alternatively, the second electrodes of the read transistors in the memory cells of the memory array along the first direction are electrically connected to the same read word line, and the first electrodes of the read transistors in the memory cells of the memory array along the second direction are electrically connected to the same read bit line.
13. The memory according to any one of claims 4 to 12, characterized in that: In a read word line and a read bit line electrically connecting two electrodes of a read transistor, a metal line electrically connected to a read circuit has a resistivity of a material greater than a resistivity of a material used for another metal line.
14. A method for reading a memory, characterized in that: The reading method is used to read the memory according to any one of claims 4 to 13, and the reading method comprises: The read word line corresponding to the read transistor of the storage unit to be read in the memory is configured to be a first voltage, and the voltages of the other read word lines are maintained at a second voltage; wherein the first voltage is a ground voltage and the second voltage is a power supply voltage, or the first voltage is a power supply voltage and the second voltage is a ground voltage; After a preset time, the voltage change on the read bit line is detected. When the voltage change on the read bit line is detected to be greater than the first difference voltage, the read data is the first stored data; when the voltage change on the read bit line is detected to be less than the first difference voltage, the read data is the second stored data; the first difference voltage is between the first voltage and the second voltage; the preset time is set to be greater than the time required for the voltage on the read bit line to read the first stored data to change to be greater than the first difference voltage, and less than the time required for the voltage on the read bit line to read the second stored data to change to be greater than the first difference voltage; After the data is read, all read word lines and read bit lines are precharged to a second voltage.