Preparation method of on-chip waveguide integrated magnesium silicide polarization beam splitting type photoelectric detector
By integrating the silicon waveguide directional coupler and the magnesium silicide photoelectric conversion layer on a double-layer SOI substrate, the existing infrared detector material pollution and compatibility problems are solved, and the on-chip integrated detection function and efficient polarized light detection are realized, which is suitable for large-scale photonic integrated device manufacturing.
Patent Information
- Application Number
- CN202510278148.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-10
- Publication Date
- 2025-06-06
AI Technical Summary
Existing infrared detector materials have the risk of heavy metal contamination and are incompatible with silicon-based CMOS processes, which limits the integration and large-scale production of detectors. At the same time, the lack of on-chip photoelectric detection capabilities hinders the expansion and deployment of photonic integrated circuits.
A double-layer SOI substrate is used to form a directional coupler by etching, deposit silicon dioxide and magnesium films, conduct thermal reaction to generate a magnesium silicide film, and prepare a top electrode to achieve the integration of the silicon waveguide directional coupler and the magnesium silicide photoelectric conversion layer.
It realizes the integrated detection function on chip, reduces signal transmission loss, is compatible with CMOS processes, is suitable for large-scale photonic integrated device manufacturing, and improves the detection ability of light of different polarization modes.
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Figure CN120111990A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of infrared detection technology, and in particular to an on-chip waveguide integrated magnesium silicide polarization beam splitting type photoelectric detector. Background Art
[0002] As an important category of optoelectronic devices, the core function of infrared detectors is to accurately convert the incident infrared light signal into an electrical signal output for subsequent processing. In many key areas of today's society, such as security monitoring, environmental monitoring, disaster warning, power system status monitoring, and artificial intelligence perception, infrared detectors play an indispensable role. In the preparation of short-wave infrared detectors, materials such as InGaAs, InSb, and HgCdTe have long dominated. However, these material systems have obvious drawbacks. First, most of these materials contain heavy metal elements, which pose a serious pollution risk to the ecological environment throughout the entire life cycle from raw material mining, device preparation, use to waste disposal. Second, in terms of material process compatibility, these materials are incompatible with the widely used silicon-based complementary metal oxide semiconductor (CMOS) process, which greatly limits the development of detectors towards high integration and miniaturization, and is not conducive to achieving the goal of high-performance, low-cost large-scale production.
[0003] With the booming development of photonics technology and the increasingly prominent trend of integration of various components, the demand for photonic material platforms that can provide wider transparency windows, lower losses and diversified optical nonlinear properties is increasing day by day, and a large number of such platforms have emerged. These platforms are widely used in many fields such as mid-infrared circuits, nonlinear optics and ultra-high-speed data coding. Integrated photodetectors play a vital role in these technical systems. As the main readout device of many systems, their important position is irreplaceable. However, in most new photonic material platforms, the lack of on-chip photodetection capabilities has become a prominent problem that needs to be solved urgently. Due to the lack of easily integrated photodetectors, these platforms have to rely on external detection methods. This situation seriously restricts the expansion of photonic integrated circuits and large-scale deployment and application.
[0004] Currently, on-chip photodetection methods have significant limitations. On the one hand, there are detection methods that rely on specific platforms. For example, traditional photodiode materials such as germanium and III-V can only operate on silicon-on-insulator (SOI) or III-V platforms due to their stringent material synthesis process requirements, including high synthesis temperatures and lattice conditions that match the host material. On the other hand, there are methods that are universal but challenging to scale, such as depositing these materials in an amorphous state. However, the low carrier mobility of amorphous materials requires the use of nanoscale manufacturing process features, which greatly increases the difficulty of process implementation. Although two-dimensional (2D) materials do not have lattice matching requirements due to their surface properties and can theoretically be transferred to almost any substrate, they still face major obstacles in terms of manufacturing process, stability and scalability. At present, the mechanical exfoliation process relied on by the manufacture of 2D photodetectors is not only random, but also a labor-intensive manual operation process. Although the large-area synthesis technology of 2D materials has made continuous progress, problems such as small grain size, strain and reliable material transfer are still very prominent.
[0005] In view of this, the development of a semiconductor material that can work efficiently at room temperature, is compatible with silicon-based CMOS processes and is environmentally friendly has become a key problem that needs to be overcome in the field of short-wave infrared detectors. Magnesium silicide (Mg2Si) is an indirect bandgap semiconductor material with unique physical properties, and its bandgap range is between 0.6 and 0.8 eV. Theoretical calculations show that the cutoff response wavelength of magnesium silicide detectors can reach about 1800nm, which means that it has good detection capabilities for near-infrared light. At the same time, the preparation process of magnesium silicide is highly compatible with silicon-based CMOS processes, which lays a solid technical foundation for large-scale integrated manufacturing. In addition, magnesium silicide detectors have excellent performance, high sensitivity, can accurately capture extremely weak infrared light signals, and have a fast response speed, which can respond to rapidly changing infrared scenes in a timely manner. In summary, magnesium silicide detectors show broad application prospects in the field of near-infrared detection and imaging technology, and are expected to become an important force in promoting technological innovation and industrial development in this field.
[0006] The most common Mg silicide photodiode device structure is the PN structure. In the 1960s, Stella A et al. discovered that Mg silicide materials are compatible with silicon processes and have the potential to be used to prepare silicon-based photodetection devices, which has attracted widespread attention from researchers. In 2010, Xiao Qingquan, Xie Quan et al. deposited a layer of Mg film on a flat Si substrate using magnetron sputtering and prepared a single-phase semiconductor Mg by diffusion reaction. 2Si thin film, and explored the device that forms heterojunction with silicon. In 2019, Japanese scholars EI-AmirA et al. prepared n-Mg by magnetron sputtering. 2 Si / p-Si photodiode, the prepared photodiode exhibits obvious rectification behavior, has obvious spectral response at 800-1350nm, and the spectral response reaches a maximum value of 0.47A / W at 1000nm.
[0007] The above-mentioned traditional magnesium silicide PN junction detector has a high response rate, but it has not been integrated with the photonic material platform, and cannot fully take advantage of the diverse advantages provided by the photonic material platform, which limits its application expansion in complex photonic systems and makes it difficult to meet the requirements of advanced application scenarios such as highly integrated optical communication modules and multifunctional photon sensor arrays for device collaboration and system compactness. In addition, the utilization efficiency of incident light energy through free-space optical coupling is not high, and it is easy to cause thermal effects to generate hot carriers that affect the response speed.
[0008] The present invention selects a double-layer SOI substrate including a silicon base, a lower silicon dioxide buried oxide layer, a silicon layer, an upper silicon dioxide buried oxide layer and a top silicon layer; etches the double-layer SOI substrate to form a directional coupler shape, etches through the top silicon layer, the upper silicon dioxide buried oxide layer and the silicon layer, and exposes the lower silicon dioxide buried oxide layer; deposits silicon dioxide until it is flush with the top silicon layer; partially etches silicon dioxide to the top of the upper silicon dioxide buried oxide layer, exposing the branch arm at the port on one side of the top silicon layer; deposits a magnesium film at the etched notch; generates a magnesium silicide film through a thermal reaction; and prepares a top electrode. In the preparation method, the magnesium film and the top silicon structure diffuse and react with each other to generate a magnesium silicide film, and the silicon waveguide directional coupler below the film transmits and separates light of different polarization modes, which is coupled to the magnesium silicide layer through the evanescent field, resulting in light absorption and the generation of photocarriers, and the photoelectric response signal can be collected through the metal top electrode. Compared with other discrete photodetectors, on the one hand, the integration of silicon waveguide directional couplers with magnesium silicide photoelectric conversion layers realizes on-chip integrated detection functions and reduces signal transmission losses. It is compatible with CMOS processes and highly integrated, suitable for large-scale photonic integrated device manufacturing. On the other hand, the silicon waveguide directional coupler couples light to the magnesium silicide layer through the evanescent field, enhancing light absorption and photogenerated carrier generation. In addition, the directional coupler can accurately transmit and separate light of different polarization modes, achieving efficient use of light polarization characteristics, and can accurately detect specific polarized light. It has obvious advantages in scenarios with high requirements for polarized light processing, such as optical communications. Summary of the invention
[0009] In view of the above problems, the purpose of the present invention is to provide a method for preparing an on-chip waveguide integrated magnesium silicide polarization beam splitting photodetector, which integrates the magnesium silicide film with the silicon waveguide directional coupler, can not only greatly enhance light absorption through evanescent field coupling, but also realize the detection of different polarization modes, demonstrating the potential of integrating the functions of multiple optoelectronic devices into one device.
[0010] In order to achieve the above object, the present invention provides a method for preparing an on-chip waveguide integrated magnesium silicide polarization beam splitting photodetector, the method comprising the following steps:
[0011] Step 1: Select a double-layer SOI substrate, which includes a silicon base (10), a lower silicon dioxide buried oxide layer (20), a silicon layer (30), an upper silicon dioxide buried oxide layer (40), and a top silicon layer (50), such as Figure 1 -a and Figure 2 -a as shown;
[0012] Step 2: Etching the double-layer SOI substrate to form a directional coupler shape, etching through the top silicon layer (50), the upper silicon dioxide buried oxide layer (40), and the silicon layer (30), exposing the lower silicon dioxide buried oxide layer (20), such as Figure 1 -b and Figure 2 -b as shown;
[0013] Step 3: Deposit a silicon dioxide film (31) until it is flush with the top silicon layer (50), such as Figure 1 -c and Figure 2 -c as shown;
[0014] Step 4: Partially etch the silicon dioxide (31) to the top of the upper silicon dioxide buried oxide layer (40), exposing the branch arm at the port on one side of the top silicon layer (50), such as Figure 1 -d and Figure 2 -d as shown;
[0015] Step 5: Deposit a magnesium film (32) at the notch etched in step 4, such as Figure 1 -e and Figure 2 -e as shown;
[0016] Step 6: Thermal reaction to generate magnesium silicide film (33), such as Figure 1 -f and Figure 2 -f as shown;
[0017] Step 7: Prepare the top electrode (60), such as Figure 1 -g and Figure 2 -g as shown.
[0018] Furthermore, the double-layer SOI substrate in step 1 has a silicon base thickness of 100μm to 500μm, a lower silicon dioxide buried oxide layer thickness of 1μm to 10μm, a silicon layer thickness of 100nm to 2μm, an upper silicon dioxide buried oxide layer thickness of 10nm to 50nm, and a top silicon layer thickness of 100nm to 1μm.
[0019] Furthermore, the directional coupler in step 2 has a coupling region length of 10 μm to 30 μm, a coupling region spacing of 80 nm to 200 nm, a waveguide width of 400 nm to 500 nm, and is prepared by photolithography combined with ion etching process.
[0020] Furthermore, the silicon dioxide film in step 3 is prepared by magnetron sputtering, and the film thickness is 200 nm to 4 μm.
[0021] Furthermore, the magnesium film in step 5 is prepared by magnetron sputtering, electron beam evaporation or thermal evaporation, and the film thickness is 50nm to 300nm.
[0022] Furthermore, the temperature of the thermal reaction in step 6 is 300 to 600° C., and the time is 10 to 600 minutes.
[0023] Furthermore, the metal electrode in step 7 is prepared by magnetron sputtering, electron beam evaporation or thermal evaporation combined with photolithography, and the electrode material is made of any one of gold, silver, titanium, aluminum, nickel, and chromium or an alloy of at least two of them, with a thickness of 20 to 200 nm.
[0024] The beneficial effects of the present invention compared with the prior art are:
[0025] The present invention selects a double-layer SOI substrate; etches the double-layer SOI substrate to form a directional coupler shape; deposits silicon dioxide until it is flush with the top silicon layer; partially etches silicon dioxide to the top of the upper silicon dioxide buried oxide layer to expose the branch arm at the port on one side of the top silicon layer; deposits a magnesium film at the etched notch; generates a magnesium silicide film through thermal reaction; and prepares a top electrode. In the preparation method, the magnesium film and the top silicon structure diffuse and react with each other to generate a magnesium silicide film, and the silicon waveguide directional coupler under the film transmits and separates light of different polarization modes, which is coupled to the magnesium silicide layer through the evanescent field, resulting in light absorption and the generation of photocarriers, and the photoelectric response signal can be collected through the metal top electrode. Compared with other discrete photodetectors, on the one hand, the silicon waveguide directional coupler is integrated with the magnesium silicide photoelectric conversion layer to realize the on-chip integrated detection function and reduce the signal transmission loss. It is compatible with CMOS technology and highly integrated, and is suitable for large-scale photonic integrated device manufacturing. On the other hand, the silicon waveguide directional coupler couples light to the magnesium silicide layer through the evanescent field, which enhances light absorption and photogenerated carrier generation. In addition, the directional coupler can accurately transmit and separate light of different polarization modes, realize efficient utilization of the polarization characteristics of light, and accurately detect light of specific polarization. It has obvious advantages in scenarios with high requirements for polarization light processing, such as optical communications. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 It is a cross-sectional schematic diagram of the preparation process of the present invention
[0027] Figure 2 It is a three-dimensional schematic diagram of the preparation process of the present invention
[0028] Figure 3 This is a functional demonstration diagram of the present invention
[0029] In the figure: 10-silicon substrate; 20-lower silicon dioxide buried oxygen layer; 30-silicon layer; 31a-silicon dioxide film; 31b-silicon dioxide film; 32-magnesium film; 33-magnesium silicide film; 40-upper silicon dioxide buried oxygen layer; 50-top silicon layer; 60-metal top electrode. DETAILED DESCRIPTION
[0030] The present invention is further described below in conjunction with embodiments. The description of the following embodiments is only used to help understand the present invention. It should be noted that for ordinary persons in the art, without departing from the principle of the present invention, the present invention can also be modified in some ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.
[0031] Although current photodetectors have demonstrated relatively excellent detection performance, their integration with other photonic platforms has always faced many bottlenecks. In the vast majority of new photonic material platforms, the lack of on-chip photodetection devices is extremely prominent, and they often have to rely on external detection mechanisms. This serious lack of on-chip photodetection capabilities not only limits the functional expansion of photonic integrated circuits, but also significantly hinders their large-scale deployment and practical applications. Therefore, the present invention is based on device structure and process design to solve the key problem of integrating silicon-based photonic platforms with magnesium silicide photodetectors.
[0032] Specifically, an embodiment of the present invention provides a method for preparing an on-chip waveguide integrated magnesium silicide polarization beam splitting photodetector, comprising:
[0033] Step 1: Select a double-layer SOI substrate, which includes a silicon base (10), a lower silicon dioxide buried oxide layer (20), a silicon layer (30), an upper silicon dioxide buried oxide layer (40), and a top silicon layer (50), such as Figure 1 -a and Figure 2 -a as shown;
[0034] Step 2: Etching the double-layer SOI substrate to form a directional coupler shape, etching through the top silicon layer (50), the upper silicon dioxide buried oxide layer (40), and the silicon layer (30), exposing the lower silicon dioxide buried oxide layer (20), such as Figure 1 -b and Figure 2 -b as shown;
[0035] Step 3: Deposit a silicon dioxide film (31) until it is flush with the top silicon layer (50), such as Figure 1 -c and Figure 2 -c as shown;
[0036] Step 4: Partially etch the silicon dioxide (31) to the top of the upper silicon dioxide buried oxide layer (40), exposing the branch arm at the port on one side of the top silicon layer (50), such as Figure 1 -d and Figure 2 -d as shown;
[0037] Step 5: Deposit a magnesium film (32) at the notch etched in step 4, such as Figure 1 -e and Figure 2 -e as shown;
[0038] Step 6: Thermal reaction to generate magnesium silicide film (33), such as Figure 1 -f and Figure 2 -f as shown;
[0039] Step 7: Prepare the top electrode (60), such as Figure 1 -g and Figure 2 -g as shown.
[0040] The double-layer SOI substrate in step 1 has a silicon base thickness of 100μm to 500μm, a lower silicon dioxide buried oxide layer thickness of 1μm to 10μm, a silicon layer thickness of 100nm to 2μm, an upper silicon dioxide buried oxide layer thickness of 10nm to 50nm, and a top silicon layer thickness of 100nm to 1μm.
[0041] The directional coupler in step 2 has a coupling region length of 10 μm to 30 μm, a coupling region spacing of 80 nm to 200 nm, a waveguide width of 400 nm to 500 nm, and is prepared using photolithography technology combined with ion etching technology.
[0042] The silicon dioxide film in step 3 is prepared by magnetron sputtering, and the film thickness is 200nm to 4μm.
[0043] The magnesium film in step 5 is prepared by magnetron sputtering, electron beam evaporation or thermal evaporation, and the film thickness is 50nm to 300nm.
[0044] The temperature of the thermal reaction in step 6 is 300 to 600° C., and the time is 10 to 600 minutes.
[0045] The metal electrode in step 7 is prepared by magnetron sputtering, electron beam evaporation or thermal evaporation combined with photolithography. The electrode material is made of any one of gold, silver, titanium, aluminum, nickel, and chromium or an alloy of at least two of them, and has a thickness of 20 to 200 nm.
[0046] Example 1 and Function Demonstration
[0047] like Figure 1 , Figure 2 As shown, a method for preparing an on-chip waveguide integrated magnesium silicide polarization beam splitting photodetector comprises the following steps:
[0048] (1) Select a double-layer SOI substrate, the thickness of the silicon base is controlled at 100 μm, the thickness of the lower silicon dioxide buried oxide layer is 3 μm, the thickness of the silicon layer is 220 nm, the thickness of the upper silicon dioxide buried oxide layer is 10 nm, and the thickness of the top silicon layer is 200 nm. Figure 1 -a and Figure 2 -a as shown;
[0049] (2) Using photolithography technology, a mask was used to expose and develop the double-layer SOI substrate, pattern the directional coupler, and ion etching was combined to etch a directional coupler with an arm length of 15 μm, an arm spacing of 8 μm, a waveguide width of 420 nm, a coupling region length of 17 μm, and a coupling region spacing of 115 nm on the substrate. The etching power was 180 W, and SF 6 Gas and Ar gas as reaction gas, such as Figure 1 -b and Figure 2 -b as shown;
[0050] (3) Silicon dioxide thin film was prepared by radio frequency magnetron sputtering process, the silicon target was sputtered with power of 30 W, the sputtering time was 20 min, and the sputtering atmosphere was 0.5 Pa argon mixed with 25% oxygen atmosphere. The prepared silicon dioxide thin film was as follows Figure 1 -c and Figure 2 -c as shown;
[0051] (4) Using photolithography technology, a mask is used to expose and develop the double-layer SOI substrate, and ion etching is used to etch the silicon dioxide film, such as Figure 1 -d and Figure 2 -d as shown;
[0052] (5) A magnesium film was prepared on the surface of a silicon substrate by a DC magnetron sputtering process, with a sputtering power of 50 W, a sputtering time of 15 min, and a sputtering atmosphere of 0.5 Pa argon gas. Figure 1 -e and Figure 2 -e as shown;
[0053] (6) In-situ annealing is performed in the chamber of the magnetron device to form a magnesium silicide film through diffusion reaction. The annealing temperature is 390°C, the holding time is 2 hours, and the pure argon pressure in the chamber is 1000 Pa. After the holding time is completed, the chamber is opened and the sample is taken out. Figure 1 -f and Figure 2 -f as shown.
[0054] (7) Ag electrode with a thickness of 200 nm was prepared on the surface of magnesium silicide by thermal evaporation. Figure 1 -g and Figure 2 -g as shown.
[0055] like Figure 3 As shown, the prepared directional coupler is composed of two or more optical waveguides close to each other. When light of different polarization modes is input into the directional coupler, due to the coupling effect between the optical waveguides and the difference in propagation constants of light of different polarization modes in the waveguides, the light of different polarization modes undergoes different coupling processes and transmission paths in the directional coupler. This characteristic enables the directional coupler to separate the input mixed polarization light according to the polarization mode and guide the light of different polarization modes to different output ports or waveguide arms, thereby realizing the effective distinction and independent transmission of light of different polarization modes.
[0056] Through precise preparation technology, magnesium silicide film is prepared on one arm of the directional coupler. When the separated specific polarized light is transmitted to the arm, the magnesium silicide film can absorb the energy of the specific polarized light, triggering the internal photoelectric effect. The energy of the photon is converted into electron-hole pairs. These photogenerated carriers form current or voltage signals under the action of the electric field. By detecting and analyzing these electrical signals, the detection of specific polarized light can be achieved. This method based on directional coupler separation and magnesium silicide film detection can not only improve the sensitivity and selectivity of specific polarized light detection, but also can be integrated with other photonics and optoelectronic devices, providing an effective way to build high-performance, multifunctional optical systems and optoelectronic devices, and has broad application prospects in many fields such as optical communications, optical sensing, and optical imaging.
Claims
1. A method for preparing an on-chip waveguide integrated magnesium silicide polarization beam splitting photodetector, the method comprising the following steps: Step 1: A double-layer SOI substrate is selected, which comprises a silicon base (10), a lower silicon dioxide buried oxide layer (20), a silicon layer (30), an upper silicon dioxide buried oxide layer (40), and a top silicon layer (50), as shown in FIG. 1-a and FIG. 2-a; Step 2: Etching a double-layer SOI substrate to form a directional coupler shape, etching through the top silicon layer (50), the upper silicon dioxide buried oxide layer (40), and the silicon layer (30), exposing the lower silicon dioxide buried oxide layer (20), as shown in FIG. 1-b and FIG. 2-b; Step 3: depositing a silicon dioxide film (31) until it is flush with the top silicon layer (50), as shown in FIG. 1-c and FIG. 2-c; Step 4: Partially etching the silicon dioxide (31) to the top of the upper silicon dioxide buried oxide layer (40) to expose the branch arm at the port on one side of the top silicon layer (50), as shown in FIG. 1-d and FIG. 2-d; Step 5: depositing a magnesium film (32) at the notch etched in step 4, as shown in FIG. 1-e and FIG. 2-e; Step 6: thermal reaction to generate a magnesium silicide film (33), as shown in FIG1-f and FIG2-f; Step 7: Prepare the top electrode (60), as shown in FIG. 1-g and FIG. 2-g.
2. The method for preparing an on-chip waveguide integrated magnesium silicide polarization beam splitting photodetector according to claim 1, characterized in that: The double-layer SOI substrate in step 1 has a silicon base thickness of 100μm to 500μm, a lower silicon dioxide buried oxide layer thickness of 1μm to 10μm, a silicon layer thickness of 100nm to 2μm, an upper silicon dioxide buried oxide layer thickness of 10nm to 50nm, and a top silicon layer thickness of 100nm to 1μm.
3. The method for preparing an on-chip waveguide integrated magnesium silicide polarization beam splitting photodetector according to claim 1, characterized in that: The directional coupler in step 2 has a coupling region length of 10 μm to 30 μm, a coupling region spacing of 80 nm to 200 nm, a waveguide width of 400 nm to 500 nm, and is prepared using photolithography technology combined with ion etching technology.
4. The method for preparing an on-chip waveguide integrated magnesium silicide polarization beam splitting photodetector according to claim 1, characterized in that: The silicon dioxide film in step 3 is prepared by magnetron sputtering, and the film thickness is 200nm to 4μm.
5. The method for preparing an on-chip waveguide integrated magnesium silicide polarization beam splitting photodetector according to claim 1, characterized in that: The magnesium film in step 5 is prepared by magnetron sputtering, electron beam evaporation or thermal evaporation, and the film thickness is 50nm to 300nm.
6. The method for preparing an on-chip waveguide integrated magnesium silicide polarization beam splitting photodetector according to claim 1, characterized in that: The temperature of the thermal reaction in step 6 is 300 to 600° C., and the time is 10 to 600 minutes.
7. The method for preparing an on-chip waveguide integrated magnesium silicide polarization beam splitting photodetector according to claim 1, characterized in that: The metal electrode in step 7 is prepared by magnetron sputtering, electron beam evaporation or thermal evaporation combined with photolithography. The electrode material is made of any one of gold, silver, titanium, aluminum, nickel, and chromium or an alloy of at least two of them, and has a thickness of 20 to 200 nm.