High-order compensation low-temperature coefficient band-gap reference circuit based on substrate bias technology

Abstract

The invention belongs to the technical field of analog circuits, and particularly relates to a high-order compensation low-temperature-coefficient band-gap reference circuit based on a substrate bias technology. The high-order compensation band-gap reference circuit is characterized in that a substrate bias technology is used in the high-order compensation band-gap reference circuit, a temperature term highly fitted with a high-order nonlinear temperature term of base-emitter voltage VBE of a bipolar transistor is generated through substrate bias of an MOS tube in a sub-threshold region for temperature compensation, and the temperature coefficient of output voltage is greatly reduced; the circuit introduces trimming current to be injected into the resistor (R3), error trimming is achieved, trimming is easy, and the problem of temperature coefficient change caused by various non-ideal factors can be solved conveniently.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog circuits, and in particular, relates to a high-order compensated low temperature coefficient bandgap reference circuit based on substrate biasing technology. Background Art

[0002] The bandgap reference (BGR) reference voltage plays an important role in most digital-analog and mixed-signal systems, whether as part of the internal bias or as the output of the circuit. Since electronic systems may operate under various physical conditions, the stability of its reference voltage is crucial, which usually limits the maximum absolute accuracy achievable by the system. Currently, the increasing demand for high-performance circuits (such as voltage regulators and high-resolution data converters) has driven the demand for high-precision reference voltages with low temperature coefficients.

[0003] In high-precision analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), the accuracy and stability of the reference voltage directly affect the performance of the converter. A low-temperature-drift bandgap reference circuit can provide a high-precision, low-temperature-drift reference voltage, thereby improving the conversion accuracy of ADCs and DACs. In sensor chips, the bandgap reference circuit, as a key voltage reference source, its performance such as temperature stability and power supply rejection ratio has an important impact on the accuracy and reliability of the sensor. The low-temperature-drift bandgap reference circuit can effectively reduce the influence of temperature and power supply fluctuations on the sensor performance and improve the measurement accuracy of the sensor.

[0004] Traditional bandgap reference circuits utilize the negative temperature coefficient of the base-emitter voltage V BE of bipolar transistors that varies with temperature, and the positive temperature coefficient of the thermal voltage V T that varies with temperature. By weighted addition, a reference voltage with a temperature coefficient close to zero can be obtained, namely the bandgap reference voltage V REF . Its basic formula is

[0005] V REF = V BE + nV T ln(N)

[0006] where n is the proportionality coefficient and N is the current ratio of the current mirror.

[0007] The relationship between the base-emitter voltage V BE of bipolar transistors and temperature is:

[0008]

[0009] where, V GO (T r) is the bandgap voltage at the reference temperature Tr, ξ is the order of the collector current temperature dependence, η is a constant independent of temperature but process-related, and its typical value is 3 to 4. V T = kT / q is the thermal voltage, k is the Boltzmann constant, and q is the charge of an electron.

[0010] It can be seen that the traditional bandgap reference circuit only compensates for the first-order component of the base-emitter voltage of the bipolar transistor while ignoring the higher-order non-linear components. Therefore, the traditional bandgap reference has a poor temperature coefficient and cannot be applied to high-precision circuits. Thus, a low-temperature coefficient bandgap reference circuit with higher-order compensation has practical significance. Summary of the Invention

[0011] The object of the present invention is to solve the problem of poor temperature coefficient caused by the uncompensated higher-order non-linear components of the traditional bandgap reference circuit. By using the substrate bias technology, a temperature term with a very high fitting degree to the higher-order non-linear components of the base-emitter voltage of the bipolar transistor is obtained for higher-order compensation, and it has the advantages of high precision and easy trimming.

[0012] The technical solution of the present invention is as follows:

[0013] A higher-order compensation low-temperature coefficient bandgap reference circuit based on substrate bias technology, including a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first triode, a second triode, a third triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, a third capacitor, a first operational amplifier, and a second operational amplifier;

[0014] The first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the first capacitor, and the second capacitor form a start-up circuit; wherein, the source of the first PMOS transistor is connected to the power supply V DDL , its gate is connected to the source of the third PMOS transistor and the output terminal of the first operational amplifier; the gate of the third PMOS transistor is connected to the drain of the first PMOS transistor and one end of the first capacitor, and the drain of the third PMOS transistor and the other end of the first capacitor are grounded; the source of the second PMOS transistor is connected to the power supply V DDL, its gate is connected to the source of the fourth PMOS transistor and the drain of the sixth PMOS transistor; the gate of the fourth PMOS transistor is connected to the drain of the second PMOS transistor and one end of the second capacitor, and the drain of the fourth high-voltage PMOS transistor and the other end of the fourth capacitor are grounded;

[0015] The fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, and the first resistor form a high-order compensation circuit; among them, the source of the fifth PMOS transistor is connected to the power supply V DDL , its gate is connected to the source of the fourth PMOS transistor, the gate and drain of the sixth PMOS transistor, the gate of the ninth PMOS transistor, and the source of the eighth PMOS transistor, and the drain of the fifth PMOS transistor is connected to the source of the seventh PMOS transistor; the sources of the sixth PMOS transistor, the ninth PMOS transistor, and the eleventh PMOS transistor are connected to the power supply V DDL , the drain of the ninth PMOS transistor is connected to the source of the tenth PMOS transistor; the gate of the seventh PMOS transistor is connected to the gate and drain of the eighth PMOS transistor, the gate of the tenth PMOS transistor, and the drain of the second NMOS transistor, and the drain of the seventh PMOS transistor is connected to the drain and gate of the first NMOS transistor and the gate of the second NMOS transistor; the source and substrate of the first NMOS transistor are grounded; the source of the second NMOS transistor is grounded through the first resistor, and the substrate of the second NMOS transistor is grounded; the drain of the tenth PMOS transistor is connected to the drain and gate of the fifth NMOS transistor and the gate of the sixth NMOS transistor; the source of the fifth NMOS transistor is connected to the drain and gate of the third NMOS transistor and the gate of the fourth NMOS transistor; the source of the third NMOS transistor is grounded; the drains of the sixth NMOS transistor and the eleventh PMOS transistor are connected to the reference voltage, the source of the sixth NMOS transistor is connected to the drain of the fourth NMOS transistor, and the source of the fourth NMOS transistor is grounded; the gate of the eleventh PMOS transistor is connected to the output terminal of the first operational amplifier;

[0016] The twelfth PMOS transistor, the thirteenth PMOS transistor, the fourteenth PMOS transistor, the first operational amplifier, the first triode, the second triode, the third triode, the second resistor, and the third resistor form a BGR core circuit; among them, the source of the twelfth PMOS transistor is connected to the power supply V DDL , its gate is connected to the output terminal of the first operational amplifier, the gate of the thirteenth PMOS transistor, and the gate of the fourteenth PMOS transistor, and the drain of the twelfth PMOS transistor is connected to the negative input terminal of the first operational amplifier and the emitter of the first triode; the base and collector of the first triode are grounded; the source of the thirteenth PMOS transistor is connected to the power supply V DDL, its drain is connected to the positive input terminal of the first operational amplifier and one end of the second resistor; the other end of the second resistor is connected to the emitter of the second triode, and the base and collector of the second triode are grounded; the source of the fourteenth PMOS transistor is connected to the power supply V DDL , its drain is connected to the reference voltage and one end of the third resistor; the other end of the third resistor is connected to the base and collector of the third triode, and the emitter of the third triode is grounded;

[0017] The second operational amplifier, the fifteenth PMOS transistor, the third capacitor, the fourth resistor, the fifth resistor, and the sixth resistor constitute a pre-regulator circuit; among them, the source of the fifteenth PMOS transistor is connected to the power supply V DD , its gate is connected to the output terminal of the second operational amplifier and one end of the third capacitor; the other end of the third capacitor is connected to one end of the sixth resistor; the other end of the sixth resistor is connected to the drain of the fifteenth PMOS transistor, one end of the fifth resistor, and the power supply V DDL ; the other end of the fifth resistor is connected to the positive input terminal of the second operational amplifier and one end of the fourth resistor; the other end of the fourth resistor is grounded; the negative input terminal of the second operational amplifier is connected to the reference voltage;

[0018] The power supply V DDL is a 3.6V voltage, and the power supply V DD is a 4 - 5V voltage.

[0019] The beneficial effect of the present invention is that it solves the problem of noise interference in the extremely light load state of the current switching power supply converter from the source. As the system load gradually changes from heavy to light, the circuit switching frequency will gradually decrease to improve the conversion efficiency. When the switching frequency decreases to the designed lower threshold value, the frequency remains stable and will not continue to decrease. It not only has the advantages of the current mainstream control mode for improving light load efficiency but also solves the noise problem in the extremely light load state. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic diagram of the circuit structure of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] The present invention will be described in detail below with reference to the accompanying drawings.

[0022] The specific circuit diagram of a high - order compensation low - temperature - coefficient bandgap reference circuit based on the substrate bias technology proposed by the present invention is as Figure 1 shown. It consists of 4 parts, namely, a start - up circuit, a high - order compensation circuit, a BGR core circuit, and a pre - regulator circuit. Figure 1 Among them, MN1 and MN2 operate in the sub - threshold region, and the I DS expression of the sub - threshold MOS transistor can be written as:

[0023]

[0024] where μ is the carrier mobility (related to the process and temperature), Cox is the gate oxide capacitance per unit area, and S is the channel width-to-length ratio of the MOS transistor. V GS and V DS are the gate-source voltage and drain-source voltage of the MOS transistor respectively, V th is the threshold voltage, and n is the subthreshold swing factor (usually 1.0 - 1.5), which characterizes the gate control efficiency. Since the influence of V DS on I DS can be ignored, μCoxV T 2 [1 - exp(-V DS / V T )] can be set as I o (it can be considered that I o is a quantity related only to the process and temperature) and can be canceled out in the subsequent analysis.

[0025] By using the equality of the currents of MN1 and MN2, the voltage expression across R1 can be obtained from KVL as follows:

[0026]

[0027] where S 1 and S 2 are the width-to-length ratios of MN1 and MN2 respectively, and V TH under the condition of body bias can be written as:

[0028]

[0029] V TH0 is the threshold voltage at zero substrate bias, and γ is the body effect factor (related only to the process), so the voltage across R1 can be rewritten as:

[0030]

[0031] where φ F = V T ln(n i / N A ) is the Fermi potential, n i is the intrinsic doping concentration, N A is the substrate doping concentration, θ = γ / [2(2φ F ) 1 / 2 , and n is the subthreshold slope factor.

[0032] Furthermore, the voltage drop across V R1 can be obtained as

[0033]

[0034] It can be considered that nVT ln(S 2 / S 1 ) is the PTAT voltage, while nθV T ln(S 2 / S 1 ) is the threshold voltage difference between MN1 and MN2, which can be used to compensate for the temperature non - linear term of V BE of the BJT.

[0035] The current flowing through R1 is copied by a current mirror and amplified, and the current flowing through MN4 is the PTAT term minus the θT term. Subtracting the current on MN4 from the standard PTAT current generated by the reference core, that is, the current flowing through MP11, the PTAT current plus the θT current is obtained, and then it flows into the right - hand branch of the BGR core circuit to generate a reference voltage with high - order compensation, which can be expressed as:

[0036]

[0037] where N = 8 is the emitter area ratio of Q1 and Q2 in the BGR circuit, and a, b, c are current mirror ratios.

[0038] In the present invention, the trimming network is divided into two parts: the trimming of MP9, MP10 and MP11 and the trimming of MP14. That is, the trimming parameters are the current mirror ratios a, b, c. The trimming of MP9 and MP10 is mainly to trim the coefficient of θT, but the trimming of MP9 and MP10 will affect the PTAT voltage. Therefore, in order to avoid the huge change in the PTAT voltage caused by trimming, a similar trimming circuit is connected in parallel to MP11. Since the influence of MP9 and MP10 on the PTAT voltage cannot be completely offset by trimming MP11, trimming only MP3 will make the trimming complicated. In view of this situation, the trimming of MP14 is adopted to solve this problem.

[0039] The key point of the present invention is that the high - order compensation bandgap reference circuit uses the substrate biasing technology. By generating a temperature term highly fitting the high - order non - linear temperature term of the base - emitter voltage V BE of the bipolar transistor through the substrate biasing of the MOS transistor in the sub - threshold region for temperature compensation, the temperature coefficient of the output voltage is greatly reduced; and the circuit injects a trimming current into R3 to achieve error trimming, making it easy to trim and facilitating the solution of the problem of temperature coefficient change caused by various non - ideal factors.

Claims

1. A high-order compensated low temperature coefficient bandgap reference circuit based on substrate bias technology, characterized in that: Including a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first triode, a second triode, a third triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, a third capacitor, a first operational amplifier, and a second operational amplifier; The first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the first capacitor, and the second capacitor constitute a startup circuit; wherein the source of the first PMOS tube is connected to the power supply V DDL The gate of the third PMOS tube is connected to the source of the third PMOS tube and the output of the first operational amplifier; the gate of the third PMOS tube is connected to the drain of the first PMOS tube and one end of the first capacitor, and the drain of the third PMOS tube and the other end of the first capacitor are grounded; the source of the second PMOS tube is connected to the power supply V DDL , its gate is connected to the source of the fourth PMOS tube and the drain of the sixth PMOS tube; the gate of the fourth PMOS tube is connected to the drain of the second PMOS tube and one end of the second capacitor, and the drain of the fourth high-voltage PMOS tube and the other end of the fourth capacitor are grounded; The fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube, the tenth PMOS tube, the eleventh PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, and the first resistor constitute a high-order compensation circuit; wherein the source of the fifth PMOS tube is connected to the power supply V DDL The gate of the fourth PMOS tube is connected to the source of the fourth PMOS tube, the gate and drain of the sixth PMOS tube, the gate of the ninth PMOS tube, the source of the eighth PMOS tube, the drain of the fifth PMOS tube is connected to the source of the seventh PMOS tube; the source of the sixth PMOS tube, the source of the ninth PMOS tube and the source of the eleventh PMOS tube are connected to the power supply V DDL , the drain of the ninth PMOS tube is connected to the source of the tenth PMOS tube; the gate of the seventh PMOS tube is connected to the gate and drain of the eighth PMOS tube, the gate of the tenth PMOS tube, and the drain of the second NMOS tube, the drain of the seventh PMOS tube is connected to the drain and gate of the first NMOS tube, and the gate of the second NMOS tube; the source and substrate of the first NMOS tube are grounded; the source of the second NMOS tube is grounded after passing through the first resistor, and the substrate of the second NMOS tube is grounded; the drain of the tenth PMOS tube is connected to the drain and gate of the fifth NMOS tube, and the gate of the sixth NMOS tube; the source of the fifth NMOS tube is connected to the drain and gate of the third NMOS tube, and the gate of the fourth NMOS tube; the source of the third NMOS tube is grounded; the drain of the sixth NMOS tube and the drain of the eleventh PMOS tube are connected to the reference voltage, the source of the sixth NMOS tube is connected to the drain of the fourth NMOS tube, and the source of the fourth NMOS tube is grounded; the gate of the eleventh PMOS tube is connected to the output end of the first operational amplifier; The twelfth PMOS tube, the thirteenth PMOS tube, the fourteenth PMOS tube, the first operational amplifier, the first triode, the second triode, the third triode, the second resistor, and the third resistor constitute a BGR core circuit; wherein the source of the twelfth PMOS tube is connected to the power supply V DDL The gate of the transistor is connected to the output terminal of the first operational amplifier, the gate of the thirteenth PMOS tube, and the gate of the fourteenth PMOS tube. The drain of the twelfth PMOS tube is connected to the negative input terminal of the first operational amplifier and the emitter of the first transistor. The base and collector of the first transistor are grounded. The source of the thirteenth PMOS tube is connected to the power supply V DDL , its drain is connected to the positive input terminal of the first operational amplifier and one end of the second resistor; the other end of the second resistor is connected to the emitter of the second triode, and the base and collector of the second triode are grounded; the source of the fourteenth PMOS tube is connected to the power supply V DDL , its drain is connected to the reference voltage and one end of the third resistor; the other end of the third resistor is connected to the base and collector of the third triode, and the emitter of the third triode is grounded; The second operational amplifier, the fifteenth PMOS tube, the third capacitor, the fourth resistor, the fifth resistor, and the sixth resistor constitute a pre-voltage stabilization circuit; wherein the source of the fifteenth PMOS tube is connected to the power supply V DD , its gate is connected to the output end of the second operational amplifier and one end of the third capacitor; the other end of the third capacitor is connected to one end of the sixth resistor; the other end of the sixth resistor is connected to the drain of the fifteenth PMOS tube, one end of the fifth resistor and the power supply V DDL ; The other end of the fifth resistor is connected to the positive input end of the second operational amplifier and one end of the fourth resistor; the other end of the fourth resistor is grounded; the negative input end of the second operational amplifier is connected to the reference voltage; The power supply V DDL The voltage is 3.6V, the power supply V DD The voltage is 4~5V.

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