Parallel IGBT junction temperature balancing method and system based on thermal resistance and grid resistance compensation

Abstract

The invention discloses a parallel IGBT junction temperature balancing method and system based on thermal resistance and grid resistance compensation, belongs to the technical field of power electronics, and solves the technical problems that in the prior art, when the temperature difference of parallel IGBTs is caused by the thermal resistance parameter mismatching condition, the parameter matching mode is single, a real object needs to be designed for iterative measurement for matching, and the cost is high. According to the method, circuit parasitic parameters and IGBT static parameters are obtained by using ANSYS software simulation and related measurement equipment, a thermal resistance network model and an electrical loss model are coupled to establish a steady-state junction temperature equalization model, and the grid resistance is dynamically adjusted to compensate thermal resistance mismatch, so that the steady-state junction temperature difference of the parallel IGBTs is reduced, and the stability of the parallel IGBTs is improved. The optimal design enabling the steady-state junction temperature difference of the parallel IGBTs to be the minimum is sought through iterative design and calculation, a real object does not need to be designed for iterative measurement matching, time cost and material cost are greatly saved, and the method has the advantages of being clear, easy and convenient to calculate and low in cost.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronics, and relates to a parallel IGBT junction temperature equalization method and system based on thermal resistance and gate resistance compensation. Background Art

[0002] With the development of magnetic confinement controlled nuclear fusion engineering technology, the capacity of the magnet power supply required to establish a magnetic field in a Tokamak device has also increased. The plasma vertical displacement fast control power supply in the magnet power supply is usually called the fast control power supply. In the Experimental Advanced Superconducting Tokamak (EAST) developed by the Institute of Plasma Physics, Chinese Academy of Sciences, the first-generation fast control power supply was put into use in 2006, with parameters of ±0.8 kV / ±5 kA. The second-generation fast control power supply was put into use in 2014, and the parameters have been improved to ±1.6 kV / ±9 kA. Currently, the fast control power supply in the China Fusion Engineering Test Reactor (CFETR) has also entered the conceptual design stage, and the estimated power supply capacity requirements have reached ±7.46 kV / ±309.74 kA. However, limited by the capacity of power devices, it is difficult to meet the above indicators by selecting a single IGBT module as the switching device in the device. Therefore, the power device parallel technology is an effective way to solve the problem of insufficient rated current of a single power device.

[0003] Currently, the research results on reducing the steady-state junction temperature difference of parallel IGBTs can be roughly divided into the following two categories: The first category of research combines intelligent algorithms with heat conduction equations to optimize the chip or IGBT module layout to achieve the thermal impedance parameter matching of parallel devices, thereby realizing the equalization of the junction temperature difference. For example, the invention patent with the application publication number CN114492039A discloses an IGBT junction temperature estimation method based on a thermal impedance model. By calculating the thermal loss of the IGBT power module and building an equivalent thermal resistance model according to the actual heat conduction path of the IGBT power module, the theoretical junction temperature of the IGBT of the equivalent thermal resistance model is obtained. At the same time, a power unit system including a multi-thermal resistance conduction model is constructed, and the approximation model thermal conductivity method is used to gradually approximate the estimated junction temperature of the IGBT of the multi-thermal resistance conduction model to the theoretical junction temperature of the IGBT of the equivalent thermal resistance model, and finally the thermal conductivity of the multi-thermal resistance conduction model is determined to obtain the accurate estimated junction temperature of the multi-thermal resistance conduction model IGBT.

[0004] The second type is to achieve the balance of the steady-state junction temperature through the parameter matching of the thermal resistance and the emitter parasitic inductance. For example, the invention patent with the application publication number CN111830389A discloses an IGBT junction temperature estimation method based on the temperature of the emitter power terminal, which uses the main controller to send a gate trigger signal to the IGBT gate driver, and at the same time receives the temperature signal on the IGBT power emitter terminal transmitted by the IGBT gate driver, and estimates the IGBT junction temperature according to the temperature signal on the IGBT power emitter terminal, realizes the over-temperature protection of the IGBT, and realizes the IGBT temperature estimation on the controller side. However, the aforementioned first type of method requires intelligent algorithms and finite element simulation iterations, which greatly increases the time cost; while the aforementioned second type of method uses the emitter parasitic parameters to match the imbalance of the thermal resistance, which is not conducive to the design of the power loop.

[0005] In summary, when the thermal resistance parameter mismatch occurs in the prior art, resulting in temperature differences in parallel IGBTs, there is a single parameter matching method, and it is necessary to design physical objects for iterative measurement and matching, resulting in high costs. At the same time, considering that the selection of the gate resistance can adjust the switching loss of the parallel IGBT and does not affect the design of the power loop; in addition, the current in the loop where the gate resistance is located is small, which is convenient for layout and selection, but the prior art has not considered using the gate resistance for junction temperature equalization. Summary of the Invention

[0006] The technical solution of the present invention is used to solve the technical problem that when the thermal resistance parameter mismatch occurs in the prior art, resulting in temperature differences in parallel IGBTs, the parameter matching method is single, and it is necessary to design physical objects for iterative measurement and matching, resulting in high costs.

[0007] The present invention solves the above technical problems through the following technical solutions:

[0008] A method for equalizing the junction temperature of parallel IGBTs based on thermal resistance and gate resistance compensation, including:

[0009] S1. Simulate and extract the parasitic parameters of the designed circuit and determine the working parameters of the circuit;

[0010] S2. Use a preset test tool to measure the IGBT output characteristic data and transmission characteristic data, establish a simulation model, and perform circuit simulation in combination with the stray parameters to obtain the electrical loss data under different working conditions;

[0011] S3. Perform data fitting on the electrical loss data to obtain the loss expression of parallel IGBTs under different working conditions;

[0012] S4. Simulate and extract the thermal resistance parameters of the thermal impedance network of parallel IGBTs in a specific heat dissipation system;

[0013] S5. Combine the loss expression with the thermal impedance network expression to obtain the steady-state junction temperature difference ΔT of the parallel IGBTs. j12 , let ΔT j12 = 0, and solve for the gate resistance matching amount ΔR under the condition of thermal resistance mismatch g1 , and the steady-state junction temperature T of the parallel IGBTs js ;

[0014] S6. Verify whether the steady-state junction temperature T js meets the IGBT junction temperature requirement. If it does not meet the requirement, modify the heat dissipation system and jump to execute S4 until the steady-state junction temperature T js meets the IGBT junction temperature requirement; if it meets the requirement, replace the gate resistance in the actual circuit according to the matching amount ΔR g1 to complete the steady-state junction temperature equalization of the parallel IGBTs.

[0015] Further, the parasitic parameters in S1 include dynamic and static collector parasitic inductances, dynamic and static emitter parasitic inductances, gate parasitic inductance, dynamic drive emitter parasitic inductance, static drive emitter parasitic inductance, static collector parasitic inductance, static emitter parasitic inductance, gate parasitic resistance, dynamic drive emitter parasitic resistance, and static drive emitter parasitic resistance;

[0016] The operating parameters include switching frequency, output current, filter inductor, drive resistance, turn-off voltage, turn-on voltage, input voltage, and output voltage.

[0017] Further, the following logic is used to represent the loss expression in S3:

[0018] E t = (a 1 + a 2 T j1 + a 3 T j2 ) R g1 + (a 4 + a 5 T j1 + a 6 T j2 ) R g2 + a 7 R g1 R g2 + a 8 T j1 2 + a 9 T j1 + a 10 T j2 2 + a 11 T j2 + a 12 T j1 Tj2 +a 13

[0019] Among them, E t is the total loss of an IGBT switching cycle, T j1 , T j2 are the junction temperatures of the parallel IGBTs, R g1 , R g2 are the gate resistances of the parallel IGBTs, a 1 ~a 13 are fitting coefficients.

[0020] Furthermore, the S4 includes:

[0021] S41. Import the 3D model of the heat dissipation system containing parallel IGBTs into ANSYS Icepak, apply a step loss power to the heat source IGBT chip, and obtain the junction temperature response, substrate temperature response, and heat sink temperature response of the IGBT chip;

[0022] S42. Calculate the thermal resistance parameters of the thermal impedance network in the IGBT heat dissipation system according to the junction temperature, substrate temperature, heat sink temperature of the IGBT chip, and the applied step loss power. The thermal resistance parameters include the thermal resistance from the IGBT chip to the substrate, the thermal resistance from the IGBT substrate to the heat sink, and the thermal resistance from the heat sink to the environment.

[0023] Furthermore, the steady-state junction temperature difference ΔT of the parallel IGBTs is represented by the following logic in the S5 j12 :

[0024] ΔT j12 = E t_1 f s (R thjc1 + R thch1 ) - E t_2 f s (R thjc2 + R thch2 )

[0025] Among them, E t_1 , E t_2 are the total losses of the parallel IGBTs, f s is the IGBT switching frequency, R thjc1 , R thjc2 are the thermal resistances from the parallel IGBT chips to the substrate, and R thch1 , R thch2 are the thermal resistances from the parallel IGBT substrates to the heat sink.

[0026] Furthermore, the steady-state junction temperature T of the parallel IGBTs is represented by the following logic in the S5 js :

[0027] Tjs = f s E t_1 (R thjc1 + R thch1 ) + f s (E t_1 + E t_2 )R thha + T a

[0028] wherein, R thha is the thermal resistance from the radiator to the environment, and T a is the ambient temperature.

[0029] Furthermore, in the step S5, the gate resistance matching amount ΔR is represented by the following logic g1 :

[0030] ΔR g1 = R g1f - R g1

[0031] wherein, R g1 is the gate resistance value of the first IGBT, and R g1f is the matched gate resistance, specifically the gate resistance value of the first IGBT corresponding to ΔT j12 = 0.

[0032] The parallel IGBT junction temperature equalization system based on thermal resistance and gate resistance compensation includes:

[0033] A circuit parameter extraction module, configured to simulate and extract the parasitic parameters of the designed circuit and determine the operating parameters of the circuit;

[0034] An IGBT parameter extraction module, configured to measure the IGBT output characteristic data and transmission characteristic data using a preset test tool, establish a simulation model, and perform circuit simulation in combination with the stray parameters to obtain the electrical loss data under different working conditions;

[0035] A data fitting module, configured to perform data fitting on the electrical loss data to obtain the loss expression of the parallel IGBT under different working conditions;

[0036] A thermal impedance network module, configured to simulate and extract the thermal resistance parameters of the thermal impedance network of the parallel IGBT in a specific heat dissipation system;

[0037] A steady-state junction temperature calculation module, configured to combine the loss expression and the thermal impedance network expression to obtain the steady-state junction temperature difference ΔT j12 of the parallel IGBT, set ΔT j12 = 0, solve for the gate resistance matching amount ΔR g1 under the thermal resistance mismatch condition, and the steady-state junction temperature T js of the parallel IGBT;

[0038] A verification module, used to verify whether the steady-state junction temperature T js meets the IGBT junction temperature requirement. If it does not meet the requirement, modify the heat dissipation system and jump to execute the thermal impedance network module until the steady-state junction temperature T js meets the IGBT junction temperature requirement; if it meets the requirement, replace the gate resistor in the actual circuit according to the matching amount ΔR g1 to complete the steady-state junction temperature balance of the parallel IGBTs.

[0039] Further, the parasitic parameters in the circuit parameter extraction module include dynamic and static collector parasitic inductance, dynamic and static emitter parasitic inductance, gate parasitic inductance, dynamic drive emitter parasitic inductance, static drive emitter parasitic inductance, static collector parasitic inductance, static emitter parasitic inductance, gate parasitic resistance, dynamic drive emitter parasitic resistance, and static drive emitter parasitic resistance;

[0040] The operating parameters include switching frequency, output current, filter inductor, drive resistance, turn-off voltage, on-state voltage, input voltage, and output voltage.

[0041] Further, the following logic is used to represent the loss expression in the data fitting module:

[0042] E t = (a 1 + a 2 T j1 + a 3 T j2 )R g1 + (a 4 + a 5 T j1 + a 6 T j2 )R g2 + a 7 R g1 R g2 + a 8 T j1 2 + a 9 T j1 + a 10 T j2 2 + a 11 T j2 + a 12 T j1 T j2 + a 13

[0043] where E t is the total loss of an IGBT in one switching cycle, T j1 , T j2For the parallel IGBT junction temperature, R g1 and R g2 are the gate resistors of the parallel IGBTs, and a 1 to a 13 are fitting coefficients.

[0044] The advantages of the present invention are as follows:

[0045] (1) At the initial stage of the design of power electronic devices, through model calculation and parameter matching calculation, the appropriate gate resistor parameter values can be found. Under different heat dissipation conditions, when there is a thermal resistance mismatch in parallel IGBTs, the gate resistor parameters are adjusted for matching, thereby reducing the steady-state junction temperature difference ΔT j12 of the parallel IGBTs. Designers of power electronic devices do not need to create physical objects for iterative search of the optimal matching scheme, providing a matching scheme for suppressing the steady-state junction temperature mismatch of parallel IGBTs with clear calculation, simplicity and low cost.

[0046] (2) The present invention uses ANSYS software simulation and related measurement equipment to obtain circuit parasitic parameters and IGBT static parameters, couples the thermal resistance network model with the electrical loss model to establish a steady-state junction temperature equilibrium model, calculates the steady-state junction temperature difference as a compensation condition according to the steady-state junction temperature equilibrium model, and dynamically adjusts the gate resistor to compensate for the thermal resistance mismatch, thereby reducing the steady-state junction temperature difference of the parallel IGBTs. The present invention seeks the optimal design that minimizes the steady-state junction temperature difference of the parallel IGBTs through iterative design and calculation, without the need to design physical objects for iterative measurement and matching, saving a large amount of time cost and material cost; and when the thermal resistance parameters of the parallel IGBTs are inconsistent, by adjusting the gate resistor, the steady-state junction temperature difference ΔT j12 of the parallel IGBTs is equal to 0. By replacing physical object iteration with software simulation, the design cost is significantly reduced, and the method of suppressing the excessive steady-state junction temperature difference of the parallel IGBTs has the characteristics of clear calculation, simplicity and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 is a schematic diagram of the basic steps of the parallel IGBT junction temperature equalization method based on thermal resistance and gate resistor compensation according to Embodiment 1 of the present invention;

[0048] Figure 2 is a schematic diagram of the specific steps of obtaining the thermal impedance parameters of the heat dissipation system according to Embodiment 1 of the present invention;

[0049] Figure 3 is a schematic diagram of the electrothermal coupling and thermal impedance network structure according to Embodiment 1 of the present invention;

[0050] Figure 4 is a comparison diagram of the junction temperatures before and after implementing the parallel IGBT junction temperature equalization method and not implementing the parallel IGBT junction temperature equalization method according to Embodiment 1 of the present invention;

[0051] Figure 5 This is a schematic diagram of the specific implementation steps of the parallel IGBT junction temperature equalization method based on thermal resistance and gate resistance compensation in the second embodiment of the present invention. Specific implementation manner

[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0053] The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings of the specification and specific embodiments:

[0054] Embodiment 1

[0055] As Figure 1 shown, specifically, a parallel IGBT junction temperature equalization method based on thermal resistance and gate resistance compensation is disclosed, including the following steps:

[0056] S1. Simulate and extract the parasitic parameters of the designed circuit and determine the operating parameters of the circuit;

[0057] In this embodiment, the PCB of the designed circuit or the 3D model of the copper busbar of the designed circuit is imported into the ANSYS Q3D simulation software to extract the parasitic parameters of the designed circuit and determine the operating parameters of the circuit.

[0058] Furthermore, the parasitic parameters include dynamic and static collector parasitic inductance, dynamic and static emitter parasitic inductance, gate parasitic inductance, dynamic drive emitter parasitic inductance, static drive emitter parasitic inductance, static collector parasitic inductance, static emitter parasitic inductance, gate parasitic resistance, dynamic drive emitter parasitic resistance, and static drive emitter parasitic resistance; the operating parameters include switching frequency, output current, filter inductor, drive resistance, turn-off voltage, conduction voltage, input voltage, and output voltage.

[0059] In this embodiment, through ANSYS / Q3D simulation, the parasitic parameters of the designed circuit are extracted and the operating parameters of the circuit are determined as shown in Table 1 below:

[0060] Table 1 Parasitic parameters and operating parameter table of the designed circuit

[0061]

[0062] In this embodiment, in Table 1, j = 1, 2 is taken to indicate that at most 2 IGBTs are in parallel.

[0063] S2. Measure the IGBT output characteristic data and transmission characteristic data using a preset test tool, establish a simulation model, and perform circuit simulation in combination with the stray parameters to obtain the electrical loss data under different working conditions;

[0064] In this embodiment, use an IGBT static test device to measure the IGBT output characteristic data and transmission characteristic data, import the output characteristic data and transmission characteristic data into the software ANSYS Simplorer for IGBT characterization modeling, create a simulation model corresponding to the IGBT output characteristic data and transmission characteristic data, and in combination with the parasitic parameters extracted in S1, build a corresponding simulation circuit in ANSYS Simplorer for circuit simulation to obtain the IGBT electrical loss data under different junction temperatures and different gate resistances.

[0065] S3. Perform data fitting on the electrical loss data to obtain the loss expressions of parallel IGBTs under different working conditions;

[0066] In this embodiment, perform data fitting on the electrical loss data obtained in S2 according to the loss formula to obtain the loss expressions of parallel IGBTs under different junction temperatures and different gate resistances, and use the following logic to represent the loss expressions:

[0067] E t = (a 1 + a 2 T j1 + a 3 T j2 )R g1 + (a 4 + a 5 T j1 + a 6 T j2 )R g2 + a 7 R g1 R g2 + a 8 T j1 2 + a 9 T j1 + a 10 T j2 2 + a 11 T j2 + a 12 T j1 T j2 + a 13

[0068] Among them, E t is the total loss of an IGBT in one switching cycle, Tj1 、T j2 is the parallel IGBT junction temperature, R g1 、R g2 are the gate resistances of the parallel IGBTs, and a 1 ~a 13 are fitting coefficients.

[0069] In this embodiment, E t_1 、E t_2 respectively represent the total losses of two IGBTs. The fitting results of the total losses of different IGBTs in one switching cycle are shown in Table 2 below:

[0070] Table 2 Fitting Coefficient Table

[0071]

[0072] S4. Simulate and extract the thermal resistance parameters of the thermal impedance network of the parallel IGBTs in a specific heat dissipation system;

[0073] As Figures 2 to 3 shown, in this embodiment, through ANSYS Icepak simulation, the thermal impedance network of the parallel IGBTs in a specific heat dissipation system is extracted. The S4 includes the following specific steps:

[0074] S41. Import the 3D model of the heat dissipation system containing the parallel IGBTs into ANSYS Icepak, apply a step loss power to the heat source IGBT chip, and obtain the junction temperature response, substrate temperature response, and heat sink temperature response of the IGBT chip.

[0075] S42. Calculate the thermal resistance parameters of the thermal impedance network in the IGBT heat dissipation system according to the junction temperature, substrate temperature, heat sink temperature of the IGBT chip, and the applied step loss power. The thermal resistance parameters include the thermal resistance from the IGBT chip to the substrate, the thermal resistance from the IGBT substrate to the heat sink, and the thermal resistance from the heat sink to the environment; in this embodiment, the thermal impedance network parameter data is shown in Table 3 below:

[0076] Table 3 Thermal Impedance Network Parameter Table

[0077]

[0078] S5. Combine the loss expression with the thermal impedance network to obtain the steady-state junction temperature difference ΔT j12 of the parallel IGBTs. Let ΔT j12 = 0, and solve for the gate resistance matching amount ΔR g1 under the condition of thermal resistance mismatch, as well as the steady-state junction temperature T js of the parallel IGBTs;

[0079] In this embodiment, the steady-state junction temperature difference ΔT of the parallel-connected IGBTs is represented by the following logic j12 :

[0080] ΔT j12 = E t_1 f s (R thjc1 + R thch1 ) - E t_2 f s (R thjc2 + R thch2 )

[0081] Wherein, E t_1 , E t_2 are the total losses of the parallel-connected IGBTs, f s is the IGBT switching frequency, R thjc1 , R thjc2 are the thermal resistances from the parallel-connected IGBT chips to the substrate, and R thch1 , R thch2 are the thermal resistances from the parallel-connected IGBT substrates to the heat sink.

[0082] In this embodiment, the steady-state junction temperature T of the parallel-connected IGBTs is represented by the following logic js :

[0083] T js = f s E t_1 (R thjc1 + R thch1 ) + f s (E t_1 + E t_2 )R thha + T a

[0084] Wherein, R thha is the thermal resistance from the heat sink to the environment, and T a is the ambient temperature.

[0085] In this embodiment, the gate resistance matching amount ΔR is represented by the following logic g1 :

[0086] ΔR g1 = R g1f - R g1

[0087] Wherein, R g1 is the gate resistance value of the first IGBT, and R g1f is the matched gate resistance, specifically the gate resistance value of the first IGBT corresponding to ΔT j12 = 0.

[0088] In this embodiment, substituting the fitting data table 2 into the loss expression yields E t_1 and the expression of E t_2 . Considering R thch2 >R thch1 , here, the gate resistance matching amount ΔR g1 is solved for matching. Using the data in Table 1 and the data in Table 3, substituting into the ΔT j12 expression, setting ΔT j12 =0, the calculated gate resistance after matching is R g1f =6.0405 [Ω]; again considering that the gate parasitic resistance R g1 of the drive loop is 10 [mΩ], the gate resistance matching amount ΔR g1 =R g1f -R g1 =6.0305 [Ω]. At the same time, substituting the above data into the steady-state junction temperature T js expression to determine whether the matching condition (i.e., the IGBT junction temperature requirement) T js <400 [K] is satisfied, indicating that the steady-state junction temperature during the long-term safe and stable operation of the Si-based chip needs to be less than 400 [K] (i.e., 125 [°C]). The gate resistance matching amount ΔR g1 and the steady-state junction temperature T js data obtained in this embodiment are as follows:

[0089] ΔR g1 =6.0305 [Ω], T js =385.49 [K]

[0090] In this embodiment, it can be seen from Table 3 that the thermal resistance R thch2 of the second IGBT is greater than the thermal resistance R thch1 of the first IGBT. Therefore, in this embodiment, the correspondingly adjusted gate resistance is R g1 . When calculating the gate resistance matching amount, substitute R g2 into the data in Table 1, and use the gate resistance solved after setting ΔT j12 =0 as R g1f ; correspondingly, if the thermal resistance R thch1 is greater than the thermal resistance R thch2 , then R g1 should be substituted into the values in Table 1 to solve for R g2 .

[0091] This embodiment can, in the case of inconsistent thermal resistance parameters of parallel IGBTs, adjust the gate resistance R g1 to make the steady-state junction temperature difference ΔT j12 of the parallel IGBTs equal to 0, effectively suppressing the situation of excessive steady-state junction temperature difference of the parallel IGBTs. The calculation logic is clear and simple, and the design cost is low.

[0092] S6. Verify the steady-state junction temperature T js to see if it meets the IGBT junction temperature requirement. If not, modify the heat dissipation system and jump to execute S4 until the steady-state junction temperature T js meets the IGBT junction temperature requirement; if it meets the requirement, according to the matching amount ΔR g1 replace the gate resistor in the actual circuit to complete the steady-state junction temperature equilibrium of the parallel IGBTs;

[0093] As Figure 4 shown, simulate and verify the foregoing results. In this embodiment, when the steady-state junction temperature T js <400 [K], it is considered that the steady-state junction temperature T js meets the IGBT junction temperature requirement. Modify the gate resistor matching amount in the actual circuit, replace the gate resistor, and complete the matching; if the steady-state junction temperature T js does not meet the IGBT junction temperature requirement, loop to execute steps S4 - S6. By modifying the heat dissipation method of the specific heat dissipation system, replacing the radiator with a smaller thermal resistance, or modifying the layout of the parallel IGBTs, extract the thermal resistance, recalculate the steady-state junction temperature difference ΔT j12 and the gate resistor matching amount ΔR g1 , verify whether the steady-state junction temperature T js meets the IGBT junction temperature requirement, and perform iterative calculation until the steady-state junction temperature T js meets the IGBT junction temperature requirement, and then replace the gate resistor in the actual circuit.

[0094] In the initial design of the power electronic device in this embodiment, through model calculation and parameter matching calculation, the appropriate gate resistor parameter value can be found. Under different heat dissipation conditions, when there is a thermal resistance mismatch in the parallel IGBTs, adjust the gate resistor parameters for matching, so as to reduce the steady-state junction temperature difference ΔT j12 of the parallel IGBTs. The designers of power electronic devices do not need to create physical objects to perform iterative search for the optimal matching scheme, providing a matching scheme for suppressing the steady-state junction temperature mismatch of parallel IGBTs with clear calculation, simplicity and low cost.

[0095] In this embodiment, the ANSYS software simulation and related measurement equipment are used to obtain the circuit parasitic parameters and the IGBT static parameters. The thermal resistance network model and the electrical loss model are coupled to establish a steady-state junction temperature equilibrium model. The steady-state junction temperature difference is calculated according to the steady-state junction temperature equilibrium model as the compensation condition, and the gate resistance is dynamically adjusted to compensate for the thermal resistance mismatch, thereby reducing the steady-state junction temperature difference of the parallel IGBTs. In this embodiment, through iterative design and calculation, the optimal design that minimizes the steady-state junction temperature difference of the parallel IGBTs is sought. There is no need to design physical objects for iterative measurement and matching, which greatly saves time cost and material cost. And when the thermal resistance parameters of the parallel IGBTs are inconsistent, by adjusting the gate resistance, the steady-state junction temperature difference ΔT j12 equals 0. By replacing physical object iteration with software simulation, the design cost is significantly reduced. At the same time, the method of suppressing the excessive steady-state junction temperature difference of the parallel IGBTs has the characteristics of clear and simple calculation and low cost.

[0096] Embodiment 2

[0097] As Figure 2 shown, in this embodiment, the parallel IGBT junction temperature equilibrium method based on thermal resistance and gate resistance compensation further includes the following specific implementation steps:

[0098] S1’: Obtain the 3D model data of the designed circuit;

[0099] S2’: Extract the parasitic parameters of the designed circuit according to Q3D;

[0100] S3’: Measure the output characteristic data and transmission characteristic data of the IGBT;

[0101] S4’: Create a simulation model corresponding to the IGBT according to Simplorer;

[0102] S5’: Perform circuit simulation analysis according to Simplorer to obtain the electrical loss data;

[0103] S6’: Perform data fitting according to the loss formula;

[0104] S7’: Obtain the 3D model data of the thermal impedance network;

[0105] S8’: Import the Icepak simulation;

[0106] S9’: Extract the thermal impedance network;

[0107] S10’: According to the gate resistance R g and the thermal resistance R th matching relationship, calculate the steady-state junction temperature T js ;

[0108] S11’: Verify the steady-state junction temperature Tjs Whether it meets the IGBT junction temperature requirements;

[0109] S12’. If so, replace the gate resistor in the actual circuit to complete the steady-state junction temperature balance of the parallel IGBTs;

[0110] S13’. If not, modify the heat dissipation system and then jump to execute the aforementioned step S7’.

[0111] Embodiment III

[0112] The present invention also provides a parallel IGBT junction temperature equalization system based on thermal resistance and gate resistor compensation, including a circuit parameter extraction module, an IGBT parameter extraction module, a data fitting module, a thermal impedance network module, a steady-state junction temperature calculation module, and a verification module;

[0113] The circuit parameter extraction module is used to simulate and extract the parasitic parameters of the designed circuit and determine the operating parameters of the circuit;

[0114] In this embodiment, the PCB of the designed circuit or the 3D model of the copper busbar of the designed circuit is imported into the ANSYS Q3D simulation software to extract the parasitic parameters of the designed circuit and determine the operating parameters of the circuit.

[0115] Further, the parasitic parameters include dynamic and static collector parasitic inductances, dynamic and static emitter parasitic inductances, gate parasitic inductance, dynamic drive emitter parasitic inductance, static drive emitter parasitic inductance, static collector parasitic inductance, static emitter parasitic inductance, gate parasitic resistance, dynamic drive emitter parasitic resistance, and static drive emitter parasitic resistance; the operating parameters include switching frequency, output current, filter inductor, drive resistance, turn-off voltage, on-state voltage, input voltage, and output voltage.

[0116] The IGBT parameter extraction module is used to measure the IGBT output characteristic data and transmission characteristic data using a preset test tool, establish a simulation model, and perform circuit simulation in combination with the stray parameters to obtain the electrical loss data under different working conditions;

[0117] In this embodiment, an IGBT static test device is used to measure the IGBT output characteristic data and transmission characteristic data, and the output characteristic data and transmission characteristic data are imported into the software ANSYS Simplorer for IGBT characterization modeling to create a simulation model corresponding to the IGBT output characteristic data and transmission characteristic data. In combination with the parasitic parameters extracted in S1, a corresponding simulation circuit is built in ANSYS Simplorer for circuit simulation to obtain the IGBT electrical loss data at different junction temperatures and different gate resistances.

[0118] The data fitting module is used to perform data fitting on the electrical loss data to obtain the loss expressions of parallel IGBTs under different working conditions;

[0119] In this embodiment, the electrical loss data obtained by the IGBT parameter extraction module is fitted according to the loss formula to obtain the loss expressions of parallel IGBTs at different junction temperatures and different gate resistances. The loss expressions are represented by the following logic:

[0120] E t =(a 1 +a 2 T j1 +a 3 T j2 )R g1 +(a 4 +a 5 T j1 +a 6 T j2 )R g2 +a 7 R g1 R g2 +a 8 T j1 2 +a 9 T j1 +a 10 T j2 2 +a 11 T j2 +a 12 T j1 T j2 +a 13

[0121] Among them, E t is the total loss of an IGBT in one switching cycle, T j1 , T j2 are the junction temperatures of parallel IGBTs, R g1 , R g2 are the gate resistances of parallel IGBTs, and a 1 ~a 13 are fitting coefficients.

[0122] The thermal impedance network module is used to simulate and extract the thermal resistance parameters of the thermal impedance network of parallel IGBTs in a specific heat dissipation system;

[0123] In this embodiment, through ANSYS Icepak simulation, the thermal impedance network of parallel IGBTs in a specific heat dissipation system is extracted. The thermal impedance network module includes an import unit and a calculation unit;

[0124] The import unit is used to import the 3D model of the heat dissipation system containing parallel IGBTs into ANSYS Icepak, apply a step loss power to the heat source IGBT chip, and obtain the junction temperature response, substrate temperature response, and heat sink temperature response of the IGBT chip.

[0125] The calculation unit is used to calculate the thermal resistance parameters of the thermal impedance network in the IGBT heat dissipation system according to the junction temperature, substrate temperature, heat sink temperature of the IGBT chip, and the applied step loss power. The thermal resistance parameters include the thermal resistance from the IGBT chip to the substrate, the thermal resistance from the IGBT substrate to the heat sink, and the thermal resistance from the heat sink to the environment.

[0126] The steady-state junction temperature calculation module is used to combine the loss expression and the thermal impedance network expression to obtain the steady-state junction temperature difference ΔT of the parallel IGBTs j12 , let ΔT j12 = 0, and solve for the gate resistance matching amount ΔR under the thermal resistance mismatch condition g1 , and the steady-state junction temperature T of the parallel IGBTs js ;

[0127] In this embodiment, the following logic is used to represent the steady-state junction temperature difference ΔT of the parallel IGBTs j12 :

[0128] ΔT j12 = E t_1 f s (R thjc1 + R thch1 ) - E t_2 f s (R thjc2 + R thch2 )

[0129] where E t_1 , E t_2 are the total losses of the parallel IGBTs, f s is the IGBT switching frequency, R thjc1 , R thjc2 are the thermal resistances from the parallel IGBT chips to the substrate, and R thch1 , R thch2 are the thermal resistances from the parallel IGBT substrates to the heat sink.

[0130] In this embodiment, the following logic is used to represent the steady-state junction temperature T of the parallel IGBTs js :

[0131] T js = f s E t_1 (R thjc1 + R thch1 ) + f s (Et_1 +E t_2 )R thha +T a

[0132] wherein, R thha is the thermal resistance from the radiator to the environment, and T a is the ambient temperature.

[0133] In this embodiment, the following logic is used to represent the gate resistor matching amount ΔR g1 :

[0134] ΔR g1 = R g1f - R g1

[0135] wherein, R g1 is the gate resistor value of the first IGBT, and R g1f is the matched gate resistor, specifically the gate resistor value of the first IGBT corresponding to ΔT j12 = 0.

[0136] The verification module is used to verify whether the steady-state junction temperature T js meets the IGBT junction temperature requirement. If it does not meet the requirement, modify the heat dissipation system and jump to execute the thermal impedance network module until the steady-state junction temperature T js meets the IGBT junction temperature requirement; if it meets the requirement, replace the gate resistor in the actual circuit according to the matching amount ΔR g1 to complete the steady-state junction temperature balance of the parallel IGBTs;

[0137] Perform simulation verification on the foregoing results. In this embodiment, when the steady-state junction temperature T js < 400 [K], it is considered that the steady-state junction temperature T js meets the IGBT junction temperature requirement. Modify the gate resistor matching amount in the actual circuit, replace the gate resistor, and complete the matching; if the steady-state junction temperature T js does not meet the IGBT junction temperature requirement, loop to execute steps S4 - S6. By modifying the heat dissipation method of the specific heat dissipation system, replacing the radiator with a smaller thermal resistance, or modifying the layout of the parallel IGBTs, perform thermal resistance extraction, recalculate the steady-state junction temperature difference ΔT j12 and the gate resistor matching amount ΔR g1 , verify whether the steady-state junction temperature T js meets the IGBT junction temperature requirement, and perform iterative calculation until the steady-state junction temperature T js meets the IGBT junction temperature requirement, and then replace the gate resistor in the actual circuit.

[0138] This embodiment can, in the case of inconsistent thermal resistance parameters of parallel IGBTs, adjust the gate resistor R g1, making the steady-state junction temperature difference ΔT of the parallel IGBTs j12 equal to 0, effectively suppressing the situation of excessive steady-state junction temperature difference of the parallel IGBTs, with clear and simple calculation logic and low design cost.

[0139] In the initial design of the power electronic device in this embodiment, through model calculation and parameter matching calculation, the appropriate gate resistance parameter value can be found. Under different heat dissipation conditions, when the thermal resistance of the parallel IGBTs is mismatched, the gate resistance parameters are adjusted for matching, thereby reducing the steady-state junction temperature difference ΔT of the parallel IGBTs j12 , and the designers of power electronic devices do not need to create physical objects for iterative search of the optimal matching scheme, providing a matching scheme for suppressing the steady-state junction temperature mismatch of parallel IGBTs with clear and simple calculation and low cost.

[0140] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A parallel IGBT junction temperature balancing method based on thermal resistance and gate resistance compensation, characterized in that: include: S1, extract the parasitic parameters of the designed circuit through simulation and determine the working parameters of the circuit; S2. Use a preset test tool to measure the IGBT output characteristic data and transmission characteristic data, establish a simulation model, perform circuit simulation in combination with the stray parameters, and obtain the power loss data under different working conditions; S3, performing data fitting on the electrical loss data to obtain loss expressions under different working conditions of parallel IGBTs; S4, extracting the thermal resistance parameters of the thermal impedance network of the parallel IGBT in a specific heat dissipation system through simulation; S5. Combine the loss expression with the thermal impedance network expression to obtain the steady-state junction temperature difference ΔT of the parallel IGBTs. j12 , let ΔT j12 = 0, solve the gate resistance matching value ΔR under the condition of thermal resistance mismatch g1 , and the steady-state junction temperature T js ; S6, check steady-state junction temperature T js Whether it meets the IGBT junction temperature requirements. If not, modify the heat dissipation system and jump to S4 until the steady-state junction temperature T js Meet the IGBT junction temperature requirements; if it meets the requirements, according to the matching amount ΔR g1 In the actual circuit, the gate resistor is replaced to achieve steady-state junction temperature balance of parallel IGBTs.

2. The parallel IGBT junction temperature balancing method based on thermal resistance and gate resistance compensation according to claim 1, characterized in that: The parasitic parameters described in S1 include dynamic and static collector parasitic inductance, dynamic and static emitter parasitic inductance, gate parasitic inductance, dynamic drive emitter parasitic inductance, static drive emitter parasitic inductance, static collector parasitic inductance, static emitter parasitic inductance, gate parasitic resistance, dynamic drive emitter parasitic resistance and static drive emitter parasitic resistance; The operating parameters include switching frequency, output current, filter inductance, drive resistance, turn-off voltage, turn-on voltage, input voltage and output voltage.

3. The parallel IGBT junction temperature balancing method based on thermal resistance and gate resistance compensation according to claim 1, characterized in that: The loss expression is expressed in S3 using the following logic: E t =(a1+a2T j1 +a3T j2 )R g1 +(a4+a5T j1 +a6T j2 )R g2 +a7R g1 R g2 +a8T j1 2 +a9T j1 +a 10 T j2 2 +a 11 T j2 +a 12 T j1 T j2 +a 13 Among them, E t is the total loss of one IGBT switching cycle, T j1 , T j2 is the junction temperature of the parallel IGBT, R g1 , R g2 is the gate resistance of the parallel IGBT, a1~a 13 is the fitting coefficient.

4. The parallel IGBT junction temperature balancing method based on thermal resistance and gate resistance compensation according to claim 1, characterized in that: The S4 includes: S41, importing the 3D model of the heat dissipation system including the parallel IGBTs into ANSYS Icepak, applying step loss power to the heat source IGBT chip, and obtaining the junction temperature response, substrate temperature response, and heat sink temperature response of the IGBT chip; S42. Calculate the thermal resistance parameters of the thermal impedance network in the IGBT heat dissipation system according to the junction temperature, substrate temperature, heat sink temperature and applied step loss power of the IGBT chip, wherein the thermal resistance parameters include the thermal resistance from the IGBT chip to the substrate, the thermal resistance from the IGBT substrate to the heat sink and the thermal resistance from the heat sink to the environment.

5. The parallel IGBT junction temperature balancing method based on thermal resistance and gate resistance compensation according to claim 1, characterized in that: The following logic is used in S5 to represent the steady-state junction temperature difference ΔT of the parallel IGBTs: j12 : ΔT j12 =E t_1 f s (R thjc1 +R thch1 )-E t_2 f s (R thjc2 +R thch2 ) Among them, E t_1 、E t_2 is the total loss of parallel IGBTs, f s is the IGBT switching frequency, R thjc1 , R thjc2 is the thermal resistance from the parallel IGBT chip to the substrate, R thch1 , R thch2 is the thermal resistance from the parallel IGBT substrate to the heat sink.

6. The parallel IGBT junction temperature balancing method based on thermal resistance and gate resistance compensation according to claim 5, characterized in that: The following logic is used in S5 to represent the steady-state junction temperature T of the parallel IGBTs: js : T js =f s E t_1 (R thjc1 +R thch1 )+f s (E t_1 +E t_2 )R thha +T a Among them, R thha is the thermal resistance from the heat sink to the environment, T a is the ambient temperature.

7. The parallel IGBT junction temperature balancing method based on thermal resistance and gate resistance compensation according to claim 6, characterized in that: In S5, the gate resistance matching amount ΔR is expressed by the following logic: g1 : ΔR g1 =R g1f -R g1 Among them, R g1 is the gate resistance value of the first IGBT, R g1f is the gate resistance after matching, specifically ΔT j12 =0 corresponds to the gate resistance value of the first IGBT.

8. A parallel IGBT junction temperature balancing system based on thermal resistance and gate resistance compensation, characterized in that: include: Circuit parameter extraction module, used to simulate and extract the parasitic parameters of the designed circuit and determine the working parameters of the circuit; An IGBT parameter extraction module is used to measure the IGBT output characteristic data and transmission characteristic data using a preset test tool, establish a simulation model, perform circuit simulation in combination with the stray parameters, and obtain electrical loss data under different working conditions; A data fitting module is used to perform data fitting on the electrical loss data to obtain loss expressions under different working conditions of parallel IGBTs; Thermal impedance network module, used to simulate and extract the thermal resistance parameters of the thermal impedance network of parallel IGBTs in a specific heat dissipation system; Steady-state junction temperature calculation module, used to combine the loss expression with the thermal impedance network expression to obtain the steady-state junction temperature difference ΔT of parallel IGBTs j12 , let ΔT j12 = 0, solve the gate resistance matching value ΔR under the condition of thermal resistance mismatch g1 , and the steady-state junction temperature T of the parallel IGBTs js ; Verification module, used to verify the steady-state junction temperature T js Whether it meets the IGBT junction temperature requirements. If not, modify the heat dissipation system and jump to execute the thermal impedance network module until the steady-state junction temperature T js Meet the IGBT junction temperature requirements; if it meets the requirements, according to the matching amount ΔR g1 In the actual circuit, the gate resistor is replaced to achieve steady-state junction temperature balance of parallel IGBTs.

9. The parallel IGBT junction temperature balancing system based on thermal resistance and gate resistance compensation according to claim 8, characterized in that: The parasitic parameters in the circuit parameter extraction module include dynamic and static collector parasitic inductance, dynamic and static emitter parasitic inductance, gate parasitic inductance, dynamic drive emitter parasitic inductance, static drive emitter parasitic inductance, static collector parasitic inductance, static emitter parasitic inductance, gate parasitic resistance, dynamic drive emitter parasitic resistance and static drive emitter parasitic resistance; The operating parameters include switching frequency, output current, filter inductance, drive resistance, turn-off voltage, turn-on voltage, input voltage and output voltage.

10. The parallel IGBT junction temperature balancing system based on thermal resistance and gate resistance compensation according to claim 8, characterized in that: The data fitting module uses the following logic to express the loss expression: E t =(a1+a2T j1 +a3T j2 )R g1 +(a4+a5T j1 +a6T j2 )R g2 +a7R g1 R g2 +a8T j1 2 +a9T j1 +a 10 T j2 2 +a 11 T j2 +a 12 T j1 T j2 +a 13 Among them, E t is the total loss of one IGBT switching cycle, T j1 , T j2 is the junction temperature of the parallel IGBT, R g1 , R g2 is the gate resistance of the parallel IGBT, a1~a 13 is the fitting coefficient.

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