Digital-analog hybrid integrated circuit netlist extraction method
By extracting and rewriting the digital-to-analog hybrid integrated circuit netlist in the CADENCE software environment, the problem of submodule pin errors when the virtuoso software extracts the verilog language model is solved, and more efficient and accurate digital function simulation is achieved.
Patent Information
- Application Number
- CN202510196810.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-21
- Publication Date
- 2025-06-10
AI Technical Summary
In the simulation of digital-to-analog hybrid integrated circuits, when extracting the verilog language model through virtuoso software, it is easy to cause submodule pin errors, resulting in confusion in simulation data, and requires manual inspection and modification, affecting efficiency.
In the CADENCE circuit assisted design software environment, find the simulation library for the digital-analog hybrid integrated circuit calls that need to be extracted, delete the submodule netlist of the submodule, extract the digital-analog hybrid integrated circuit netlist, rewrite the submodule internal netlist to ensure the consistent pin definition, and merge the netlist to generate a complete digital-analog hybrid integrated circuit netlist.
By directly extracting the underlying module netlist in the form of name maps, we ensure that the pin definition and definition during use are consistent, avoid manual errors, and improve simulation efficiency and accuracy.
Smart Images
Figure CN120124570A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of integrated circuits, relates to integrated circuit simulation technology, and particularly relates to a method for extracting a netlist of a mixed-signal integrated circuit. Background Art
[0002] A mixed-signal integrated circuit refers to an integrated circuit that has both analog circuits and a large number of digital logic circuits. When performing simulation on a mixed-signal integrated circuit, the traditional mode is to instantiate the code written in the Verilog computer language representing the functions of the digital logic circuit and the analog circuit netlist formed by the SPICE language reflecting the analog circuit, and then perform simulation through a test platform. However, the workload of instantiating the SPICE-formatted netlist and the simulation time of this simulation method are too long.
[0003] In view of the above drawbacks, an improved method is not to perform SPICE netlist instantiation, but to directly export the analog circuit in the form of a Verilog language model (verilog_module) through the Virtuoso software. Combine the Verilog code representing the digital logic circuit and the Verilog language model representing the analog circuit for simulation, so that it is actually transformed into traditional digital verification, which can greatly reduce the simulation running time.
[0004] However, when using the Virtuoso software to extract the Verilog language model of the circuit, the Virtuoso software only directly gives the Verilog language model according to the devices used in the circuit diagram and the input and output ports of each device. Since the instantiation of the extracted Verilog language model is mapped according to the position. This instantiation method is prone to errors in the pins of the sub-module when calling other sub-modules, resulting in inconsistent called ports, and thus the simulation data of the entire module is chaotic. Not only can the Verilog language model not be directly used, but also it needs to be checked and modified manually, which is not only error-prone but also affects efficiency. Summary of the Invention
[0005] In view of the defects existing in the above-mentioned prior art, the present invention discloses a method for extracting a netlist of a mixed-signal integrated circuit.
[0006] The method for extracting a netlist of a mixed-signal integrated circuit according to the present invention includes the following steps: Step 1. In the CADENCE circuit-aided design software environment, find the simulation library called by the mixed-signal integrated circuit for which the netlist needs to be extracted; Step 2. Find out each sub-module in the simulation library that directly calls devices and whose functions can be described by a simulation language, and define the set as A; Step 3. Delete the sub-module netlists of all sub-modules in the set A found in Step 2; Step 4. Extract the netlist of the mixed-signal integrated circuit; Step 5. Find the pin descriptions used when all sub-modules in set A are called in the netlist of the mixed-signal integrated circuit; Step 6. Rewrite the internal netlists of each sub-module in set A, specifically: Step 61. Write the pin definitions of each sub-module based on the pin descriptions obtained in Step 5; Step 62. Describe the functions of the sub-modules in a simulation language based on the pin definitions in Step 61 to obtain the sub-module netlists; Step 7. Merge the netlist of the mixed-signal integrated circuit obtained in Step 4 and the sub-module netlists of all sub-modules in set A obtained in Step 6 to obtain a complete netlist of the mixed-signal integrated circuit.
[0007] Preferably, in Step 4, the virtuoso software is used for software extraction.
[0008] Preferably, Step 6 is specifically: delete the connection descriptions after each pin name in the pin descriptions obtained in Step 5 to obtain the pin definitions.
[0009] Preferably, the simulation language used in Step 62 is VERILOG.
[0010] Preferably, the device includes transistors, resistors, and capacitors.
[0011] In the method for extracting the netlist of the mixed-signal integrated circuit according to the present invention, by directly extracting the underlying module netlist in the form of name mapping using a computer, the pin definitions of the underlying modules are kept completely consistent with the pin definitions when the entire netlist uses the underlying modules, eliminating the need for manual editing of pin definitions and checking and modification, thereby improving the efficiency and accuracy of digital function simulation of the mixed-signal integrated circuit. Description of the Drawings
[0012] Figure 1 The figure shows a schematic flowchart of a specific embodiment of the method for extracting the netlist of the mixed-signal integrated circuit according to the present invention. Specific Embodiment
[0013] To more intuitively and clearly describe the specific details of the technical solution of the present invention, the following will be described in detail in combination with specific embodiments and example drawings.
[0014] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the specific embodiments of the present invention and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.
[0015] The method for extracting the netlist of the digital-analog hybrid integrated circuit according to the present invention includes the following steps: Step 1. In the CADENCE circuit-aided design software environment, find the simulation library called by the digital-analog hybrid integrated circuit for which the netlist needs to be extracted. Step 2. Find each sub-module in the simulation library that directly calls devices and whose functions can be described in the simulation language, and define the set as A. Step 3. Delete the sub-module netlists of all the sub-modules in the set A found in Step 2. Step 4. Extract the netlist of the digital-analog hybrid integrated circuit. Step 5. Find the pin descriptions used when calling all the sub-modules in the set A in the netlist of the digital-analog hybrid integrated circuit. Step 6. Rewrite the internal netlists of each sub-module in the set A, specifically: Step 61. Based on the pin descriptions obtained in Step 5, write the pin definitions of each sub-module. Step 62. Based on the pin definitions in Step 61, describe the functions of the sub-modules in the simulation language to obtain the sub-module netlists. Step 7. Merge the netlist of the digital-analog hybrid integrated circuit obtained in Step 4 and the sub-module netlists of all the sub-modules in the set A obtained in Step 6 to obtain the complete netlist of the digital-analog hybrid integrated circuit.
[0016] The method for extracting the netlist of the digital-analog hybrid integrated circuit according to the present invention is based on the use of CADENCE circuit-aided design software. In the environment of this aided design software, each circuit module in the analog circuit is stored in a circuit library at a certain path. By calling the circuit module name, a complete top-level circuit can be finally built.
[0017] The complete form of the netlist of each circuit module stored in the circuit library is as follows: Module xnor2(Y,A,B,DNW,VN,VP); Output Y; Input A,B,DNW,VN,VP; Specify Specparam CDS_LIBNAME = "GM605AA_TT"; Endspecify; nd2 I3 (net13, DNW, VN, VP, net2, net11); nd2 I2 (net11, DNW, VN, VP, B, net9); nd2 I1 (net12, DNW, VN, VP, A, net9); nd2 I0 (net9, DNW, VN, VP, A, B); inv1 I4(Y, DNW, VN, VP, net13); endmodule Among them, the first line XOR2 represents the current module name. The pins involved in all external connections of this model are in the parentheses after the current module name; Output and Input respectively represent the definitions of the output pins and input pins for all the pins of the current module in the first line; Specify represents the definitions of the library called in the model, the corresponding model name in the library, and the netlist storage location; nd2 is the module name of the sub-module called by this circuit module. The corresponding sub-module already exists in the library. Subsequently, I3 is the name given to the sub-module in the current module netlist. Then, in the parentheses are the connection lines of each pin of this sub-module in the current module netlist.
[0018] For example, for the I3 sub-module, the nd2 circuit module in the library is called. This circuit module has 6 pins, which are respectively connected to the connection lines net13, DNW, VN, VP, net2, and net11.
[0019] The sub-module may be a bottom-layer module. A bottom-layer module means that this circuit module does not call any other circuit modules in the library, but only calls devices in the library such as MOS transistors, resistors, capacitors and other basic components to form a circuit module.
[0020] The sub-module may also be a non-bottom-layer module. A non-bottom-layer module means that it calls at least one circuit module in the library that is not a device.
[0021] For example, the nd2 module only calls two devices, NMOS transistors and PMOS transistors, in the library, so it is a bottom-layer module, while the xnor2 calls a circuit module like nd2, so it is a non-bottom-layer module.
[0022] When performing digital netlist extraction in the prior art, for the device models formed by extraction, digital simulation cannot be directly performed. For example, a specific instance of extracting the netlist from the underlying module nd2 circuit module is as follows: Module nd2 (y,dnw,vn,vp,a,b) pmos_5t M1 [dpw(vn),d(y),b(vp),g(b),s(vp)] pmos_5t M0 [dpw(vn),s(vp),d(y),g(a),b(vp) ] nmos_5t M2 [dnw(dnw),b(vn),d(y),g(b),s(net26) ] nmos_5t M3 [dnw(dnw),d(net26),b(vn),g(a),s(vn) ] In the first line, the names of the respective pins of the nd2 circuit module are within the brackets. The second to fifth lines are the device connection relationships within the module. Taking the second line as an example, pmos_5t represents the device name, M1 represents the device number, and the brackets list the respective ports of the device, and the small brackets contain the connection names corresponding to the ports.
[0023] In the above-extracted netlist, the devices pmos_5t and nmos_5t cannot be called by the digital simulation tool, making the entire nd2 model unable to perform digital simulation.
[0024] Therefore, the existing processing method is to directly perform a digitally simulatable language function description on the nd2 module by hand. A specific description method is as follows: Module nd2 (y,dnw,vn,vp,a,b) Assign y=a&b The second line represents the digital logic implemented by the nd2 module in the simulation language VERILOG. Since this digital logic has nothing to do with the connection relationships of the dnw, vn, vp pins listed in the first line, these 3 pins are not used. During the digital logic simulation process, it is default that the connections of all pins such as the power supply, ground, substrate, etc. of all devices that have nothing to do with the implementation of the digital logic are all correct.
[0025] Since the arrangement order of the pins in the first line of the underlying module such as the above-mentioned nd2 circuit module called is manually input, it may be entered incorrectly. Once entered incorrectly, the corresponding connection relationships of the pins of the called underlying module will be incorrect.
[0026] In the present invention, all the netlists stored in each underlying module are deleted. After deletion, extraction is performed using the virtuoso software. Since the netlist within the underlying module is deleted, during the extraction process, when the virtuoso software calls the underlying module, it can only read the pin information defined by the underlying module. The pin names are used to define each connection point of the underlying module. When the generated netlist calls the underlying module, each pin and connection line adopt a name mapping relationship. For example, the specific manifestation form of the underlying module nd2 in the extracted netlist is as follows: nd2 I3 (y(net13), dnw (dnw), vn (vn), vp (vp),a(net2),b(net11)); For the pin connections of each underlying module, they are uniformly described in the name mapping relationship of "pin name (connection line)". For example, in the above embodiment, A, DNW, VN, VP, B, and Y respectively represent the pin names of the underlying module nd2, and net13, dnw, vn, vp, net2, and net11 respectively represent the connection lines of these six pins A, DNW, VN, VP, B, and Y.
[0027] Meanwhile, using the verilog simulation language, without changing the pin definitions, the functions of the underlying model nd2 with the internal netlist deleted are described and defined in the form of a simulation language to obtain the underlying module model in the form of a simulation language; combining the extracted netlist with these newly written underlying module models generates a new netlist, and then simulation can be performed.
[0028] For example, when an engineer describes the nd2 module in a computer language recognizable for digital simulation, such as the verilog language, the netlist of the underlying module extracted by the computer can be directly copied, and the connection lines can be deleted to obtain the pin definitions of the underlying module. Since the netlist extracted by the computer is directly copied, the pin names and arrangement order cannot be incorrect.
[0029] For example, according to the netlist of the underlying module nd2 extracted by the computer nd2 I3 (y(net13), dnw (dnw), vn (vn), vp (vp),a(net2),b(net11)); By deleting the connection lines after the pins, the pin definitions of the nd2 module can be obtained Module nd2 (y, dnw, vn, vp,a,b) Then add the function description language: Assign y=a&b To obtain the complete computer language model of the underlying module nd2 Module nd2 (y, dnw, vn, vp, a, b) Assign y = a & b。
[0030] For all bottom-level modules and non-bottom-level modules containing devices, since digital simulation tools cannot handle these sub-modules of bottom-level modules and non-bottom-level modules containing devices, the above method needs to be used for processing. The computer is used to extract the netlist for pin description, and then the module function language is added manually to realize the digital simulation definition of the sub-module.
[0031] By using the netlist extraction method described in the present invention, it is possible to avoid the model pin wiring errors caused by manual input pin errors, change the original position mapping relationship to name mapping, and the obtained model conforms to the digital verification format without too many modifications. It not only improves the accuracy but also shortens the working time.
[0032] The foregoing are the preferred embodiments of the present invention. If the preferred implementation manners in each preferred embodiment are not obviously self-contradictory or premised on a certain preferred implementation manner, the preferred implementation manners can be arbitrarily superimposed and combined for use. The embodiments and the specific parameters in the embodiments are only for clearly expressing the inventor's invention verification process, and are not used to limit the patent protection scope of the present invention. The patent protection scope of the present invention still depends on its claims. All equivalent structural changes made by using the content of the specification and drawings of the present invention should be included in the protection scope of the present invention by the same token.
Claims
1. A method for extracting a netlist of a digital-analog hybrid integrated circuit, characterized in that , including the following steps: Step 1. In the CADENCE circuit-aided design software environment, find the simulation library called by the mixed-signal integrated circuit whose netlist needs to be extracted; Step 2. Find out the submodules in the simulation library that directly call the device and can describe the functions in the simulation language, and define the set as A; Step 3. Delete the submodule netlists of all submodules in set A found in step 2; Step 4. Extract the digital-analog hybrid integrated circuit netlist; Step 5. Find the pin description used when calling all submodules in set A in the digital-analog hybrid integrated circuit netlist; Step 6. Rewrite the internal netlist of each submodule in set A, specifically: Step 61. Based on the pin description obtained in step 5, write the pin definition of each submodule; Step 62. Based on the pin definition of step 61, describe the submodule function in simulation language to obtain the submodule netlist; Step 7. Combine the netlist of the digital-analog hybrid integrated circuit obtained in step 4 and the sub-module netlists of all sub-modules in set A obtained in step 6 to obtain a complete netlist of the digital-analog hybrid integrated circuit.
2. The method for extracting a netlist of a digital-analog hybrid integrated circuit according to claim 1, wherein: In step 4, virtuoso software is used to perform software extraction.
3. The method for extracting a netlist of a digital-analog hybrid integrated circuit according to claim 1, wherein: The step 6 specifically includes: deleting the connection line description after each pin name in the pin description obtained in step 5 to obtain the pin definition.
4. The method for extracting a netlist of a digital-analog hybrid integrated circuit according to claim 1, wherein: The simulation language used in step 62 is VERILOG.
5. The method for extracting a netlist of a digital-analog hybrid integrated circuit according to claim 1, wherein: The devices include transistors, resistors, and capacitors.