Sectional driving framework for detecting and adjusting slew rate of BOOST power tube

Abstract

The invention relates to a sectional driving framework for detecting and adjusting the slew rate of a BOOST power tube, which comprises a logic and dead zone module for receiving a PWM (Pulse Width Modulation) signal, and a level shifting module, a high-side driving circuit and a high-side power tube which are sequentially connected with the logic and dead zone module, the slope detection and dynamic adjustment module, the low-side driving circuit and the low-side power tube are sequentially connected with the logic and dead zone module, the slope detection and dynamic adjustment module is connected with a source electrode of the high-side power tube and a drain electrode of the low-side power tube, and the logic and dead zone module processes the PWM signal and then generates a switch control signal. The slope detection and dynamic adjustment module receives the switch control signal, detects the slew rate of the low-side power tube when the low-side power tube is turned off, and controls the parallel number of driving tubes in the low-side driving circuit according to a detection result, and the low-side driving circuit outputs a low-side driving signal according to the parallel number of the driving tubes; and the low-side driving signal controls the on and off of the low-side power tube.

Description

Technical Field

[0001] The present invention relates to the technical field of gate drive of BOOST power transistors, and particularly to the detection and regulation of the rate of change of the voltage of a power transistor driven by a gate driver. More specifically, it relates to a segmented drive architecture for detecting and regulating the slew rate of a BOOST power transistor. Background Art

[0002] Benefiting from the superior conductivity of metal-oxide-semiconductor field-effect transistors (MOS transistors), the switching frequency (F SW ) of a BOOST power converter can soar to several megahertz or even dozens of megahertz, and at the same time, the efficiency of the BOOST power supply can be significantly improved.

[0003] However, during the switching process of a MOS power transistor, due to the distributed capacitance (C GS ) between the input and output, under the action of inverting amplification, the equivalent input capacitance value is amplified, and this process will form a "Miller plateau", making the switching process slow. At the same time, the Miller plateau causes a large overlap between the drain-source voltage V DS and the drain current I D , resulting in energy loss, increased power consumption, and decreased system stability.

[0004] As the switching speed increases, the gate drive current I G of the power transistor can be increased to increase dI / dt (i.e., the slope of the drain current I D ) and dV / dt (i.e., the slope of the drain-source voltage V DS ) to accelerate the turn-on or turn-off, reduce the influence of the Miller plateau, and minimize energy loss. However, excessive dI / dt and dV / dt may result in very steep V DS voltage transients and I D current transients, and then reliability problems such as EMI noise and gate oscillation may occur. More seriously, due to the existence of parasitic inductance at the PIN terminals of the chip, during the switching process (especially during the turn-off process of the BOOST low-side power transistor), too fast a change in inductance current (excessive dI / dt) will cause a voltage drop across the parasitic inductance, and the drain-source voltage V DS of the power transistor will have a large overshoot, increasing the risk of breakdown of the power transistor.

[0005] In order to slow down the commutation speed of the inductor current during the switch transition and reduce the overvoltage drop on the power transistor, there are currently two active gate control techniques: 1) The digital open-loop method can achieve segmented update during the switching transient, but the complex digital algorithm and the performance of the gate drive process limit its application in the drive circuit, and the control sequence in this method cannot adaptively change with the load and input voltage; 2) Adding a gate resistor to the gate of the power transistor. This technique can reduce the gate charging and discharging current, thereby reducing dI / dt and dV / dt, but this method sacrifices the switching speed of the MOS transistor and will also greatly increase the conduction delay and switching loss. Summary of the Invention

[0006] To solve the problems in the above-mentioned prior art, the present invention provides a segmented drive architecture for detecting and adjusting the slew rate of a BOOST power transistor, which can reduce the voltage overshoot caused by the too-fast current commutation on the parasitic inductor during the switch transition without affecting the switching speed and switching loss, thereby improving the stability of the system.

[0007] A segmented drive architecture for detecting and adjusting the slew rate of a BOOST power transistor provided by the present invention includes a logic and dead zone module for receiving a PWM signal, a level shift module, a high-side drive circuit, and a high-side power transistor sequentially connected to the logic and dead zone module, and a slope detection and dynamic adjustment module, a low-side drive circuit, and a low-side power transistor sequentially connected to the logic and dead zone module. The slope detection and dynamic adjustment module is respectively connected to the source of the high-side power transistor and the drain of the low-side power transistor; the logic and dead zone module processes the PWM signal to generate a switch control signal. The slope detection and dynamic adjustment module receives the switch control signal, detects the slew rate of the low-side power transistor when the low-side power transistor is turned off, and controls the number of parallel-connected drive transistors in the low-side drive circuit according to the detection result. The low-side drive circuit outputs a low-side drive signal according to the number of parallel-connected drive transistors, and the low-side drive signal controls the conduction and turn-off of the low-side power transistor.

[0008] Further, the two output terminals of the logic and dead zone module are respectively connected to the input terminal of the level shift module and the first input terminal of the slope detection and dynamic adjustment module. The output terminal of the level shift module is connected to the input terminal of the high-side drive circuit, and the output terminal of the high-side drive circuit is connected to the gate of the high-side power transistor.

[0009] Further, the output terminal of the slope detection and dynamic adjustment module is connected to the input terminal of the low-side drive circuit, the output terminal of the low-side drive circuit is connected to the gate of the low-side power transistor, and the drain of the low-side power transistor is respectively connected to the source of the high-side power transistor and the second input terminal of the slope detection and dynamic adjustment module.

[0010] Further, the drain of the low-side power transistor is connected to an external inductor, and the drain of the high-side power transistor is connected to an external load.

[0011] Further, the slope detection and dynamic adjustment module includes a slope detector, a V-I converter, and a current comparator connected in sequence. The slope detector detects the change rate of the drain-source voltage of the low-side power transistor and converts the change rate of the drain-source voltage into a changing voltage signal. The V-I converter converts the changing voltage signal into a changing current signal, and the changing current signal is compared with a preset current threshold in the current comparator to detect whether the change rate of the drain-source voltage of the low-side power transistor reaches a preset value, so as to output a drive control signal to control the low-side drive circuit.

[0012] Further, the output end of the slope detector is connected to the input end of the V-I converter, the output end of the V-I converter is connected to the input end of the current comparator, and the output end of the current comparator outputs the drive control signal.

[0013] Further, both the high-side drive circuit and the low-side drive circuit include n PMOS drive transistors and n NMOS drive transistors, where n is a positive integer.

[0014] Further, the sources of the first PMOS transistor, the second PMOS transistor, …, the nth PMOS transistor are connected together and connected to the input power supply; the drains of the first PMOS transistor, the second PMOS transistor, …, the nth PMOS transistor, the drains of the first NMOS transistor, the second NMOS transistor, …, the nth NMOS transistor are connected together; the sources of the first NMOS transistor, the second NMOS transistor, …, the nth NMOS transistor are all grounded; the gates of the first PMOS transistor, the second PMOS transistor, …, the nth PMOS transistor, the gates of the first NMOS transistor, the second NMOS transistor, …, the nth NMOS transistor are all connected to the output of the drive circuit.

[0015] The present invention can, on the premise of ensuring a large dV / dt and not affecting the switching speed and switching loss, the slope detection and dynamic adjustment module can adjust the number of drive transistors in the drive circuit during the inductor current commutation stage according to the breakdown voltage of the power transistor and the actual requirements, so as to adjust the magnitude of the current and the inductor current commutation speed dI / dt, reduce the voltage drop on the parasitic inductor and the overshoot voltage on the power transistor, and further improve the stability and reliability of the system. The implementation structure of the present invention is simple, the use cost is low, and it is safe and reliable. Description of the Drawings

[0016] Figure 1It is the basic block diagram of the segmented driving architecture for detecting and adjusting the slew rate of the BOOST power transistor according to the present invention.

[0017] Figure 2 It is the specific structural schematic diagram of the segmented driving architecture for detecting and adjusting the slew rate of the BOOST power transistor according to the present invention.

[0018] Figure 3 is Figure 1 the structural schematic diagram of the slope detection and dynamic adjustment module in

[0019] Figure 4 is Figure 1 the structural schematic diagram of the driving circuit in

[0020] Figure 5 It is the working schematic diagram of the segmented driving architecture for detecting and adjusting the slew rate of the BOOST power transistor according to the present invention.

[0021] Figure 6 It is the waveform schematic diagram of the segmented driving architecture for detecting and adjusting the slew rate of the BOOST power transistor according to the present invention. Specific embodiments

[0022] In order to make the purpose, scheme and advantages of the present invention clearer, the specific structure and working principle of the present invention will be described in more detail below with reference to the accompanying drawings. The embodiments mentioned are only used to explain the present invention and are not limited to this embodiment, and are not used to limit the application scope of the present invention.

[0023] The following content aims to enable the public to have a clearer understanding of the present invention, and for those skilled in the relevant art, the present invention can be clearly understood even without the following detailed description.

[0024] Such as Figure 1As shown in the figure, a segmented driving architecture for detecting and adjusting the slew rate of a BOOST power transistor provided by the present invention includes a logic AND dead-time module 10 for receiving a PWM signal, a level-shifting module 21, a high-side driving circuit 22, and a high-side power transistor 23 that are sequentially connected to the logic AND dead-time module 10, and a slew-rate detection and dynamic adjustment module 31, a low-side driving circuit 32, and a low-side power transistor 33 that are sequentially connected to the logic AND dead-time module 10. The slew-rate detection and dynamic adjustment module 31 is respectively connected to the source of the high-side power transistor 23 and the drain of the low-side power transistor 33, and the logic AND dead-time module 10 is also connected to the low-side driving circuit 32. The logic AND dead-time module 10 performs a series of processes such as delaying and inverting the PWM signal to generate a first switch control signal and a second switch control signal. The first switch control signal is converted into a high-side driving signal after passing through the level-shifting module 21 and the high-side driving circuit 22, and the high-side driving signal controls the conduction and cutoff of the high-side power transistor 23. The slew-rate detection and dynamic adjustment module 31 receives the second switch control signal, simultaneously detects the slew rate of the low-side power transistor 33, and controls the number of parallel-connected driving transistors in the low-side driving circuit 32 according to the detection result. The low-side driving circuit 32 outputs a low-side driving signal according to the number of parallel-connected driving transistors and the received second switch control signal, and the low-side driving signal controls the conduction and cutoff of the low-side power transistor 33.

[0025] More specifically, two output terminals of the logic AND dead-time module 10 are respectively connected to the input terminal of the level-shifting module 21 and the first input terminal of the slew-rate detection and dynamic adjustment module 31. The output terminal of the level-shifting module 21 is connected to the input terminal of the high-side driving circuit 22. The level-shifting module 21 is used to shift a switch signal controlled by a low voltage rail into a switch control signal controlled by a high voltage rail. The output terminal of the high-side driving circuit 22 is connected to the gate of the high-side power transistor 23. The output terminal of the slew-rate detection and dynamic adjustment module 31 is connected to the input terminal of the low-side driving circuit 32. The output terminal of the low-side driving circuit 32 is connected to the gate of the low-side power transistor 33. The drain of the low-side power transistor 33 is respectively connected to the source of the high-side power transistor 23 and the second input terminal of the slew-rate detection and dynamic adjustment module 31, and the drain of the low-side power transistor 33 is connected to an external inductor. The drain of the high-side power transistor 23 is connected to an external load.

[0026] Such as Figure 2As shown in the figure, a specific structural schematic diagram of the segmented driving architecture for detecting and adjusting the slew rate of the BOOST power transistor of the present invention is shown, including a logic AND dead zone module 10, a level shifter module 21, a high-side driving circuit 22, and a high-side power transistor 23 that are sequentially connected to the logic AND dead zone module 10, and a slope detection and dynamic adjustment module 31, a low-side driving circuit 32, and a low-side power transistor 33 that are sequentially connected to the logic AND dead zone module 10. The slope detection and dynamic adjustment module 31 is respectively connected to the source of the high-side power transistor 23 and the drain of the low-side power transistor 33, and the logic AND dead zone module 10 is also connected to the low-side driving circuit 32. Among them, the level shifter module 21 consists of two level shifter circuits, and the voltage differences between the high and low potentials of the two level shifter circuits are VH1 and VH2 respectively. The logic AND dead zone module 10 performs a series of processes such as delaying and inverting the PWM signal to generate a first switch control signal and a second switch control signal with power rails both being GND to VBAT. After passing through the level shifter module 21, the power rails of the first switch control signal are respectively shifted to VBST to VBST + VH1 and VSW to VSW + VH2, and then are converted into a high-side driving signal through the high-side driving circuit 22. The high-side driving signal controls the conduction and cutoff of the high-side power transistor 23. The slope detection and dynamic adjustment module 31 receives the second switch control signal, simultaneously detects the slew rate of the low-side power transistor 33, and controls the number of parallel-connected driving transistors in the low-side driving circuit 32 according to the detection result. The low-side driving circuit 32 outputs a low-side driving signal according to the number of parallel-connected driving transistors and the received second switch control signal, and the low-side driving signal controls the conduction and cutoff of the low-side power transistor 33.

[0027] As Figure 3 shown in the figure, a structural schematic diagram of the slope detection and dynamic adjustment module of the present invention is shown. The slope detection and dynamic adjustment module 31 includes a slope detector 311, a V-I converter 312, and a current comparator 313 that are sequentially connected. Among them, the output end of the slope detector 311 is connected to the input end of the V-I converter 312, the output end of the V-I converter 312 is connected to the input end of the current comparator 313, and the output end of the current comparator 313 outputs a driving control signal to control the low-side driving circuit 32. The working principle of this module is that the slope detector detects the change rate of the drain-source voltage of the low-side power transistor 33 at the switch node SW, and converts the change rate of the drain-source voltage into a changing voltage signal, which is output to the V-I converter 312. The V-I converter 312 converts the changing voltage signal into a changing current signal, which is output to the current comparator 313. The changing current signal is compared with a preset current threshold in the current comparator 313 to detect whether the change rate of the drain-source voltage reaches the preset value, so as to output a driving control signal to control the low-side driving circuit 32.

[0028] As Figure 4As shown, a schematic structural diagram of the driving circuit of the present invention is shown. The driving circuit includes a plurality of PMOS driving transistors and a plurality of NMOS driving transistors, which are formed by connecting the sources and drains of MOS devices of the same size in parallel. The switching control signal is the switching control signal jointly output by the logic AND dead zone module 10 and the slope detection and dynamic adjustment module 31 to control the switching of PMOS and NMOS in the driving circuit. Taking the low-side driving circuit as an example, it includes n (n is a positive integer) PMOS driving transistors and n NMOS driving transistors. Specifically, the sources of the first PMOS transistor PM1, the second PMOS transistor PM2,..., the nth PMOS transistor PMn are connected together and connected to the BOOST input power supply VBAT. The drains of the first PMOS transistor PM1, the second PMOS transistor PM2,..., the nth PMOS transistor PMn, the drains of the first NMOS transistor NM1, the second NMOS transistor NM2,..., the nth NMOS transistor NMn are connected together, and this connection point is set as the BOOST switch node SW. The sources of the first NMOS transistor NM1, the second NMOS transistor NM2,..., the nth NMOS transistor NMn are all grounded. The gates of the first PMOS transistor PM1, the second PMOS transistor PM2,..., the nth PMOS transistor PMn, the gates of the first NMOS transistor NM1, the second NMOS transistor NM2,..., the nth NMOS transistor NMn are all connected to the input of the driving circuit. The structure of the high-side driving circuit is the same as that of the low-side driving circuit and will not be described in detail here.

[0029] As Figure 5 shown, a schematic working diagram of the segmented driving architecture of the present invention when the low-side power transistor is turned off and the high-side power transistor is turned on is shown; as Figure 6 shown, a schematic diagram of the working waveform principle of the low-side power transistor under segmented driving control is shown.

[0030] At the initial moment t 1 when the low-side power transistor is turned off, the driving circuit discharges the MOS gate-source capacitance C 1 with a driving current of I GS . The gate-source voltage V GS of the power transistor gradually decreases. The difference between the gate-source voltage V GS and the MOS threshold voltage V TH is greater than the MOS drain-source voltage V DS at this time, and the power transistor is in the linear region.

[0031] At the moment t 2 , the gate-source voltage V GS of the power transistor drops to V M . The difference between the gate-source voltage V GS and the MOS threshold voltage V TH is exactly equal to the drain-source voltage V of the MOS at this timeDS , the power transistor enters the saturation region. Next, the drive current I G no longer discharges the MOS gate-source capacitance C GS , but instead charges the MOS gate-drain capacitance C GD . The charging of C GD causes the MOS drain voltage to gradually rise, thereby causing the MOS drain-source voltage V DS to gradually rise at a rate of VS 1 . The magnitude of the rate of rise dV / dt of the MOS drain-source voltage V DS has the following relationship:

[0032] dV / dt = I G / C GD (1)

[0033] As can be seen from equation (1), when the magnitude of the MOS gate-drain parasitic capacitance C GD is fixed, the magnitude of the rate of rise dV / dt of the MOS drain-source voltage V DS is proportional to the magnitude of the MOS gate terminal drive current I G .

[0034] Since the gate terminal drive current is continuously charging the MOS gate-drain capacitance C GD at this time, and the voltage on the MOS gate-source capacitance C GS does not change, the MOS gate-source voltage V GS remains unchanged at this time and enters the Miller plateau, and the process of the MOS switch becomes slow. The existence of the Miller plateau causes a large overlap between the MOS drain-source voltage V DS and the drain current I D , resulting in energy loss and increased power consumption. Therefore, at the initial stage of MOS turn-off, the gate drive current I G is usually increased to increase dV / dt and thus accelerate MOS turn-off, reduce the influence of the Miller plateau, and minimize energy loss.

[0035] At time t 3 , the MOS drain-source voltage V DS increases to the maximum value, which is approximately V BST , and the Miller plateau ends. At this time, the MOS gate terminal drive current I G no longer charges the MOS gate-drain capacitance C GD , but continues to discharge the MOS gate-source capacitance C GS , the MOS gate-source voltage V GS continues to decrease, and the magnitude of the MOS saturation region drain current I D is:

[0036]

[0037] Among them, un is the carrier mobility, C ox is the gate oxide capacitance per unit area, and W and L are the gate channel width and gate channel length of the MOS respectively.

[0038] As can be seen from Equation (2), V GS decrease leads to the MOS drain current I D starting to gradually decrease at a rate of IS1 from the maximum value I DM , and the inductor current enters the commutation stage and gradually flows from the low-side power transistor to the high-side power transistor.

[0039] Although at time t 3 , the MOS drain-source voltage V DS has increased to the maximum value V BST , due to the parasitic inductance L P1 at the VBST terminal and the parasitic inductance L P1 at the ground terminal (assuming L P1 = L P2 ) at this time, the commutation of the inductor current from the low side to the high side causes a changing current in the two parasitic inductors, and thus a changing voltage ΔV P1 is generated on the parasitic inductors, and its magnitude is:

[0040]

[0041] Therefore, the drain-source voltage drop V DS across the low-side power MOS transistor will gradually overshoot from V BST , until at time t4, the MOS gate-source voltage V GS drops to the MOS threshold voltage V TH , the power transistor turns off, the commutation of the inductor current ends, and the drain-source voltage drop V DS overshoots to the maximum value (V BST + 2ΔV P1 ) at this time. As can be seen from Equation (3), the larger the value of the parasitic inductor, the faster the commutation speed of the inductor current, the larger the voltage drop generated on the parasitic inductor, and the larger the voltage drop borne by the MOS drain-source voltage drop V DS , and there may even be a risk of the power transistor being broken down.

[0042] In order to slow down the commutation speed of the inductor current, reduce the voltage drop generated on the parasitic inductor and the drain-source overshoot voltage on the power transistor, prevent the power transistor from being broken down, and at the same time ensure a large dV / dt to improve the switching speed and reduce the loss, the present invention provides a method of segmented driving.

[0043] At time t 2Starting from a certain moment, the slope detection and dynamic adjustment module can detect the rate of change dV / dt of the drain-source voltage of the low-side power transistor at the switching node SW, and convert the value of this rate of change into a changing current signal to compare with a preset current threshold. If the rate of change dV / dt of the drain-source voltage is greater than the set threshold, the slope detection and dynamic adjustment module will, after a delay of t 2 -t 3 output a drive control signal at moment t 3 to reduce the number of parallel-connected driver transistors in the drive circuit, so that the MOS gate drive current is reduced to I 3 at the initial moment t 2 (I 2 <I 1 ) of the inductive current commutation, and discharge C 2 at the magnitude of t GS , the speed of V GS decrease slows down, thereby reducing the commutation speed of the MOS drain current I D to IS 2 (IS 2 <IS 1 ). As can be seen from Equation (3), the voltage drop generated on the parasitic inductor decreases to ΔV P2 (ΔV P2 <ΔV P1 ). At moment t 5 , the power transistor turns off, the inductive current commutation ends, and the maximum value reached by the overshoot of the drain-source voltage V DS decreases to VBST + 2ΔV P2 . In short, the slope detection and dynamic adjustment module can effectively reduce the voltage drop between the drain and source of the power MOS transistor by reducing the number of parallel-connected driver transistors in the drive circuit, thereby effectively preventing the power MOS transistor from being broken down.

[0044] The present invention provides a segmented drive architecture for detecting and adjusting the slew rate of a BOOST power transistor. In order to ensure a large dV / dt and effectively control dI / dt without affecting the switching speed and switching loss, this drive architecture still discharges C GS with a large drive current at the initial stage of the turn-off of the BOOST low-side power transistor to reduce the influence of the Miller plateau, and at the same time detect dV / dt; the slope detection and dynamic adjustment module can adjust the number of driver transistors in the drive circuit during the inductive current commutation stage according to the breakdown voltage of the power transistor and actual requirements to reduce the drive current, effectively reducing the inductive current commutation speed and the reduction speed of the leakage current I D , effectively reducing the voltage drop on the parasitic inductor and the overshoot voltage on the power transistor, effectively reducing the risk of the power transistor being broken down, improving the overall reliability of the driver, achieving a simple structure, reducing the use cost, and being safe and reliable.

[0001] The above are only the preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various changes can be made to the above embodiments of the present invention. That is, all simple, equivalent changes and modifications made in accordance with the claims and the content of the specification of the present invention application fall within the scope of protection of the claims of the present invention patent. Those not described in detail in the present invention are all conventional technical contents.

Claims

1. A segmented drive architecture for BOOST power tube slew rate detection and regulation, characterized in that: It includes a logic and dead zone module for receiving a PWM signal, a level shift module, a high-side drive circuit and a high-side power tube connected to the logic and dead zone module in sequence, and a slope detection and dynamic adjustment module, a low-side drive circuit and a low-side power tube connected to the logic and dead zone module in sequence, wherein the slope detection and dynamic adjustment module is connected to the source of the high-side power tube and the drain of the low-side power tube respectively; The logic and dead zone module generates a switch control signal after processing the PWM signal, and the slope detection and dynamic adjustment module receives the switch control signal. When the low-side power tube is turned off, the slew rate of the low-side power tube is detected, and the number of parallel drive tubes in the low-side drive circuit is controlled according to the detection result. The low-side drive circuit outputs a low-side drive signal according to the number of parallel drive tubes, and the low-side drive signal controls the conduction and shutdown of the low-side power tube.

2. The segmented drive architecture for BOOST power tube slew rate detection and regulation according to claim 1 is characterized in that: The two output ends of the logic and dead zone module are respectively connected to the input end of the level shift module and the first input end of the slope detection and dynamic adjustment module, the output end of the level shift module is connected to the input end of the high-side drive circuit, and the output end of the high-side drive circuit is connected to the gate of the high-side power tube.

3. The segmented drive architecture for BOOST power tube slew rate detection and regulation according to claim 2 is characterized in that: The output end of the slope detection and dynamic adjustment module is connected to the input end of the low-side drive circuit, the output end of the low-side drive circuit is connected to the gate of the low-side power tube, and the drain of the low-side power tube is respectively connected to the source of the high-side power tube and the second input end of the slope detection and dynamic adjustment module.

4. The segmented drive architecture for BOOST power tube slew rate detection and regulation according to claim 1 is characterized in that: The drain of the low-side power tube is connected to an external inductor, and the drain of the high-side power tube is connected to an external load.

5. The segmented drive architecture for BOOST power tube slew rate detection and regulation according to claim 1 is characterized in that: The slope detection and dynamic adjustment module includes a slope detector, a VI converter and a current comparator connected in sequence. The slope detector detects the change rate of the drain-source voltage of the low-side power tube and converts the change rate of the drain-source voltage into a changing voltage signal. The VI converter converts the changing voltage signal into a changing current signal. The changing current signal is compared with a preset current threshold in the current comparator to detect whether the change rate of the drain-source voltage of the low-side power tube reaches a preset value, so as to output a drive control signal to control the low-side drive circuit.

6. The segmented drive architecture for BOOST power tube slew rate detection and regulation according to claim 5 is characterized in that: The output end of the slope detector is connected to the input end of the VI converter, the output end of the VI converter is connected to the input end of the current comparator, and the output end of the current comparator outputs the drive control signal.

7. The segmented drive architecture for BOOST power tube slew rate detection and regulation according to claim 1 is characterized in that: The high-side driving circuit and the low-side driving circuit both include n PMOS driving tubes and n NMOS driving tubes, where n is a positive integer.

8. The segmented drive architecture for BOOST power tube slew rate detection and regulation according to claim 7 is characterized in that: The source of the first PMOS tube, the source of the second PMOS tube, ..., and the source of the nPMOS tube are connected together and connected to the input power supply; the drain of the first PMOS tube, the drain of the second PMOS tube, ..., the drain of the nPMOS tube, the drain of the first NMOS tube, the drain of the second NMOS tube, ..., and the drain of the nNMOS tube are connected together; the source of the first NMOS tube, the source of the second NMOS tube, ..., and the source of the nNMOS tube are all grounded; the gate of the first PMOS tube, the gate of the second PMOS tube, ..., the gate of the nPMOS tube, the gate of the first NMOS tube, the gate of the second NMOS tube, ..., and the gate of the nNMOS tube are all connected to the output of the driving circuit.

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