Analog-to-digital converter with embedded filter, driving chip and electronic equipment

Abstract

The invention relates to an analog-to-digital converter of an embedded filter, a driving chip and electronic equipment, and the analog-to-digital converter comprises a first analog-to-digital conversion module which is a successive approximation type analog-to-digital converter with a plurality of sampling capacitors and a plurality of sampling periods, the first analog-to-digital conversion module realizes a finite impulse response (FIR) filtering effect on an input sampling signal through charge sharing among sampling capacitors; and while part of the sampling capacitors still perform the process of sampling the input signals, the successive approximation quantization process of the signals on part of the sampling capacitors which have already been sampled is started. The analog-to-digital converter provided by the embodiment of the invention has a filtering characteristic and also has the characteristics of high bandwidth, low power consumption and small area.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technologies, and particularly to an analog-to-digital converter (ADC) with an embedded filter, a driving chip, and an electronic device. Background Art

[0002] An analog-to-digital converter (ADC) is a key bridge connecting digital systems and the physical world. It has an indispensable important position in advanced electronic systems in key fields such as communication, signal acquisition, and even national defense and aerospace, and is usually implemented using integrated circuits (chips).

[0003] In many current applications of wireless receivers, ADC chips are mostly an independent optimal design, which is separated from the front and rear stage modules on the signal chain. Therefore, from the perspective of the complete signal chain system, global optimization has not been achieved. In order to pursue lower overall system power consumption and a better overall system architecture, the joint optimization technology at the front end of the signal chain is particularly important. It has opened up new ideas for the research and development in the field of analog-to-digital conversion and signal chains.

[0004] As Figure 1 shown, the current mainstream analog front end (AFE) solutions in the industry include the following: 1. An independent filter and an independent ADC; 2. A continuous-time ΔΣ (CTDSM) type; 3. A successive approximation register (SAR) type with an embedded switched-capacitor filter.

[0005] Figure 1 In (a), it is an AFE composed of an independent filter and an independent ADC. This is a traditional AFE architecture widely used in wireless receivers. Figure 1 In (b), it is an AFE architecture based on a continuous-time Delta-Sigma modulator (CTDSM). CTDSM is a classic high-precision ADC architecture. Due to its anti-aliasing characteristics, it is usually used as an AFE architecture to replace independent filters and independent ADCs in many wireless receivers in the industry. It can achieve relatively high power consumption within a bandwidth range of dozens of megahertz and has a small area. Figure 1 In (c), it is a SAR ADC architecture with an embedded switched-capacitor filter. It multiplexes the sampling and quantization capacitors in the SAR ADC as switched-filter capacitors, so that the filtered signal can be directly generated on the sampling and quantization capacitors, avoiding an additional independent filter stage. Therefore, it can achieve a small area, low power consumption, and low noise.

[0006] In an AFE (Analog Front End) that adopts an independent filter and independent ADC architecture, the ADC chip is locally optimized as an independent design, being separated from the front and rear stage modules on the signal chain. Therefore, from the perspective of the complete signal chain system, global optimization is not achieved. The additional filter will introduce additional noise and area consumption. Taking CTDSM (Continuous-Time Delta-Sigma Modulator) as the AFE architecture, although a relatively high bandwidth can be achieved through a high-order quantizer and it has a relatively low area at the same time, it is difficult to achieve low power consumption in the high-bandwidth mode. This is because limited by its inherent closed-loop structure, CTDSM has to consume a relatively high power at a relatively high bandwidth. The SAR ADC (Successive Approximation Register ADC) with an embedded switched-capacitor filter has low power consumption and area, but its bandwidth is very limited, usually less than 10 MHz, and it can only be used for filtering and quantization of extremely low-speed signals. This is because the SAR ADC with an embedded switched-capacitor filter must first complete multi-cycle switched-capacitor sampling and filtering operations before the SAR quantization starts. This will greatly extend the time required for the ADC sampling stage and slow down the overall conversion rate of the ADC.

[0007] It can be seen that the ADC architectures of these traditional solutions are difficult to meet the requirements of low area, low power consumption, and high bandwidth simultaneously. Summary of the Invention

[0008] According to one aspect of the present disclosure, there is provided an analog-to-digital converter with an embedded filter, including a first analog-to-digital conversion module, where the first analog-to-digital conversion module is a successive approximation analog-to-digital converter having a plurality of sampling capacitors and a plurality of sampling periods. The first analog-to-digital conversion module realizes the finite impulse response (FIR) filtering effect on the input sampling signal through charge sharing among the respective sampling capacitors; and while part of the sampling capacitors are still sampling the input signal, the successive approximation quantization process of the signals on part of the sampling capacitors that have completed sampling is started.

[0009] In a possible implementation manner, the analog-to-digital converter further includes one or more filtering capacitors; after any sampling capacitor samples the input signal, it is connected to each of the filtering capacitors one by one, and the infinite impulse response (IIR) filtering effect on the input sampling signal is realized through charge sharing with each of the filtering capacitors; and while part of the sampling capacitors are still sampling the input signal or performing IIR filtering, the successive approximation quantization process of the signals on part of the sampling capacitors that have completed sampling and filtering is started.

[0010] In a possible implementation manner, the analog-to-digital converter further includes an amplifier and a second analog-to-digital conversion module, and the first analog-to-digital conversion module, the amplifier, and the second analog-to-digital conversion module form a pipelined successive approximation analog-to-digital converter.

[0011] In a possible implementation manner, the first analog-to-digital conversion module further includes a plurality of analog-to-digital conversion units, and a time-domain interleaving relationship is formed among the respective analog-to-digital conversion units. After all the sampling capacitors of one analog-to-digital conversion unit complete sampling, the next analog-to-digital conversion unit starts the sampling process.

[0012] In a possible implementation manner, all the analog-to-digital conversion units in the first analog-to-digital conversion module include a plurality of switch sampling components, an amplification control switch, a first comparator, and a first successive approximation logic circuit unit. The switch sampling components include a first sampling capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and one or more filtering control switches. Among them,

[0013] The first end of the first sampling capacitor is connected to the first ends of the first switch, the second switch, and the third switch.

[0014] The second end of the first sampling capacitor is connected to the first ends of the fourth switch, the fifth switch, the second end of the third switch, and the first ends of the respective filtering control switches.

[0015] The second end of the second switch accesses a common-mode voltage. The second ends of the first switches of the respective switch sampling components are all connected to the first end of the amplification control switch and the first input end of the first comparator. The second input end of the first comparator is used to receive a preset voltage. The second end of the amplification control switch is connected to the input end of the amplifier. The output end of the first comparator is connected to the first successive approximation logic circuit unit.

[0016] The second ends of the fourth switches of the respective switch sampling components are all connected to the output end of the input buffer.

[0017] The second ends of the fifth switches of the respective switch sampling components are all connected to the first successive approximation logic circuit unit.

[0018] The second ends of the respective filtering control switches are connected to corresponding filtering capacitors.

[0019] In a possible implementation manner, the respective switch sampling components are configured to be in a reset stage, a sampling stage, a filtering stage, a quantization stage, and a residue amplification stage in sequence. Among them, for any one switch sampling component:

[0020] In the reset stage, the second switch and the third switch are turned on, and the first sampling capacitor is in a reset state.

[0021] In the sampling stage, the second switch and the fourth switch are turned on, and the first sampling capacitor performs charge sampling. After sampling for a first duration, the fourth switch is turned off, and after a second delay duration, the second switch is turned off;

[0022] In the filtering stage, the second switch is turned on, and each filtering control switch is sequentially turned on, and each filtering control switch is turned on for a preset duration;

[0023] In the quantization stage, the first switch and the fifth switch are turned on;

[0024] In the residual difference amplification stage, the amplification control switch is turned on.

[0025] In a possible implementation, the i-th switch sampling component is sequentially configured to be in a reset stage, a sampling stage, a filtering stage, a quantization stage, and a residual difference amplification stage starting from the i-th clock cycle, where i is a positive integer.

[0026] According to one aspect of the present disclosure, a driving chip is provided, and the chip includes the analog-to-digital converter with an embedded filter described above.

[0027] According to one aspect of the present disclosure, an electronic device is provided, and the electronic device includes the driving chip described above.

[0028] In a possible implementation, the electronic device includes any one of a display, a smart phone, a smart watch, a smart bracelet, a tablet computer, a laptop computer, an all-in-one computer, an access control device, and an electronic door lock.

[0029] In the embodiments of the present disclosure, charge sharing between each sampling capacitor is set to achieve a finite impulse response (FIR) filtering effect on the input sampling signal; and while some sampling capacitors are still sampling the input signal, the successive approximation quantization process of the signals on some sampling capacitors that have completed sampling is started, which can realize the parallelism of the sampling and quantization processes, accelerate the conversion rate of the ADC, and improve the system bandwidth. Moreover, there is no closed-loop feedback loop in the analog-to-digital converter of the embodiments of the present disclosure, so the sharp deterioration of power consumption at high bandwidth is avoided. It can be seen that the analog-to-digital converter of the embodiments of the present disclosure has the characteristics of high bandwidth, low power consumption, and low area.

[0030] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear according to the following detailed description of exemplary embodiments with reference to the drawings. Description of the Drawings

[0031] The accompanying drawings here are incorporated into the specification and constitute a part of this specification. These drawings show embodiments consistent with the present disclosure and, together with the specification, are used to illustrate the technical solutions of the present disclosure.

[0032] Figure 1 Shows a schematic diagram of the current analog front-end (AFE) solution.

[0033] Figure 2a Shows a schematic diagram of an analog-to-digital converter with an embedded filter according to an embodiment of the present disclosure. Figure 2b Shows Figure 2a The working schematic diagram of the analog-to-digital converter with the embedded filter in

[0034] Figure 3a Shows a schematic diagram of an analog-to-digital converter with an embedded filter according to an embodiment of the present disclosure.

[0035] Figure 3b Shows a schematic diagram of an analog-to-digital converter with an embedded filter according to an embodiment of the present disclosure.

[0036] Figure 4 Shows the timing schematic diagram of the first analog-to-digital conversion module of the embodiment of the present disclosure. Detailed implementation manners

[0037] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings do not have to be drawn to scale unless otherwise specified.

[0038] In the description of the present disclosure, it should be understood that the orientation or positional relationships indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present disclosure.

[0039] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present disclosure, "a plurality" means two or more unless otherwise specifically defined.

[0040] In this disclosure, unless otherwise clearly defined or limited, terms such as "installed", "connected", "linked", "fixed", etc. shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0041] The specifically used word "exemplary" herein means "serving as an example, an embodiment, or illustrative". Any embodiment described as "exemplary" here does not have to be construed as superior to or better than other embodiments.

[0042] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the term "at least one" in this article represents any one of multiple types or any combination of at least two of multiple types. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set composed of A, B, and C.

[0043] In addition, to better illustrate this disclosure, numerous specific details are given in the following specific implementation manners. Those skilled in the art should understand that this disclosure can still be implemented without certain specific details. In some instances, methods, means, elements, and circuits well-known to those skilled in the art are not described in detail in order to highlight the gist of this disclosure.

[0044] An embodiment of this disclosure provides an analog-to-digital converter with an embedded filter, including a first analog-to-digital conversion module. The first analog-to-digital conversion module is a successive approximation analog-to-digital converter having multiple sampling capacitors and multiple sampling periods. The first analog-to-digital conversion module achieves a finite impulse response (FIR) filtering effect on the input sampling signal through charge sharing between the respective sampling capacitors; and while some sampling capacitors are still sampling the input signal, the successive approximation quantization process of the signals on some of the sampling capacitors that have completed sampling is started.

[0045] Embodiments of the present disclosure achieve a finite impulse response (FIR) filtering effect on an input sampling signal by setting charge sharing among sampling capacitors; and while some sampling capacitors are still sampling the input signal, the successive approximation quantization process of the signals on some sampled capacitors that have completed sampling is started, enabling parallelism between the sampling and quantization processes, accelerating the conversion rate of the ADC, increasing the system bandwidth, and since there is no closed-loop feedback loop in the analog-to-digital converter of the embodiments of the present disclosure, the sharp deterioration of power consumption at high bandwidths is avoided. Additionally, there is no need to separately provide a filtering circuit, saving the circuit area overhead. It can be seen that the analog-to-digital converter of the embodiments of the present disclosure has the characteristics of high bandwidth, low power consumption, and low area.

[0046] Embodiments of the present disclosure do not limit the number of sampling capacitors in the first analog-to-digital conversion module and the specific implementation manner of the successive approximation analog-to-digital converter. Those skilled in the art can set according to actual situations and needs. Embodiments of the present disclosure do not limit the specific timing of sampling some sampling capacitors and starting the successive approximation quantization of some sampled capacitors that have completed sampling, nor the specific division method of the number of capacitors in each part. Those skilled in the art can set according to actual situations and needs. The following provides an exemplary introduction to various possible implementation manners of the first analog-to-digital conversion module.

[0047] Please refer to Figure 2a , Figure 2a which shows a schematic diagram of an analog-to-digital converter with an embedded filter according to an embodiment of the present disclosure.

[0048] Please refer to Figure 2b , Figure 2b which shows Figure 2a the working schematic diagram of the analog-to-digital converter with an embedded filter in

[0049] Exemplarily, as Figure 2a shown, the first analog-to-digital conversion module may include a switched-capacitor array module (including each sampling capacitor (C S1 ~C SN ), each switch (φ 1 ~φ N ), a comparator, and a successive approximation logic circuit.

[0050] Exemplarily, as Figure 2a shown, the first end of the switched-capacitor array module is connected to the input analog signal V IN (hereinafter also referred to as the input signal), as Figure 2bAs shown, the N sampling capacitors in the switched-capacitor array module sequentially sample the input signal during the sampling phase; the second end of the switched-capacitor array module is connected to the comparator. The N sampling capacitors in the switched-capacitor array module are sequentially connected to the comparator through switches after sampling, and the filtering effect is achieved through charge sharing. While some capacitors are still in the sampling process, the comparator is started to perform comparison and the output result is input to the successive approximation logic circuit, and the successive approximation quantization process of the signals on some capacitors that have completed sampling is started. The output result of the successive approximation logic circuit is fed back to the first end of the capacitor array module, and the output result of the successive approximation logic circuit is successively fed back to the first sampling capacitor C S1 to the Nth sampling capacitor C SN .

[0051] Of course, it is worth noting that Figure 2a the circuit structure in is an exemplary structure given for introducing the analog-to-digital conversion process of the analog-to-digital converter in the embodiments of the present disclosure, and should not be regarded as a limitation on the embodiments of the present disclosure. Those skilled in the art can set the implementation manner of the first analog-to-digital conversion module according to the actual situation and needs.

[0052] For example, in a possible implementation manner, the analog-to-digital converter may further include one or more filter capacitors; after any sampling capacitor samples the input signal, it can be connected to each filter capacitor one by one, and the infinite impulse response (IIR) filtering effect of the input sampled signal is achieved through charge sharing with each filter capacitor; and while some sampling capacitors are still in the process of sampling the input signal or performing IIR filtering, the successive approximation quantization process of the signals on some sampling capacitors that have completed sampling and filtering can be started. Of course, the specific timing of starting can be set according to the actual situation and needs, and the embodiments of the present disclosure do not make limitations.

[0053] The embodiments of the present disclosure do not limit the specific number of filter capacitors and do not limit the specific size of each filter capacitor. Those skilled in the art can set them according to the actual situation and needs.

[0054] In a possible implementation manner, the analog-to-digital converter may further include an input buffer Buf, where the input buffer Buf is used to buffer the input analog signal (V IN ).

[0055] The embodiments of the present disclosure do not limit the specific implementation manner of the input buffer Buf. Those skilled in the art can use appropriate devices to implement it according to the actual situation and needs.

[0056] In a possible implementation, the first analog-to-digital conversion module may further include a plurality of analog-to-digital conversion units (such as two or more), and a time-domain interleaving relationship is formed among the analog-to-digital conversion units. After all the sampling capacitors of one analog-to-digital conversion unit complete sampling, the next analog-to-digital conversion unit starts the sampling process.

[0057] The analog-to-digital converter will be further introduced below.

[0058] Please refer to Figure 3a , Figure 3a which shows a schematic diagram of an analog-to-digital converter with an embedded filter according to an embodiment of the present disclosure.

[0059] Please refer to Figure 3b , Figure 3b which shows a schematic diagram of an analog-to-digital converter with an embedded filter according to an embodiment of the present disclosure.

[0060] In a possible implementation, as Figure 3a and Figure 3b shown, the analog-to-digital converter may further include an amplifier Amp and a second analog-to-digital conversion module 20, and the first analog-to-digital conversion module 10, the amplifier Amp, and the second analog-to-digital conversion module 20 form a pipelined successive approximation analog-to-digital converter.

[0061] The embodiments of the present disclosure do not limit the specific implementation manners of the amplifier Amp and the second analog-to-digital conversion module 20, and those skilled in the art can implement them using related technologies. Exemplarily, the second analog-to-digital conversion module 20 may include a two-channel time-interleaved 10-bit SAR ADC. The preferred implementation manner of the first analog-to-digital conversion module 10 will be introduced exemplarily below.

[0062] In a possible implementation, as Figure 3a shown, the first analog-to-digital conversion module 10 may include a first analog-to-digital conversion unit CH1 and a second analog-to-digital conversion unit CH2. Each analog-to-digital conversion unit may include a plurality of switch sampling components, an amplification control switch Sc1, a first comparator Cmp1, and a first successive approximation logic circuit unit SAR Logic1. The switch sampling components may include a first sampling capacitor (such as C S1 ~C S8 ), a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, and a plurality of filter control switches (for example, three filter control switches Sf1~Sf3 are included in this example). Among them,

[0063] The first end of the first sampling capacitor (hereinafter introduced by taking C S1 as an example) is connected to the first end of the first switch S1, the first end of the second switch S2, and the first end of the third switch S3.

[0064] The second terminal of the first sampling capacitor C S1 is connected to the first terminal of the fourth switch S4, the first terminal of the fifth switch S5, the second terminal of the third switch S3, and the first terminal of each filter control switch (Sf1~Sf3).

[0065] The second terminal of the second switch S2 is connected to a common-mode voltage (such as ground voltage). The second terminal of the first switch S1 of each switch sampling component is connected to the first terminal of the amplification control switch Sc1 and the first input terminal of the first comparator Cmp1. The second input terminal of the first comparator Cmp1 is used to receive a preset voltage (the magnitude of this preset voltage is not limited in the embodiments of the present disclosure, and those skilled in the art can set it according to actual situations and needs). The amplification control switch Sc1

[0066] The second terminal of is connected to the input terminal of the amplifier Amp (that is, the second terminal of the amplification control switch Sc1 serves as the output terminal of this analog-to-digital conversion unit). The output terminal of the first comparator Cmp1 is connected to the first successive approximation logic circuit unit.

[0067] The second terminal of the fourth switch S4 of each switch sampling component is connected to the output terminal of the input buffer Buf to receive the analog signal V IN ,

[0068] The second terminal of the fifth switch S5 of each switch sampling component is connected to the first successive approximation logic circuit unit SAR Logic1.

[0069] The second terminal of each filter control switch is connected to a corresponding filter capacitor (for example, in this example, it includes three filter capacitors C IIR1 , C IIR2 , C IIR3 ).

[0070] Exemplarily, as Figure 3a shown, the second terminals of the filter control switch Sf1 of the first analog-to-digital conversion unit CH1 and the filter control switch Sf1 of the second analog-to-digital conversion unit CH2 are both connected to the first terminal of the filter capacitor C IIR1 The second terminals of the filter control switch Sf2 of the first analog-to-digital conversion unit CH1 and the filter control switch Sf2 of the second analog-to-digital conversion unit CH2 are both connected to the first terminal of the filter capacitor C IIR2 The second terminals of the filter control switch Sf3 of the first analog-to-digital conversion unit CH1 and the filter control switch Sf3 of the second analog-to-digital conversion unit CH2 are both connected to the first terminal of the filter capacitor C IIR3 First terminal.

[0071] In the embodiments of the present disclosure, the switch types of the amplification control switch Sc1, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and each filtering control switch (Sf1-Sf3) are not limited, and those skilled in the art can set them according to actual situations and needs. For example, the switch can be any one of a relay, a reed switch, a thyristor, a switching diode, a switching triode, an electronic bilateral switch, an optocoupler, a transistor, etc. The transistor can be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) or an Insulated Gate Bipolar Transistor (IGBT). Among them, the transistor can be implemented based on silicon carbide (SiC) or gallium nitride (GaN) to improve performance.

[0072] Exemplarily, the fourth switch S4 and the amplification control switch Sc1 can be designed as bootstrapped switches. The embodiments of the present disclosure do not limit the specific implementation manner of the bootstrapped switch, and those skilled in the art can implement it using related technologies according to actual situations and needs. By setting the fourth switch S4 and the amplification control switch Sc1 as bootstrapped switches, the embodiments of the present disclosure can make the on-resistance of the fourth switch S4 and the amplification control switch Sc1 not change significantly with the input signal level (the gate-source voltage of the bootstrapped switch is the power supply voltage, and the on-resistance is a constant small resistance value), greatly improving the linearity of sampling, and further improving the performance such as the Spurious-Free Dynamic Range (SFDR) of the ADC.

[0073] The embodiments of the present disclosure do not limit the specific implementation manner of the first successive approximation logic circuit unit SAR Logic1. Those skilled in the art can implement it with reference to related technologies according to actual situations and needs. The first successive approximation logic circuit unit SAR Logic1 can perform operations such as initialization control, start conversion, successive approximation control, comparison control, data storage and update, bit switching control, conversion end judgment and output of the SAR ADC. For the specific working content of the first successive approximation logic circuit unit SAR Logic1, please refer to the introduction of related technologies and will not be elaborated here.

[0074] In a possible implementation manner, as Figure 3a shown, both the first analog-to-digital conversion unit CH1 and the second analog-to-digital conversion unit CH2 can include 8 switch sampling components. The switch sampling component includes 3 filtering control switches (Sf1-Sf3), and the number of filtering capacitors is 3 (C IIR1 , C IIR2 , C IIR3) Of course, the number of switch sampling components, filter control switches, and filter capacitors can also be other values, and the embodiments of the present disclosure do not limit this.

[0075] Exemplarily, the capacitance values of the first sampling capacitors in the switch sampling components can be equal or unequal, and the capacitance values of the filter capacitors can be set according to actual situations and requirements, which are not limited herein.

[0076] In a possible implementation manner, among the 8 switch sampling components: the first sampling capacitor (such as C S7 ) of one switch sampling component is obtained by paralleling two capacitors with a capacitance of 2C, the first sampling capacitor (such as C S8 ) of one switch sampling component is obtained by paralleling one capacitor with a capacitance of 2C and two capacitors with a capacitance of C, and the first sampling capacitors (such as C S1 ~C S6 ) of the remaining switch sampling components are capacitors with a capacitance of 4C, where C represents the capacitance of a unit capacitor. Of course, the capacitors can also be set in other ways, and those skilled in the art can set them according to actual situations and requirements.

[0077] The embodiments of the present disclosure do not limit the specific value of the unit capacitor, and those skilled in the art can set it according to actual situations and requirements.

[0078] By multiplexing a large number of circuit structures in the signal filtering stage and the quantization stage, the embodiments of the present disclosure can save the circuit area. In the embodiments of the present disclosure, the conversion of the first analog-to-digital conversion module 10 can be quantized by a step-by-step conversion method. The conversion of the second analog-to-digital conversion module 20 can be a common asynchronous SAR conversion. The step-by-step conversion method of the first analog-to-digital conversion module 10 is introduced exemplarily below. For the asynchronous SAR conversion method adopted by the second analog-to-digital conversion module 20, please refer to the related art and will not be elaborated herein.

[0079] In a possible implementation manner, each switch sampling component is configured to be successively in a reset stage, a sampling stage, a filtering stage, a quantization stage, and a residue amplification stage, where, for any one switch sampling component:

[0080] In the reset stage, the second switch S2 and the third switch S3 are turned on, and the first sampling capacitor C S1 is in a reset state. In this case, both switches at both ends of the first sampling capacitor C S1 are connected to the common-mode voltage, the charge is cleared, and it waits to be awakened by the start command signal. This stage lasts for half or one clock cycle;

[0081] In the sampling stage, the second switch S2 and the fourth switch S4 are turned on, and the first sampling capacitor CS1 Charge sampling is performed. After sampling for the first duration, the fourth switch S4 is turned off. After a delay of the second duration, the second switch S2 is turned off. Exemplarily, during the sampling phase, at this time, the top plate (the first end) of the first sampling capacitor C S1 remains connected to the common-mode voltage, and the bottom plate (the second end) of the first sampling capacitor C S1 is connected to the input signal through a bootstrap switch (φS) for sampling. At the end of sampling, the bottom plate switch is first turned off. After a short delay, the top plate switch is turned off, completing the high-linearity backplane sampling of the input signal. This phase lasts for one clock cycle, for example. Correspondingly, both the first duration and the second duration are less than one clock cycle.

[0082] During the filtering phase, the second switch S2 is turned on, and each of the filtering control switches (Sf1~Sf3) is turned on in sequence, and each filtering control switch is turned on for a preset duration. Exemplarily, in the three clock cycles after sampling, the top plate of the first sampling capacitor C S1 remains connected to the common-mode voltage, while the bottom plate is connected to the filter capacitor C IIR1 -C IIR3 in sequence through the filtering control switch (which can be a transmission gate) (at this time, the other end of the filter capacitor is kept grounded), forming a third-order IIR filter for the input signal.

[0083] During the quantization phase, the first switch S1 and the fifth switch S5 are turned on. Exemplarily, when the first sampling capacitor C S1 completes the IIR filtering, the first end of the first sampling capacitor C S1 will be immediately connected to the first comparator Cmp1, and the second end of the first sampling capacitor C S1 is connected to the first successive approximation logic circuit unit SAR Logic1, converted into a part of the quantization capacitor (C DAC , not shown), and participates in the SAR quantization process of this cycle. This phase will continue until all quantizations are completed.

[0084] During the residue amplification phase, the amplification control switch Sc1 is turned on. Exemplarily, after the quantization phase is completed, a residue voltage after the first-stage quantization is formed on the top plate of C DAC . All the first sampling capacitors are used as a part of the quantization capacitor C DAC and are connected to the residue amplifier Amp for the residue amplification process.

[0085] Compared with the SAR ADC with an embedded switched capacitor in the related art, the ADC according to the embodiments of the present disclosure adopts a step-by-step conversion method, that is, while performing switched-capacitor filtering on some sampling capacitors, quantifying the voltages on another part of the sampling capacitors, realizing the parallelism of the filtering process and the quantization process, accelerating the conversion rate of the ADC, and increasing the system bandwidth.

[0086] The embodiments of the present disclosure do not limit the switching control methods of the amplification control switch Sc1, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and each filtering control switch (Sf1-Sf3), etc. Those skilled in the art can implement them according to the actual situation and needs by using related technologies. For example, the switching control signals prepared in advance can be output by setting a processing component to control each switch.

[0087] The embodiments of the present disclosure do not limit the specific implementation manners of the processing component. In one example, the processing component includes, but is not limited to, a separate processor, or discrete components, or a combination of a processor and discrete components. The processor may include a controller in an electronic device having an instruction execution function, and the processor may be implemented in any suitable manner. For example, it is implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Inside the processor, the executable instructions may be executed through hardware circuits such as logic gates, switches, application specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0088] Exemplarily, as Figure 3a shown, the switching control signals may include φ RA 、φ QTZ 、φ VCM 、φ R 、φ S 、φ T1 、φ T2 、φ T3 etc. The processing component controls the corresponding switches to conduct by outputting the corresponding switching control signals at different time periods, thereby controlling the progress of the analog-to-digital conversion process. Exemplarily, in the reset stage, the processing component may control the second switch S2 and the third switch S3 to conduct through the switching control signals φ VCM 、φ R , and control the rest of the switches to disconnect through the rest of the switching control signals; in the sampling stage, the processing component passes through the switching control signals φ VCM 、φ SControl the second switch S2 and the fourth switch S4 to conduct; in the filtering stage, the processing component controls through the switch control signal φ VCM Control the second switch S2 to conduct, and control through the switch control signal φ T1 、φ T2 、φ T3 Control the filter control switches Sf1 to Sf3 to conduct in sequence; in the quantization stage, the processing component controls through the switch control signal φ QTZ Control the first switch S1 and the fifth switch S5 to conduct; in the residual difference amplification stage, the processing component controls through the switch control signal φ RA Control the amplification control switch Sc1 to conduct.

[0089] In a possible implementation manner, the i-th switch sampling component C Si Is successively configured to be in the reset stage, sampling stage, filtering stage, quantization stage, and residual difference amplification stage starting from the i-th clock cycle, where i is a positive integer. Exemplarily, the first switch sampling component is successively configured to be in the reset stage, sampling stage, filtering stage, quantization stage, and residual difference amplification stage starting from the first clock cycle, the second switch sampling component is successively configured to be in the reset stage, sampling stage, filtering stage, quantization stage, and residual difference amplification stage starting from the second clock cycle, the third switch sampling component is successively configured to be in the reset stage, sampling stage, filtering stage, quantization stage, and residual difference amplification stage starting from the third clock cycle,..., the eighth switch sampling component is successively configured to be in the reset stage, sampling stage, filtering stage, quantization stage, and residual difference amplification stage starting from the eighth clock cycle.

[0090] In this way, 8 switch sampling components start the above five steps (reset stage, sampling stage, filtering stage, quantization stage, and residual difference amplification stage) in sequence in 8 clock cycles. The first sampling capacitor of the signal after IIR filtering will be successively converted into a part of the quantization capacitor C DAC In the SAR control unit and participate in the SAR conversion process. And the charge sharing process accompanying the incorporation into the quantization capacitor C DAC Naturally has the effect of FIR filtering. The quantization process of SAR will proceed step by step as the first sampling capacitor is gradually added. Through the above step-by-step conversion strategy, the filtering process and the quantization process can be maximally overlapped, weakening the speed loss caused by the filtering operation.

[0091] Please refer to Figure 4 , Figure 4 Which shows the timing diagram of the first analog-to-digital conversion module 10 of the present disclosure embodiment.

[0092] Exemplarily, as Figure 4As shown, in the first clock cycle, the first first sampling capacitor CS1 samples the input analog signal V IN .

[0093] Exemplarily, as Figure 4 shown, in the second to fourth cycles, the first first sampling capacitor C S1 and the IIR filter capacitor C IIR1 -C IIR3 perform charge sharing in sequence to complete the filtering operation of the 3rd-order IIR. Meanwhile, the second first sampling capacitor C S2 samples the input analog signal V IN in the second cycle, and then C S2 will follow and repeat each step of the first first sampling capacitor C S1 .

[0094] Exemplarily, as Figure 4 shown, in the fifth cycle, at this time the first first sampling capacitor C S1 has completed the 3-step IIR filtering operation and is immediately connected to the comparator, and is converted into a part of the quantization capacitor C DAC .

[0095] Exemplarily, as Figure 4 shown, in the sixth cycle, at this time the second first sampling capacitor C S2 has also completed the 3-step IIR filtering operation and is immediately connected to the first comparator, and together with the first first sampling capacitor C S1 forms a part of the quantization capacitor C DAC . At this time, the charge sharing that occurs between the second first sampling capacitor C S2 and the first first sampling capacitor C S1 will introduce a 1st-order FIR filtering effect. After the charge sharing is fully established, the first comparator will be immediately started to initiate the first quantization process. Then, according to the result of the first quantization process, the bottom plate of the first first sampling capacitor C S1 will be flipped to complete the quantization of this cycle.

[0096] Exemplarily, as Figure 4 shown, in the seventh to twelfth cycles, each cycle will have a new first sampling capacitor converted into the quantization capacitor C DAC , carrying the filtered signal charge to perform charge sharing with the quantization capacitor C DAC to form a higher-order FIR filtering effect. After the charge sharing is fully established, the comparator will be immediately started to initiate the quantization process of this cycle.

[0097] Exemplarily, as Figure 4As shown, the first analog-to-digital conversion unit CH1 and the second analog-to-digital conversion unit CH2 of the embodiments of the present disclosure are configured in a time-interleaved relationship. After all the sampling capacitors of the first analog-to-digital conversion unit CH1 complete sampling, the second analog-to-digital conversion unit CH2 starts the sampling process and performs response operations of sampling, filtering, and quantization.

[0098] The above process is the stepped conversion strategy. As can be seen from the above process, in the first analog-to-digital conversion module 10 of the embodiments of the present disclosure, the 5-bit quantization accuracy is redistributed within 10 SAR conversion cycles and spread over 7 clock cycles. In the first five clock cycles, only 1-bit SAR quantization is performed, in the subsequent one cycle, 2-bit SAR quantization is performed, and in the last cycle, 3-bit SAR quantization is performed. The weight design of the SAR quantization includes sufficient redundancy to digest the signal charge incorporated into the quantization capacitor C DAC in each clock cycle.

[0099] The above takes the first analog-to-digital conversion module 10 as a two-channel time-interleaved 5-bit SAR ADC with an embedded filtering function and the second analog-to-digital conversion module 20 as a two-channel time-interleaved 10-bit SAR ADC as an example for introduction. However, the above exemplary introduction should not be regarded as a limitation to the embodiments of the present disclosure. In other implementation manners, the first analog-to-digital conversion module 10 and the second analog-to-digital conversion module 20 can also be other implementation manners, and the analog-to-digital conversion accuracy can also be set according to actual situations and needs.

[0100] The ADC solution of the embodiments of the present disclosure mainly has two advantages:

[0101] 1. High bandwidth. The analog-to-digital converter of the embodiments of the present disclosure has a higher bandwidth than the SAR ADC with an embedded switched-capacitor filter. The analog-to-digital converter of the embodiments of the present disclosure adopts a two-channel time-interleaved two-stage pipelined structure, which improves the bandwidth of the circuit. At the same time, a stepped conversion method is introduced into the first analog-to-digital conversion module, so that the filtering sampling and quantization processes can be carried out simultaneously, thereby improving the conversion rate of the ADC and weakening the speed loss problem introduced by the filtering sampling.

[0102] 2. Low power consumption. The analog-to-digital converter of the embodiments of the present disclosure has lower power consumption than the CTDSM. Since there is no closed-loop feedback loop in the analog-to-digital converter of the embodiments of the present disclosure, the sharp deterioration of power consumption under high bandwidth is avoided. The analog-to-digital converter of the embodiments of the present disclosure combines the high energy efficiency characteristics of the SAR ADC structure and the low power consumption characteristics of the switched-capacitor passive filter to realize a high-bandwidth ADC with an embedded filter having lower power consumption. Its low power consumption characteristics make it more suitable for application scenarios such as large-scale integrated receiver systems or the Internet of Things.

[0103] 3. Low area. Compared with the AFE design with an independent filter and an independent ADC, the analog-to-digital converter in the embodiments of the present disclosure adopts an architecture with a combined design of a filter and an ADC, and multiplexes the capacitor as a filter sampling capacitor and a quantization capacitor C respectively in the filtering stage and the quantization stage DAC , avoiding the additional area overhead of the filter, and thus greatly saving the area of the chip.

[0104] In practical applications, the ADC with an embedded filter proposed by the present invention can solve the problem of overall optimization of the analog front end that is difficult to achieve in the traditional architecture, and realize an analog front end design with high bandwidth, low power consumption, and low area. The low-power high-bandwidth ADC with an embedded filter has a broader application scenario. In the next-generation wireless communication system, it is expected to replace CTDSM and become a mainstream analog front-end design architecture at high bandwidths. This overall optimization of the analog front end also makes it possible to integrate chips for the Internet of Things, smart sensors, etc., that is, to implement the design of the analog front end with lower power consumption and smaller area, greatly improving the compactness of related products and reducing the material cost.

[0105] According to one aspect of the present disclosure, a driving chip is provided, and the chip includes the analog-to-digital converter with an embedded filter.

[0106] According to one aspect of the present disclosure, an electronic device is provided, and the electronic device includes the driving chip.

[0107] In a possible implementation manner, the electronic device includes any one of a display, a smart phone, a smart watch, a smart bracelet, a tablet computer, a notebook computer, an all-in-one computer, an access control device, and an electronic door lock.

[0108] Of course, the electronic device may also be other terminal devices. The terminal device may be a user equipment (UE), a mobile device, a user terminal, a terminal, a handheld device, a computing device, or a vehicle-mounted device, etc. Exemplarily, some examples of terminals are: mobile phone, tablet computer, laptop computer, palmtop computer, mobile Internet device (MID), wearable device, virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, wireless terminal in vehicle-to-everything, etc. For example, the server may be a local server or a cloud server.

[0109] The various embodiments of the present disclosure have been described above. The above description is exemplary and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, the practical application, or the improvement of the technology in the market, or to enable other ordinary skill in the art in the technical field to understand the embodiments disclosed herein.

Claims

1. An analog-to-digital converter with an embedded filter, characterized in that: The invention comprises a first analog-to-digital conversion module, which is a successive approximation analog-to-digital converter having a plurality of sampling capacitors and a plurality of sampling periods. The first analog-to-digital conversion module realizes a finite-length unit impulse response (FIR) filtering effect on an input sampling signal by charge sharing between the sampling capacitors; and while some sampling capacitors are still sampling the input signal, a successive approximation quantization process of the signal on some sampling capacitors that have completed sampling is started.

2. The analog-to-digital converter according to claim 1, characterized in that The analog-to-digital converter also includes one or more filter capacitors; after sampling the input signal, any sampling capacitor is connected to each filter capacitor one by one, and an infinite unit impulse response (IIR) filtering effect of the input sampling signal is realized by charge sharing between each filter capacitor; and while some sampling capacitors are still performing the sampling process or IIR filtering of the input signal, the successive approximation quantization process of the signal on some sampling capacitors that have completed sampling and filtering is started.

3. The analog-to-digital converter according to claim 2, characterized in that: The analog-to-digital converter also includes an amplifier and a second analog-to-digital conversion module. The first analog-to-digital conversion module, the amplifier, and the second analog-to-digital conversion module constitute a pipelined successive approximation analog-to-digital converter.

4. The analog-to-digital converter according to claim 3, characterized in that: The first analog-to-digital conversion module also includes a plurality of analog-to-digital conversion units, and each of the analog-to-digital conversion units forms a time domain interleaving relationship. After all sampling capacitors of one analog-to-digital conversion unit complete sampling, the next analog-to-digital conversion unit starts the sampling process.

5. The analog-to-digital converter according to claim 4, characterized in that: All analog-to-digital conversion units in the first analog-to-digital conversion module include multiple switch sampling components, an amplification control switch, a first comparator and a first successive approximation logic circuit unit, wherein the switch sampling component includes a first sampling capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch and one or more filter control switches, wherein: The first end of the first sampling capacitor is connected to the first end of the first switch, the first end of the second switch, and the first end of the third switch. The second end of the first sampling capacitor is connected to the first end of the fourth switch, the first end of the fifth switch, the second end of the third switch and the first end of each filter control switch. The second end of the second switch is connected to the common mode voltage, the second end of the first switch of each switch sampling component is connected to the first end of the amplification control switch and the first input end of the first comparator, the second input end of the first comparator is used to receive a preset voltage, the second end of the amplification control switch is connected to the input end of the amplifier, and the output end of the first comparator is connected to the first successive approximation logic circuit unit. The second end of the fourth switch of each switch sampling component is connected to the output end of the input buffer, The second end of the fifth switch of each switch sampling component is connected to the first successive approximation logic circuit unit. The second end of each filter control switch is connected to the corresponding filter capacitor.

6. The analog-to-digital converter according to any one of claim 5, characterized in that: Each switch sampling component is configured to be in a reset stage, a sampling stage, a filtering stage, a quantization stage, and a residual amplification stage in sequence, wherein for any switch sampling component: In the reset stage, the second switch and the third switch are turned on, and the first sampling capacitor is in a reset state; In the sampling phase, the second switch and the fourth switch are turned on, the first sampling capacitor performs charge sampling, and after sampling for a first time period, the fourth switch is turned off, and after a delay of a second time period, the second switch is turned off; In the filtering stage, the second switch is turned on, each filter control switch is turned on in sequence, and each filter control switch is turned on for a preset time; In the quantization stage, the first switch and the fifth switch are turned on; In the residual amplification stage, the amplification control switch is turned on.

7. The analog-to-digital converter according to claim 6, characterized in that: The i-th switch sampling component is configured to be in the reset stage, sampling stage, filtering stage, quantization stage, and residual amplification stage in sequence starting from the i-th clock cycle, where i is a positive integer.

8. A driver chip, characterized in that: The chip comprises an analog-to-digital converter with an embedded filter as claimed in any one of claims 1-7.

9. An electronic device, characterized in that: The electronic device comprises the driving chip as claimed in claim 8.

10. The electronic device according to claim 9, characterized in that: The electronic device includes any one of a display, a smart phone, a smart watch, a smart bracelet, a tablet computer, a laptop computer, an all-in-one computer, an access control device, and an electronic door lock.

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