PMIC digital clock anomaly detection method, device and chip

Abstract

The embodiments of the present application provide a PMIC digital clock anomaly detection method, device, and chip, which belong to the technical field of integrated power management, including: providing a digital jitter control module, the digital jitter control module being configured to generate a counting window in the digital clock domain, the counting window crossing the clock domain to the analog clock domain to detect the digital clock by counting the number of analog clock cycles, obtaining a detection result of the digital clock, judging whether the detection result is consistent with a preset range, and outputting a corresponding judgment result. The PMIC digital clock anomaly detection method provided in the embodiments of the present application realizes high-precision and low-cost clock monitoring by coordinating digital and analog signals, performing cross-clock domain collaborative detection on the analog clock ana_clk and the digital clock dig_clk, performing dynamic counting, judging the error between the counting window and the cross-clock domain, and performing corresponding processing.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of integrated power management, and specifically to a method, device, and chip for detecting anomalies in a PMIC digital clock. Background Art

[0002] In a functional safety PMIC, the digital control module implements key functions such as power conversion control and dynamic voltage regulation through a clock signal (dig_clk). The stability of the digital clock signal is crucial to system reliability. In related technologies, most PMIC digital components use a single clock source. This approach is simple and low-cost, but if the clock source fails, the entire system will not function properly. Related technologies for detecting digital clock (dig_clk) anomalies primarily rely on deploying dual clock sources (such as primary and backup clocks) in the chip's digital portion, using cross-checking to identify clock anomalies. However, cross-checking of dual clock sources significantly increases chip area and power consumption, no longer meeting expectations and urgently requires improvement. Summary of the Invention

[0003] The main purpose of the embodiments of the present application is to provide a PMIC digital clock anomaly detection method, device and chip to solve the problem in the related art that cross-checking to determine clock anomalies will significantly increase chip area and power consumption.

[0004] The beneficial technical effects of the embodiments of the present application are:

[0005] According to one aspect of an embodiment of the present application, a PMIC digital clock anomaly detection method is provided, including: providing a digital frequency jittering control module, wherein the digital frequency jittering control module is configured to generate a counting window; performing cross-clock domain processing on the digital frequency jittering control module to generate a counting window in the digital clock domain, wherein the counting window crosses the clock domain to the analog clock domain to detect the digital clock; obtaining a detection result of the digital clock, determining whether the detection result is consistent with a preset range, and outputting a corresponding judgment result.

[0006] According to at least one specific implementation of the embodiments of the present application, the digital frequency jittering control module generates a flip signal and generates counting windows of different lengths according to different configurations of the frequency jittering mode.

[0007] According to at least one specific implementation of the embodiments of the present application, the counting window is configured through a register.

[0008] According to at least one specific implementation of the embodiment of the present application, configuring the counting window through a register is specifically changing the maximum value and minimum value of the counting judgment window of the counting window through the configuration register to control the detection accuracy of the digital clock.

[0009] According to at least one specific implementation of the embodiments of the present application, registers are configured via the I2C bus to dynamically control the length of the counting window.

[0010] According to at least one specific implementation of the embodiments of the present application, during the detection of the digital clock, the clear signal and the flag signal in the analog clock domain are detected. If the clear signal is detected to be high, the flag signal is set to a high level and counting is started.

[0011] According to at least one specific implementation of the embodiments of the present application, when the clear signal and the flag signal are both high, it is detected whether the count value is within the expected range. If the count value is not within the expected range, a clock alarm signal is reported.

[0012] According to at least one specific implementation of the embodiments of the present application, in the process of judging whether the detection result is consistent with the preset range and outputting the corresponding judgment result, it includes: a first working condition: the analog clock is normal, the digital clock is normal, and the chip works normally; a second working condition: the analog clock is abnormal, the digital clock is normal or abnormal, and the chip enters a safe state; a third working condition: the analog clock is normal, the digital clock is abnormal, the detection count value is not within the expected range, and the chip enters a safe state; a fourth working condition: the analog clock is normal, the digital clock is necrotic, the detection count value is not within the expected range, and the chip enters a safe state.

[0013] According to another aspect of an embodiment of the present application, a PMIC digital clock anomaly detection device is provided for implementing the PMIC digital clock anomaly detection method, including: a digital frequency jittering control module, configured to generate a counting window; a cross-clock domain processing module, configured to perform cross-clock domain processing on a signal; a counter control module, configured to generate a clear signal and a flag signal in an analog clock domain; a counter module, configured to receive a clock monitoring enable signal in the analog clock domain, and control a counting comparison window module according to an output result of the counter control module; and a counting comparison window module, configured to receive an output result of the counter module, count in the counting window, and report or not report a clock alarm signal according to the counting result.

[0014] According to another aspect of the embodiments of the present application, a chip is provided, and when a program in the chip is executed by a processor, the method described above is implemented.

[0015] The PMIC digital clock anomaly detection method provided in the embodiment of the present application uses digital-analog collaboration to perform cross-clock domain collaborative detection on the analog clock ana_clk and the digital clock dig_clk, perform dynamic counting, determine the counting window and the error across the clock domain and perform corresponding processing, thereby achieving high-precision and low-cost clock monitoring.

[0016] The embodiment of the present application does not require the addition of redundant clocks. The only detection resources added to the digital part are a counter and a small amount of combinational logic. It has the advantages of simple structure and small footprint. It can accurately detect digital clock frequency anomalies and digital clock necrosis. It optimizes the error generated when the counting window crosses from the digital clock domain to the analog clock domain, and can flexibly configure the digital clock detection accuracy and the normal range of the digital clock through registers. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific implementation methods of the embodiments of the present application or the technical solutions in related technologies, the following will briefly introduce the drawings required for use in the specific implementation methods or related technical descriptions. Obviously, the drawings described below are only some implementation methods of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 This is a flowchart of a PMIC digital clock anomaly detection method according to an embodiment of the present application.

[0019] Figure 2 This is an architectural diagram of a PMIC digital clock anomaly detection system according to an embodiment of the present application.

[0020] Figure 3 This is a principle block diagram of the PMIC digital clock anomaly detection device according to an embodiment of the present application.

[0021] Figure 4 This is a timing diagram of the PMIC digital clock anomaly detection process in an embodiment of the present application.

[0022] Figure 5 It is a structural diagram of an electronic device. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the embodiments of the present application.

[0024] It should be noted that the terms "first", "second", etc. in the description and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present application described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0025] It should be noted that, in the absence of conflict, the implementation methods and features in the embodiments of the present application can be combined with each other. The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0026] like Figure 1 As shown, an embodiment of the present application provides a PMIC digital clock anomaly detection method, including:

[0027] Step S1: Provide a digital frequency jitter control module, which is configured to generate a counting window. In step S1, the digital frequency jitter control module is used to dynamically adjust the clock frequency. For example, by adjusting the clock frequency, it can optimize power conversion efficiency and reduce interference caused by fixed-frequency operation. Compared with the dual-clock source cross-check method in the related art, it can detect clock signal anomalies without significantly increasing chip area and power consumption, thereby improving the stability and reliability of the clock signal and avoiding the increase in power consumption and area caused by the dual-clock source method in the related art.

[0028] In step S2, the digital frequency jitter control module is processed across clock domains, a counting window is generated within the digital clock domain, and the counting window is extended across the clock domain to the analog clock domain to detect the digital clock. In step S2, the digital clock is periodically detected across clock domains, the counting window is extended across the clock domain to the analog clock domain, and the digital clock is detected by counting the number of analog clock cycles. Using technical means such as clear signals and flag bit detection, the count value is determined to be abnormal only when the detection flag and clear signal are both valid. This eliminates cross-clock domain errors, allows for timely detection and processing of digital clock anomalies, and improves the reliability and stability of the chip system operation.

[0029] Step S3: obtaining a detection result of the digital clock, determining whether the detection result is consistent with a preset range, and outputting a corresponding determination result.

[0030] Preferably, in step S1, the digital frequency jittering control module generates a flip signal, generates counting windows of different lengths according to the configuration of the frequency jittering mode, controls the counting window by configuring the corresponding register, changes the maximum and minimum values ​​of the counting window, and controls the detection accuracy of the digital clock. Exemplarily, in step S1, the counting window can be controlled by configuring the register, and the maximum and minimum values ​​of the counting window can be configured to control the detection accuracy of the digital clock, and the register can be configured through the I2C bus to dynamically control the length of the counting window.

[0031] Step S1 generates a flip signal through a digital frequency-jittering module and uses it to define a counting window. The parameters of the counting window are then dynamically adjusted by configuring the corresponding registers, thereby dynamically controlling the detection accuracy of the digital clock. Configuring the registers via the I2C bus further improves the flexibility and adaptability of setting the counting window parameters, allowing the registers to be adjusted according to actual needs during runtime. Step S1 improves the flexibility and detection accuracy of configuring the counting window, adapts to the functional safety requirements of the chip, simplifies hardware connections and communication, and enables more accurate diagnosis of chip safety issues by adjusting the counting window.

[0032] Preferably, in step S2, during the process of detecting the digital clock by crossing the clock domain to the analog clock domain, the corresponding clear signal cnt-clr and flag signal flag are detected. If the clear signal is detected to be high, the flag signal is set to a high level and counting begins. Exemplarily, when the clear signal cnt-clr and the flag signal flag are both high, it is detected whether the count value is within the expected range. If the count value is not within the expected range, a clock alarm signal is reported.

[0033] In the optimization technology provided in step S2, the digital clock is detected in the analog clock domain across clock domains. Real-time monitoring and anomaly detection of the digital clock signal are achieved by detecting the clear signal cnt-clr and the flag signal flag in the analog clock domain. The optimization technology provided in step S2 achieves synchronization and collaborative operation between the digital and analog clocks by detecting the clear signal and flag signal across clock domains. Cross-clock domain processing techniques ensure stable interaction and transmission of clock signals between different clock domains.

[0034] Preferably, in step S3, the process of determining whether the detection result is consistent with the preset range and outputting the corresponding determination result includes:

[0035] First working condition: analog clock is normal, digital clock is normal, and chip is working normally;

[0036] The second working condition: the analog clock is abnormal, the digital clock is normal or abnormal, and the chip enters the deepsafe security state;

[0037] The third working condition: The analog clock is normal, the digital clock is abnormal, the detection count value is not within the expected range, and the chip enters the deepsafe security state;

[0038] The fourth working condition: The analog clock is normal, the digital clock is faulty, the detection count value is not within the expected range, and the chip enters the deepsafe security state.

[0039] In the process of outputting the corresponding judgment result in step S3, by detecting the status of the analog clock and the digital clock and judging the working condition of the chip based on the detection results, real-time monitoring and safety management of the chip status are achieved. Step S3 ensures that the chip can enter the deepsafe security state under specific circumstances by defining different working conditions and outputting corresponding judgment results based on the detection results. Step S3 can detect the status of the digital clock across clock domains, evaluate the operating status of the chip, and further subdivide the working conditions of the digital clock, thereby improving the accuracy of fault diagnosis, timely discovering and responding to abnormal working conditions of the clock, and enabling the chip to enter the deepsafe security state when abnormal working conditions of the clock are detected. That is, by defining different working conditions and adopting corresponding measures for different types of clock anomalies, comprehensive clock detection, real-time fault response and exception handling are achieved, thereby improving the detection and processing capabilities of chip security.

[0040] In the above specific embodiments, any process or method description described in a flowchart or other manner can be understood as: a module, fragment or part of a code that represents one or more executable instructions for implementing a specific logical function or process step, and the scope of the preferred embodiment of the embodiment of the present application includes other implementations, which may not be in the order shown or discussed, including executing and implementing functions in a substantially simultaneous manner or in the opposite order according to the functions involved, or executing computer instructions and implementing corresponding functions according to program structures such as loops and branches, which can naturally be understood by those skilled in the art when implementing the embodiments of the present application.

[0041] like Figure 2 As shown, the embodiment of the present application also provides a PMIC digital clock anomaly detection system, including:

[0042] The counting window generating module is used to provide a digital frequency jittering control module, wherein the digital frequency jittering control module is configured to generate a counting window.

[0043] The cross-clock domain processing module performs cross-clock domain processing on the digital frequency jittering control module, generates a counting window in the digital clock domain, and detects the digital clock in the analog clock domain through the counting window.

[0044] The judgment result output module obtains the detection result of the digital clock, judges whether the detection result is consistent with the preset range, and outputs the corresponding judgment result.

[0045] The embodiments of the system described above are merely illustrative. For example, the various functional modules, units, or subsystems in the system may or may not be physically separate, or may or may not be physical units, that is, they may be located in the same place or distributed across multiple different systems and their subsystems or modules. Those skilled in the art may select some or all of the functional modules, units, or subsystems according to actual needs to achieve the purpose of the embodiments of the present application. For the above-mentioned situations, those of ordinary skill in the art can understand and implement them without inventive work.

[0046] like Figure 3 The PMIC digital clock anomaly detection device shown includes:

[0047] A digital frequency jittering control module is configured to generate a counting window;

[0048] A cross-clock domain processing module is configured to perform cross-clock domain processing on the signal;

[0049] A counter control module is configured to generate a clear signal and a flag signal in an analog clock domain;

[0050] a counter module configured to receive a clock monitoring enable signal in the analog clock domain and control the count comparison window module according to an output result of the counter control module;

[0051] The counting comparison window module is configured to receive the output result of the counter module, count in the counting window, and report or not report the clock alarm signal.

[0052] The PMIC digital clock anomaly detection device achieves high-precision, low-overhead clock monitoring through cross-clock domain collaborative detection of the analog clock ana_clk and the digital clock dig_clk, combined with a dynamic counting judgment window and cross-clock domain error processing. The counting window is generated by the digital frequency jitter control module and counts in the analog clock domain. The counting window can implement dynamic counting judgment functions, and the maximum and minimum values ​​of the counting window can be flexibly changed by configuring the corresponding registers. The counting window is delayed by one beat and an XOR operation is performed to generate the clear signal cnt_clr. When the flag signal flag and the clear signal cnt_clr are detected to be valid at the same time, the count value is verified to be within the expected range, reducing the error caused by the counting window when crossing clock domains and reducing the false alarm rate.

[0053] like Figure 4 The timing diagram shown in Figure 4 In the figure, DIG_CLK is the digital clock, ANA_CLK is the analog clock, FSS_TOGGLE_DIV2, FSS_TOGGLE_DIV2_SYNC, FSS_TOGGLE_DIV2_SYNC_1D are toggle signals, CNT_CLR is the clear signal, FLAG is the flag signal, and ERROR is the counting result signal.

[0054] The detection steps of the PMIC digital clock anomaly detection device are as follows:

[0055] Step 1: The flip signal generated by the digital frequency jitter control module is used as a counting window;

[0056] Step 2: The counting window crosses from the digital clock domain to the analog clock domain;

[0057] In step 3, the counting window in the analog clock domain is delayed by one beat and an XOR operation is performed to generate a clear signal (cnt_clr). The one-beat delay in step 3 refers to a delay of one clock cycle in the analog clock domain. XORing is an XOR operation used to compare the difference between two signals and output the XOR result, which can be used to detect signal changes or state transitions.

[0058] Generate a clear signal (cnt_clr). The clear operation ensures that the counter restarts counting after reaching the maximum value. Each counting cycle starts from zero. In cross-clock domain or cross-module operations, all modules are synchronized at the beginning of each counting cycle. The clear signal can restore the counter to its initial state to avoid error accumulation.

[0059] Step 4: After detecting that the clear signal (cnt_clr) is pulled high, the flag signal (flag) is pulled high and counting begins.

[0060] Step 5: When it is detected that the clear signal (cnt_clr) and the flag signal (flag) are both high, it is determined whether the count value is within the expected window. If the count value is not within the expected window, a clock alarm signal clk_err is reported.

[0061] During the above working process, clock anomalies usually include clock failure and clock frequency outside the expected range, including the following four working conditions:

[0062] Working condition 1: The analog clock and digital clock are normal: The counting window is generated periodically, the counting value is always within the expected range, the clock alarm signal clk_err is not reported, and the chip operates normally.

[0063] Working condition 2: Analog clock is abnormal, digital clock is normal or abnormal: The analog side detects that the chip output voltage is out of the set range, and the chip enters the deepsafe security state.

[0064] Working condition three: the analog clock is normal, but the digital clock is abnormal (the clock frequency is not within the expected range): the counting window is generated periodically, and the count value is not within the expected range (when the digital frequency is too low, the count value exceeds the expected range; when the digital frequency is too high, the count value is lower than the expected range). The clk_err signal is reported, and the chip enters the deepsafe security state.

[0065] Working condition 4: The analog clock is normal, but the digital clock is abnormal (clock failure): the counting window cannot be generated, the counting value exceeds the expected range, and clk_err is reported, and the chip enters the deepsafe security state.

[0066] Among the above four working conditions, deepsafe refers to the safe state of a chip in the functional safety chip. It refers to a state in which the chip reports an error and stops external output after an error occurs. By being activated when there are serious faults, abnormal conditions and unrecoverable errors, deepsafe can isolate the source of the fault, prevent the fault from spreading to other modules, ensure that the key functions of the chip are in a safe state, prevent further damage to the chip, and ensure that the chip operates within a safe range through hardware mechanisms.

[0067] like Figure 5 As shown, the embodiments of the present application provide a PMIC digital clock anomaly detection method and system, and also provide corresponding electronic devices and chips:

[0068] An electronic device includes: a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus; the memory stores a computer program, and when the computer program is executed by the processor, the processor performs the steps of a PMIC digital clock anomaly detection method.

[0069] A chip implements a PMIC digital clock anomaly detection method when a program in the chip is executed by a processor.

[0070] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 5 As shown, device 800 includes a processor 801, a memory 802, a communication interface 803, and a bus 804. The processor 801, memory 802, and communication interface 803 communicate via bus 804, and communication can also be achieved through other means such as wireless transmission. The memory 802 is used to store instructions, and the processor 801 is used to execute the instructions stored in the memory 802. The memory 802 stores program code 8021, and the processor 801 can call the program code 8021 stored in the memory 802 to execute the steps of the PMIC digital clock anomaly detection method.

[0071] It should be understood that in the embodiment of the present application, the processor 801 may be a CPU, or may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0072] The memory 802 may include a read-only memory (ROM) and a random access memory (RAM), and provides instructions and data to the processor 801. The memory 802 may also include a non-volatile random access memory. The memory 802 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM RAM (DR RAM). In addition to a data bus, bus 804 may also include a power bus, a control bus, and a status signal bus. However, for clarity, all buses are labeled as bus 804 in the figure.

[0073] Those skilled in the art will understand that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as those generally understood by those skilled in the art in the art to which the embodiments of the present application belong. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with their meanings in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless specifically defined.

[0074] It should be noted that certain terms are used in the description and claims of the embodiments of this application to refer to specific components. Those skilled in the art will understand that different manufacturers and suppliers may use different terms to refer to the same component. The description and claims of the embodiments of this application do not distinguish components based on differences in terms, but rather on differences in their functions.

[0075] In the description of the embodiments of the present application, reference to the terms "one embodiment," "example," "specific example," etc., means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any appropriate manner in any one or more embodiments or examples.

[0076] In addition, the technical solutions between the various implementation methods of the embodiments of the present application can be combined with each other, but it must be based on the fact that ordinary technicians in this field can implement it. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the embodiments of the present application.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, rather than to limit them. Although the embodiments of the present application have been described in detail with reference to the aforementioned specific implementation methods, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned specific implementation methods, or replace some or all of the technical features therein with equivalents, and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the specific implementation methods of the embodiments of the present application.

Claims

1. A PMIC digital clock anomaly detection method, characterized in that: include: A digital frequency jittering control module is provided, wherein the digital frequency jittering control module is configured to generate a counting window; Performing cross-clock domain processing on the digital frequency jitter control module, generating a counting window in the digital clock domain, and detecting the digital clock in the analog clock domain by crossing the clock domain with the counting window; Obtain a detection result of the digital clock, determine whether the detection result is consistent with a preset range, and output a corresponding determination result.

2. The PMIC digital clock anomaly detection method according to claim 1, characterized in that: The digital frequency jittering control module generates a flip signal and generates counting windows of different lengths according to different configurations of the frequency jittering mode.

3. The PMIC digital clock anomaly detection method according to claim 2, wherein: The counting window is configured via registers.

4. The PMIC digital clock anomaly detection method according to claim 3, wherein: Configuring the counting window through a register specifically involves changing the maximum value and the minimum value of the counting judgment window of the counting window through configuring the register, so as to control the detection accuracy of the digital clock.

5. The PMIC digital clock anomaly detection method according to claim 2, wherein: The registers are configured via the I2C bus to dynamically control the length of the counting window.

6. The PMIC digital clock anomaly detection method according to claim 1, wherein: In the process of detecting the digital clock, the clear signal and the flag signal in the analog clock domain are detected. If the clear signal is detected to be high level, the flag signal is set to high level and counting begins.

7. The PMIC digital clock anomaly detection method according to claim 6, characterized in that: When the clear signal and the flag signal are both high, it is detected whether the count value is within the expected range. If the count value is not within the expected range, a clock alarm signal is reported.

8. The PMIC digital clock anomaly detection method according to claim 1, wherein: The process of determining whether the detection result is consistent with the preset range and outputting the corresponding determination result includes: First working condition: analog clock is normal, digital clock is normal, and chip is working normally; The second working condition: the analog clock is abnormal, the digital clock is normal or abnormal, and the chip enters a safe state; The third working condition: the analog clock is normal, the digital clock is abnormal, the detection count value is not within the expected range, and the chip enters the safe state; The fourth working condition: the analog clock is normal, the digital clock is faulty, the detection count value is not within the expected range, and the chip enters a safe state.

9. A PMIC digital clock anomaly detection device, used to implement the PMIC digital clock anomaly detection method according to any one of claims 1 to 8, characterized in that: include: A digital frequency jittering control module is configured to generate a counting window; A cross-clock domain processing module is configured to perform cross-clock domain processing on the signal; A counter control module is configured to generate a clear signal and a flag signal in an analog clock domain; a counter module configured to receive a clock monitoring enable signal in the analog clock domain and control the count comparison window module according to an output result of the counter control module; The counting comparison window module is configured to receive the output result of the counter module, count in the counting window, and report or not report the clock alarm signal according to the counting result.

10. A chip, characterized in that: When the program in the chip is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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