Vertical cavity surface emitting laser

Abstract

The invention discloses a vertical cavity surface emitting laser. The vertical cavity surface emitting laser comprises a substrate, a plurality of arrays arranged on the substrate and a plurality of insulating grooves, the insulating grooves surround the array; each array comprises a plurality of light-emitting units and a plurality of oxidation grooves, each light-emitting unit comprises at least one oxidation limiting layer, and the oxidation grooves are arranged around at least one part of the periphery of the light-emitting units and expose the oxidation limiting layers; the array further comprises a plurality of insulation areas corresponding to at least part of the oxidation grooves. And the insulating regions are arranged around the side walls and the bottoms of the corresponding oxidation grooves. According to the embodiment of the invention, the breakdown risk of the oxidation groove can be reduced, and the reliability of the vertical-cavity surface-emitting laser is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of lasers, and in particular, to a vertical-cavity surface-emitting laser. Background Art

[0002] A vertical-cavity surface-emitting laser (VCSEL) refers to a semiconductor laser in which a resonant cavity is formed in the vertical direction of a substrate and laser light is emitted in the vertical direction. With the development of VCSEL technology, VCSEL lasers are widely used in fields such as intelligent transportation, health care, biological detection, and military security.

[0003] In the prior art, oxidation trenches are usually provided on the outer periphery of each light-emitting unit of a vertical-cavity surface-emitting laser to prepare an oxidation confinement layer, an oxidation aperture of the light-emitting unit is formed, and a passivation layer is provided to cover the surface of the oxidation trenches. However, due to surface defects of the passivation layer, uneven etching surfaces, or uneven metals, etc., leakage current is likely to occur at the oxidation trenches, and in severe cases, the passivation layer may be broken down, resulting in device failure. Therefore, the reliability of the existing vertical-cavity surface-emitting lasers is poor. Summary of the Invention

[0004] The present invention provides a vertical-cavity surface-emitting laser to reduce the breakdown risk of oxidation trenches and improve the reliability of the vertical-cavity surface-emitting laser.

[0005] An embodiment of the present invention provides a vertical-cavity surface-emitting laser, including:

[0006] A substrate;

[0007] A plurality of arrays provided on the substrate;

[0008] A plurality of insulating trenches surrounding the arrays;

[0009] Each of the arrays includes a plurality of light-emitting units and a plurality of oxidation trenches, the light-emitting unit includes at least one oxidation confinement layer, wherein the oxidation trenches are provided around at least a part of the outer periphery of the light-emitting unit and expose the oxidation confinement layer;

[0010] The array further includes: a plurality of insulating regions corresponding to at least some of the oxidation trenches; the insulating regions are provided around the side walls and bottoms of the corresponding oxidation trenches.

[0011] Optionally, the insulating region includes a side wall insulating region in contact with the side wall of the corresponding oxidation trench and a bottom insulating region in contact with the bottom of the corresponding oxidation trench;

[0012] Among them, the insulating region is prepared by an ion implantation method; the depth of the bottom insulating region is less than or equal to the depth of the sidewall insulating region; the depth of the sidewall insulating region is greater than the depth of the oxidation trench.

[0013] Optionally, the depth of the bottom insulating region is greater than 0.5 um.

[0014] Optionally, the sidewall of the oxidation trench is perpendicular to the bottom of the oxidation trench;

[0015] Or,

[0016] The cross-sectional shape of the oxidation trench is an inverted trapezoid or a trapezoid, and the angle range of the angle between the sidewall of the oxidation trench and the bottom of the oxidation trench is: 80 - 145 degrees.

[0017] Optionally, during the preparation of the insulating region, ion implantation is performed along a direction perpendicular to the bottom of the oxidation trench;

[0018] Or, during the preparation of the insulating region, ion implantation is performed along a direction at a preset angle to the direction perpendicular to the bottom of the oxidation trench.

[0019] Optionally, the light-emitting unit further includes a lower reflector, and the insulating trench exposes the lower reflector;

[0020] The oxidation trench is an annular trench provided around the outer periphery of the light-emitting unit; or, a plurality of spaced oxidation trenches are provided around the outer periphery of each light-emitting unit.

[0021] Optionally, in the same array, one oxidation trench is shared between two adjacent light-emitting units;

[0022] And / or,

[0023] One insulating trench is shared between two adjacent arrays.

[0024] Optionally, for the light-emitting units located at the peripheral positions in the array, the oxidation trench semi-surrounds the outer periphery of the light-emitting unit, and the insulating trench and the oxidation trench are jointly used to prepare the oxidation confinement layer to form the oxidation aperture of the light-emitting unit.

[0025] Optionally, the depth of the insulating trench is greater than the depth of the oxidation trench;

[0026] The width of the insulating trench is greater than the width of the oxidation trench.

[0027] Optionally, the light-emitting unit further includes an ohmic electrode, a passivation layer, a first electrode, and a second electrode, wherein the first electrode is connected to the ohmic electrode through a through hole formed in the passivation layer corresponding to the ohmic electrode;

[0028] The first electrode and the second electrode are configured to generate current and emit light in the light-emitting unit corresponding to the first electrode when connected to an external power supply.

[0029] Optionally, the second electrode is disposed below the substrate; a plurality of the arrays share the same second electrode;

[0030] In the same array, a plurality of the light-emitting units share the same first electrode.

[0031] The vertical cavity surface emitting laser provided by the embodiment of the present invention can isolate each array by providing insulating trenches, so that each array can be independently lit and controlled. Moreover, by providing oxidation trenches around the periphery of the light-emitting unit, it is beneficial to form an oxidation confinement layer in each light-emitting unit to limit the light-emitting aperture of the light-emitting unit. And, by forming a high-impedance insulating region that completely wraps the oxidation trenches around the oxidation trenches, it helps to isolate surface defects formed during processes such as oxidation and etching, reduce the leakage current of the device, and improve the breakdown voltage resistance of the device. Therefore, compared with the prior art, the embodiment of the present invention can reduce the breakdown risk of the oxidation trenches and improve the reliability of the vertical cavity surface emitting laser.

[0032] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0034] Figure 1 is a schematic structural diagram of a vertical cavity surface emitting laser provided by an embodiment of the present invention;

[0035] Figure 2 is along Figure 1 a cross-sectional structural diagram taken along A-A' in

[0036] Figure 3 is a schematic diagram of an ion implantation process provided by an embodiment of the present invention;

[0037] Figure 4 It is a schematic structural diagram of an ion implantation device provided by an embodiment of the present invention;

[0038] Figure 5 It is a schematic top view structural diagram of an ion implantation device provided by an embodiment of the present invention;

[0039] Figure 6 It is another schematic diagram of an ion implantation process provided by an embodiment of the present invention;

[0040] Figure 7 It is a schematic structural diagram of another ion implantation device provided by an embodiment of the present invention;

[0041] Figure 8 It is yet another schematic diagram of an ion implantation process provided by an embodiment of the present invention;

[0042] Figure 9 It is a schematic structural diagram of an oxidized trench provided by an embodiment of the present invention;

[0043] Figure 10 It is along Figure 1 Another schematic cross-sectional structural diagram of A - A' in Detailed implementation manners

[0044] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0045] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order different from those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion.

[0046] An embodiment of the present invention provides a vertical cavity surface emitting laser. Figure 1 It is a schematic structural diagram of a vertical cavity surface emitting laser provided by an embodiment of the present invention; Figure 2 It is along Figure 1 A schematic cross-sectional structural diagram of A - A' in Figure 1 and Figure 2, A vertical cavity surface emitting laser includes: a substrate 1000, a plurality of arrays 100 disposed on the substrate 1000, and a plurality of insulating trenches 200. Among them, the insulating trenches 200 surround the arrays 100. Each array 100 includes a plurality of light emitting units 10 and a plurality of oxidation trenches 20, and at least one oxidation confinement layer 11 is included in the light emitting unit 10 ( Figure 2 Two oxidation confinement layers 11 are exemplarily given in it). Among them, the oxidation trenches 20 are disposed around at least a part of the outer periphery of the light emitting unit 10 and expose the oxidation confinement layer 11. The array 100 further includes: a plurality of insulating regions 30 corresponding to at least some of the oxidation trenches 20; the insulating regions 30 are disposed around the side walls and the bottom of the corresponding oxidation trenches 20.

[0047] Exemplarily, a semiconductor epitaxial layer is grown on the substrate 1000. By fabricating a plurality of insulating trenches 200 on the semiconductor epitaxial layer, the semiconductor epitaxial layer can be separated into a plurality of arrays 100, and a plurality of light emitting units 10 can be regularly arranged in each array 100. Among them, the semiconductor epitaxial layer may include a lower mirror layer 12, an active layer 13, and an upper mirror layer 14 that are sequentially stacked from bottom to top; an ohmic metal layer 15 may also be disposed above the upper mirror layer 15. The insulating trenches 200 can be etched to a depth that exposes the lower mirror layer 12 to provide a plurality of arrays 100 that are isolated from each other on the active layer 13, so that each array 100 can emit light and be controlled independently. For each light emitting unit 10 in the array 1000, it may include a lower mirror 121 disposed in the lower mirror layer 12, an active region 131 disposed in the active layer 13, an upper mirror 141 disposed in the upper mirror layer 14, and an ohmic electrode 151 disposed in the ohmic metal layer 15. For any light emitting unit 10, in order to increase the current density and light emitting efficiency of the light emitting unit 10 when the same magnitude of operating voltage / current is applied, an oxidation confinement layer 11 can be disposed in the light emitting unit 10. The oxidation confinement layer 11 is a ring structure, and the light emitting aperture in the light emitting unit 10 can be defined by the oxidation aperture 111 in the oxidation confinement layer 11. Since the oxidation confinement layer 11 is a high impedance film layer, when the light emitting unit 10 is applied with an operating voltage / current, the current distribution in the light emitting unit 10 is laterally restricted by the oxidation confinement layer 11 and concentrated in the central region of the light emitting unit 10, so that laser is generated in the middle region of the active region of the light emitting unit 10. The oxidation confinement layer 11 can be formed, for example, in or above the active region. The specific number and formation position of the oxidation confinement layer 11 in the light emitting unit 10 can be selected according to requirements and are not limited here.

[0048] To facilitate the formation of the oxidation confinement layer 11 of each light-emitting unit 10, oxidation trenches 20 can be formed in each array 1000 around the outer periphery of each light-emitting unit 10. Among them, in the thickness direction Z of the vertical cavity surface emitting laser, the bottom of the oxidation trench 20 is lower than the bottom of the lowermost oxidation confinement layer 11, so as to facilitate the preparation of the oxidation confinement layer 11 of the corresponding light-emitting unit 10 through the oxidation trench 20. Exemplarily, if the lowermost oxidation confinement layer 11 is formed in the active layer 13, then the depth of the oxidation trench 20 is equal to or slightly lower than the bottom of the lowermost oxidation confinement layer 11. Therefore, the depth of the oxidation trench 20 is less than the depth h0 of the insulating trench 200, and compared with the insulating trench 200, the oxidation trench 20 is a shallow trench.

[0049] The surface of the oxidation trench 20 can be electrically isolated by a passivation layer (not shown in the figure). Since the lower mirrors between adjacent light-emitting units 10 are not cut off by the oxidation trench 20 and are actually still in a connected state, there is a lateral current transfer between adjacent light-emitting units 10. If too much current is transmitted towards the oxidation trench 20 and accumulates on the sidewalls of the oxidation trench 20, the passivation layer may be broken down, causing the light-emitting unit 10 to be directly exposed to the air and eroded by water vapor, which easily leads to device damage. Especially when there are surface defects in the passivation layer or the etched surface is uneven, the electrical isolation of the oxidation trench 20 is more likely to be damaged. In the embodiments of the present invention, by providing an insulating region 30 surrounding the oxidation trench 20, a high-resistance region is provided near the oxidation trench 20, so that the resistance values near the sidewalls and the bottom of the oxidation trench 20 become higher, forcing the current to be transmitted downward, reducing the lateral transmission of the current, and reducing the accumulation of charges near the oxidation trench 20, thereby providing a further passivation effect on the part of the oxidation trench 20 that is prone to breakdown and reducing the risk of leakage current occurring at the oxidation trench 20. Preferably, a corresponding insulating region 30 can be provided for each oxidation trench 20 to ensure the insulating protection effect on all oxidation trenches 20. Exemplarily, the insulating region 30 can be prepared by ion implantation. By ion implantation, the crystal structure of the material in the implanted region can be damaged, increasing the impedance of the implanted region and making it difficult for the current to penetrate through this region, ensuring the insulating effect near the oxidation trench 20. Among them, the insulating region 30 can be prepared before or after the formation of the passivation layer, and the specific preparation method and sequence are not limited here, as long as it is ensured that the insulating region 30 can cover the sidewalls and the bottom of the oxidation trench 20.

[0050] The vertical cavity surface emitting laser provided in the embodiment of the present invention can make each array 100 independently lit and controlled by setting an insulating groove 200 to isolate each array 100. In addition, the oxidation groove 20 is arranged around the periphery of the light-emitting unit 10, which is conducive to forming an oxidation restriction layer 11 in each light-emitting unit 10 to limit the light-emitting aperture of the light-emitting unit 10. In addition, by forming a high-impedance insulating region 30 around the oxidation groove 20 that completely wraps the oxidation groove 20, it is helpful to isolate surface defects formed during oxidation and etching, reduce the leakage current of the device, and improve the voltage resistance of the device. Therefore, compared with the prior art, the embodiment of the present invention can reduce the breakdown risk of the oxidation groove 20 and improve the reliability of the vertical cavity surface emitting laser.

[0051] Continue to see Figure 2 On the basis of the above embodiments, optionally, the insulating region 30 may specifically include a sidewall insulating region 31 in contact with the sidewall of the corresponding oxidation trench 20, and a bottom insulating region 32 in contact with the bottom of the corresponding oxidation trench 20. Specifically, the depth h1 of the sidewall insulating region 31 may be understood as the vertical distance from the top to the bottom of the sidewall insulating region 31, and the width of the sidewall insulating region 31 may be understood as the shortest distance between the two sidewalls of the sidewall insulating region 31 in the horizontal direction (i.e., the direction parallel to the upper surface of the substrate 1000 and perpendicular to the thickness direction Z), and the width and depth of the bottom insulating region 32 are similar. In the thickness direction Z, by setting the bottom of the sidewall insulation region 31 lower than the bottom of the oxidation trench 20, that is, setting the depth h1 of the sidewall insulation region 31 greater than the depth of the oxidation trench 20, it can be ensured that the sidewall insulation region 31 completely wraps the side wall of the oxidation trench 20. The sidewall insulation region 31 is connected to the bottom insulation region 32, so that the insulation region 30 can completely wrap the oxidation trench 20, reliably blocking the lateral current transfer near the oxidation trench 20, and achieving good protection of the oxidation trench 20.

[0052] Exemplarily, the width of the sidewall insulating region 31 is greater than or equal to 0.2 microns, preferably greater than 0.5 microns, to ensure that the high impedance region has sufficient thickness to reliably block leakage current. The vertical projection of the sidewall insulating region 31 on the substrate 1000 and the vertical projection of the ohmic electrode 151 on the substrate 1000 do not overlap or partially overlap, preferably do not overlap, so as to prevent the semiconductor material under the ohmic electrode 151 from being modified into a high impedance material as much as possible, so as to avoid affecting the normal electrical transmission process in the light-emitting unit 10. For example, when the cross-sectional shape of the sidewall insulating region 31 is as follows: Figure 2 When the bottom insulating region is a rectangle, the width of the sidewall insulating region 31 is the width of the rectangle, and the depth h1 of the sidewall insulating region 31 is the length of the rectangle. Exemplarily, the depth of the bottom insulating region is greater than 0.5 um.

[0053] Based on the above embodiments, optionally, the insulating region 30 can be prepared by ion implantation. The following is an exemplary description of the specific preparation process of the insulating region 30.

[0054] Figure 3 is a schematic diagram of an ion implantation process provided by an embodiment of the present invention. Figure 3 Exemplarily, the straight line with a solid arrow represents the bombardment direction of the ion beam. Refer to Figure 3 , in one embodiment, optionally, the ion implantation may specifically include the steps of depositing photoresist - patterning the photoresist - ion implantation; after the ion implantation is completed, the vertical cavity surface emitting laser can be cleaned for the next step.

[0055] Specifically, in the step of depositing photoresist, the photoresist layer 40 can be deposited on the upper surface of the semiconductor epitaxial layer, and the photoresist layer 40 covers the upper surface of the upper mirror layer 14 and the ohmic metal layer.

[0056] In the photoresist patterning step, by patterning the photoresist layer 40, the photoresist layer 40 is removed to expose a part of the semiconductor epitaxial layer, which can form an ion implantation pattern. The remaining photoresist layer 40 can protect the non - ion - implanted area (i.e., the area other than the target implantation area) from the influence of the ion implantation process by covering it. This step can be specifically realized by processes such as exposing and developing the photoresist layer 40. The vertical projection of the ion implantation pattern on the substrate 1000 covers and is larger than the vertical projection of the oxidation trench 20 on the substrate 1000, so that the insulating region 30 formed after ion implantation can include the side - wall insulating region 31 surrounding the side wall of the oxidation trench 20. The ion implantation pattern can be used to define the range of ion implantation, and the size of the side - wall insulating region 31 is related to the range of the ion implantation pattern outside the oxidation trench 20. Exemplarily, it can be set that the vertical projection of the ion implantation pattern and the ohmic electrode 151 on the substrate 1000 have no overlap to reduce or avoid the diffusion of implanted ions to the lower part of the ohmic electrode 151, so as to prevent the semiconductor under the ohmic electrode 151 from being modified.

[0057] In the ion implantation step, corresponding to the ion implantation pattern, ion implantation is performed on the semiconductor epitaxial layer to form a plurality of insulating regions 30. Among them, the type of ions required for ion implantation, the implantation energy magnitude, and the dose can all be selected according to the depth of the side - wall insulating region 31 and the film layer material to be penetrated.

[0058] Based on the above embodiments, optionally, according to different specific ion implantation processes, in the finally obtained insulating region 30, the depth h2 of the bottom insulating region 32 can be less than or equal to the depth h1 of the side - wall insulating region 31. The following is a specific description of several possible preparation methods.

[0059] See Figure 3 , in one embodiment, optionally, the sidewall of the oxidation trench 20 is perpendicular to the bottom of the oxidation trench 20. During the preparation of the insulation region 30, ion implantation can be performed in a direction perpendicular to the bottom of the oxidation trench 20 (i.e., the thickness direction Z). In this implantation method, the ion implantation of the sidewall insulation region 31 and the bottom insulation region 32 is carried out simultaneously along the thickness direction Z. Therefore, the depths of the sidewall insulation region 31 and the bottom insulation region 32 are the same.

[0060] Then, as Figure 3 shown, in this case, the depth required for ion implantation is equal to the depth h1 of the sidewall insulation region 31. Under this condition, when the implantation depth is relatively deep, multiple implantation energies and / or multiple implanted ions can be used as needed to perform ion implantation on the semiconductor epitaxial layer along the thickness direction Z, and the target implantation depth is achieved through the superposition of multiple implantation processes. Among them, the implanted ions can be H+, B+, etc., and different energies and doses cover different implantation depths.

[0061] Furthermore, in this method, the thickness of the photoresist layer 40 can be set to be sufficient to resist the ion implantation process, so that all ions outside the ion implantation pattern enter the photoresist and do not penetrate through the photoresist layer 40 and be implanted into the functional film layer of the light-emitting unit 10, ensuring that the film layer in the non-implanted area is not modified by ion bombardment. Among them, the thickness h1 of the photoresist layer 40 can be specifically set according to the target implantation depth and the blocking ability of the photoresist material to ion implantation.

[0062] Among them, the device for performing ion implantation can be seen in Figure 4 and Figure 5 , specifically, the ion implantation device can include: a carrier stage 500 and an ion emitter (not shown in the figure). Among them, the carrier stage 500 includes a plurality of carrier positions (for example, grooves) for placing the wafer 50. The surface of the wafer 50 is parallel to the surface of the carrier stage 500; a plurality of vertical cavity surface emitting lasers can be arranged in an array in the wafer 50. The ion emitter is used to generate an ion beam. Exemplarily, the ion beam emitted from the ion emitter can cover one carrier position, that is, cover one wafer 50. In the figure, exemplarily, the wafer 50 at the carrier position covered by the ion beam is represented by shaded filling, and the wafer 50 at the carrier position not covered by the ion beam is represented by pure white filling. The angle between the ion beam and the normal of the surface of the carrier stage 500 can correspond to the angle between the ion implantation direction and the thickness direction Z. As Figure 3 shown, the ion beam is perpendicular to the surface of the carrier stage 500, that is, the ion beam is incident along a direction perpendicular to the bottom of the oxidation trench 20.

[0063] During the ion implantation process, the carrier stage 500 can be controlled to rotate at a preset speed so that each wafer 50 can receive ion implantation for a sufficient time. Also, when there are multiple sets of carrier positions on the carrier stage 500, the carrier stage 500 can also be moved left and right or back and forth in the horizontal direction during rotation, so that the wafers 50 at various positions on the entire carrier stage 500 have the same implantation state and implantation dose. Among them, the preset speed can be set according to actual requirements, such as according to parameters such as the implantation dose. The preset speed is, for example, 1200 rpm; the difference in the implantation dose of the wafers 50 at different positions is controlled within an allowable range, for example, the difference < 1%.

[0064] According to the above analysis, Figure 3 In the trench structure and implantation method shown, when the depth of the oxidation trench 20 is relatively deep, multiple implantation energies and / or multiple implantation ions may be required for implantation. To simplify the preparation steps, the inventor has improved the ion implantation process, and several improvement methods are exemplarily described below.

[0065] Figure 6 is another schematic diagram of the ion implantation process provided by an embodiment of the present invention. Refer to Figure 6 , in another embodiment, optionally, the sidewall of the oxidation trench 20 is still perpendicular to its bottom. By adjusting the implantation direction of the ion implantation, on the basis of providing a sufficient width of the sidewall insulation region 31, the implantation depth can be reduced, so that the preparation of the insulation region 30 can be achieved by using one implantation energy and one implantation ion.

[0066] Specifically, ion implantation can be performed along a direction that forms a preset angle α with the direction perpendicular to the bottom of the oxidation trench (i.e., the thickness direction Z). Then, the target implantation depth is converted into the depth of the sidewall insulation region 31 in the ion implantation direction, and the width of the sidewall insulation region 31 is the ion implantation depth * sinα. This method can greatly reduce the implantation depth. Correspondingly, the depth of the bottom insulation region is the ion implantation depth * cosα. Therefore, in this case, the depth of the sidewall insulation region 31 is greater than the depth of the bottom insulation region 32. Exemplarily, the depth of the bottom insulation region 32 can be set to be greater than or equal to 1 micron. It should be noted that in the insulation region 30 formed by this method, there may be a part that protrudes compared to the target width near the top of the sidewall insulation region 31. This part is not included in the width of the sidewall insulation region 31, and the width of the sidewall insulation region 31 is still based on the width of the main part of the sidewall insulation region 31, or the minimum width of the sidewall insulation region 31 is used as its width.

[0067] In the case of inclined implantation, the configuration of the ion implantation device can be referred to Figure 7, specifically, the ion beam emitted by the ion generator forms a certain angle with the normal direction of the surface of the carrier stage 500, and this angle is equal to the preset included angle. Since it is not easy to adjust the angle of the ion beam emitted by the ion generator, in practical applications, the emission direction of the ion beam can be set to be unchanged, and the preset included angle can be adjusted by adjusting the inclination angle between the carrier stage 500 and the horizontal plane.

[0068] It should be noted that in this inclined ion implantation method, the wafer 50 itself can also rotate, for example, rotate in a plane parallel to the surface of the carrier stage 500, that is, rotate around an axis perpendicular to the surface of the wafer 50. For each wafer 50, during the ion implantation process, the wafer 50 itself can be controlled to rotate continuously so that the ion implantation range can cover all positions of the insulating region 30, avoiding the situation where there are unimplanted shielding dead corners. Or, for each wafer 50, the wafer 50 can be controlled to rotate discretely. Before the first rotation and after each rotation, the ion generator uses the same implantation energy and the same implanted ions to implant the wafer 50 in the same direction.

[0069] Among them, since the ion beam generated by the ion generator bombards the oxidation trench 20 in a direction forming a preset included angle α with the thickness direction Z, and the ion generator itself cannot extend into the oxidation trench 20, the range of each ion implantation only corresponds to a partial area of the insulating region 30. Therefore, by rotating the wafer 50 to adjust the ion beam bombardment position, the ion implantation range can completely cover all areas of the insulating region 30, ensuring that each position of the oxidation trench 20 can receive ion bombardment, thereby forming a uniform and complete insulating region 30.

[0070] On the basis of the above embodiments, optionally, during the ion implantation process, the wafer can be rotated n times so that the ion implantation range covers the entire insulating region 30. Among them, n is a positive integer, and can be specifically set according to actual needs, such as according to the implantation uniformity and process time requirements. For example, n is 1, 2, 3, or 4. Exemplarily, each rotation can adopt the same or different rotation angles as needed. Preferably, each rotation angle is the same, then each rotation angle is 360 / (n + 1) degrees.

[0071] Figure 8 is another schematic diagram of the ion implantation process provided by the embodiment of the present invention. The following combines Figure 8 , taking 3 rotations, each rotation of 90 degrees as an example, to specifically illustrate the ion implantation process. Refer to Figure 8, for example, the solid arrow indicates the direction of ion beam incidence, the large disk refers to the wafer 50, and the small circle can be understood as the ion implantation area corresponding to an oxidation groove. For the sake of convenience of explanation, only one small circle is shown here. It should be noted that the size shown here does not represent the actual size ratio of the wafer and the groove. Figure 6 and Figure 8 Due to the blocking effect of the sidewall of the oxidation trench 20 and the photoresist layer 40, when the ion beam is tilted for implantation, although the ion implantation range covers the entire wafer 50, Figure 6 , the right side wall of the oxidation trench 20 will be blocked, and the blocked area will not be bombarded by the ion beam. Figure 8 As shown in , before the first rotation, the shielded area cannot be ion-implanted, and after each rotation, the portion that was shielded before the first rotation is gradually exposed in the ion implantation area. Specifically, taking area B1 as an example, before the first rotation, area B1 is located in the shielded area and is not covered by the range of the first ion implantation. However, area B1 rotates with the rotation of wafer 50. For example, after the first rotation, the shielded area covers area B2; after the second rotation, the shielded area covers area B3; after the third rotation, the shielded area covers area B4. It can be seen that after two rotations, area B1 has become as follows relative to the ion beam. Figure 6 The left side wall portion of the oxidation groove 20 is not blocked and can be fully covered by the ion beam. That is to say, after rotating twice and performing ion implantation, the range of ion implantation has completely covered the area B1. That is, through the rotation of the wafer 50, the ion implantation of the area B1 is completed. Similarly, the side walls of the oxidation groove 20, front and back, left and right, can all be completely ion implanted. It can be seen that by rotating the wafer 50 multiple times for ion implantation, the range of ion implantation can cover the entire area of ​​the insulating area 30.

[0072] Figure 7 In the example, a plurality of wafers 50 are provided on the carrier 500, and the wafer 50 can rotate on a plane parallel to the surface of the carrier 500, but this is not intended to limit the present invention. In other embodiments, the carrier 500 can also be provided with only one carrying position to carry a wafer 50, so that the wafer 50 itself can move in six directions: x, y, z, yaw, pitch, and roll. Under the condition of keeping the ion beam emission direction unchanged, the adjustment of the position and rotation mode of the wafer 50 can be made more flexible and controllable.

[0073] Based on the above embodiments, optionally, the angular range of the preset angle α is: 1 - 20 degrees, preferably 5 - 11 degrees, for example 7 degrees. Specifically, the preset angle α can be set according to the target width and target depth of the sidewall insulation region 31 and the depth of the oxidation trench 20. Exemplarily, the upper limit value of the preset angle α is the smaller of angle one and angle two to avoid the defect that the bottom insulation region 32 cannot be completely formed. Wherein, angle one is the included angle between the line connecting the vertex of the sidewall of the oxidation trench 20 and the center position of the bottom of the oxidation trench 20 and the sidewall of the oxidation trench 20; angle two is the included angle between the line connecting the vertex of the inner wall of the photoresist layer 40 close to the oxidation trench 20 and the center position of the bottom of the oxidation trench 20 and the inner wall of the photoresist layer 40 close to the oxidation trench 20.

[0074] Figure 9 is a schematic structural diagram of an oxidation trench provided by an embodiment of the present invention. Refer to Figure 9 , in another embodiment, the implantation depth can be reduced by adjusting the shape of the oxidation trench 20. In this way, under the condition of vertical implantation, an implantation energy and an implanted ion can also be used to prepare the insulation region 30, so as to simplify the preparation process.

[0075] Specifically, the cross-sectional shape of the oxidation trench 20 is an inverted trapezoid or a trapezoid, and the angular range of the included angle δ between the sidewall of the oxidation trench 20 and the bottom of the oxidation trench 20 is: 80 - 145 degrees. Figure 9 Exemplarily, the cross-sectional shape of the oxidation trench 20 is an inverted trapezoid, so that the opening width (or area) at the top of the oxidation trench 20 is greater than the opening width (or area) at the bottom of the oxidation trench 20. The included angle δ between the sidewall and the bottom of the oxidation trench 20 is an obtuse angle, and its angular range is, for example: 93 - 145 degrees, preferably 95 - 135 degrees, for example 120 degrees. Then, when ion implantation is performed on the semiconductor epitaxial layer in the thickness direction Z, the implantation depth is adjusted to the distance between the sidewall of the oxidation trench 20 and the outer boundary of the sidewall insulation region 31 in the thickness direction Z, and this implantation depth is also less than the depth when the sidewall is vertical and the implantation is vertical.

[0076] In another embodiment, for the Figure 9 inverted trapezoid oxidation trench 20, optionally, an inclined ion implantation method can also be adopted, so that under the condition of the same implantation energy and the same implanted ion for implantation, the width of the sidewall insulation region 31 can be effectively increased; or in other words, on the basis of ensuring the same width w of the sidewall insulation region 31, the selection range of the types and energies of implanted ions can be expanded.

[0077] Based on the above embodiments, optionally, in the case of performing vertical ion implantation, the wafer 50 can also be controlled to rotate to eliminate the influence caused by the non-vertical cross-section of the photoresist layer 40 blocking the ion implantation process; and eliminate the influence caused by the non-perpendicular incidence of the ion beam.

[0078] Figure 10 is along Figure 1 Another cross-sectional structure schematic diagram of A-A' in. Refer to Figure 10 , based on the above embodiments, optionally, the vertical cavity surface emitting laser further includes: a passivation layer 16 formed above the semiconductor epitaxial layer, and the passivation layer 16 covers the upper surfaces of all exposed parts of the semiconductor epitaxial layer and the ohmic metal layer 15, for example, covers the upper surface of the upper mirror layer 40, the upper surface of the ohmic metal layer 50, the surface of the insulating trench 200, and the surface of the oxidation trench 20.

[0079] In addition, the light emitting unit 10 further includes: a first electrode 17 and a second electrode 18. Among them, the first electrode 17 is connected to the ohmic electrode 151 through a through hole corresponding to the ohmic electrode 151 provided in the passivation layer 16. The first electrode 17 and the second electrode 18 are used to generate current and emit light in the light emitting unit 10 corresponding to the first electrode 17 when connected to an external power supply, for example, when an operating voltage / current is applied.

[0080] Exemplarily, the first electrode 17 is disposed above the passivation layer 16, and the second electrode 18 is disposed below the substrate 1000. Alternatively, when the substrate 1000 is an insulating substrate, the second electrode 18 and the first electrode 17 can both be located on the same side of the substrate 1000 to form a VCSEL device with coplanar first and second electrodes. The present application is not limited to the setting position of the second electrode 18, which depends on the specific design.

[0081] Based on the above embodiments, optionally, multiple arrays 100 share the same second electrode 18. For example, all arrays 100 in the vertical cavity surface emitting laser share the same second electrode 18, and the second electrode 18 can be disposed on the entire surface below the substrate 1000. In addition, in the same array 100, multiple light emitting units 10 can share the same first electrode 17. For example, all light emitting units 10 in the same array 100 can share the same first electrode 17, so that all light emitting units 10 in the same array 100 emit light with the same brightness.

[0082] Continue to refer to Figure 1, based on the above embodiments, optionally, the insulating trench 200 is an annular trench surrounding the array 100. Preferably, one insulating trench 200 can be shared between two adjacent arrays 100, that is, there is partial overlap between the insulating trenches 200 on the outer peripheries of two adjacent arrays 100, so as to increase the density of the light-emitting units 10 per unit area and improve the unit power density of the VCSEL. Among them, the insulating trench 200 should at least penetrate through the active layer 13 to expose the lower mirror layer 12, and even can be etched to the substrate 1000 if necessary.

[0083] Continue to refer to Figure 1 , in one embodiment, optionally, for the light-emitting unit 10 located at the peripheral position (or edge position) in the array 100, the oxidation trench 20 can be set to semi-surround the outer periphery of the light-emitting unit 10. For the light-emitting unit 10 located at the peripheral position in the array 100, the insulating trench 200 has already exposed a partial position of its outer periphery. Combining with the oxidation trench 20 arranged around the unexposed position of the light-emitting unit 10, an exposed area surrounding the entire outer periphery of the light-emitting unit 10 can be formed, allowing sufficient water vapor to enter the semiconductor epitaxial layer for oxidation operation to prepare the oxidation confinement layer 11. Therefore, for the light-emitting unit 10 at the periphery of the array 100, the insulating trench 200 and the oxidation trench 20 on its outer periphery are jointly used to prepare the oxidation confinement layer 11 inside it to form the oxidation aperture 111 of the light-emitting unit 10. For the light-emitting unit 10 at the internal position of the array 100, an entire circle of oxidation trench 20 surrounding the light-emitting unit 10 needs to be set to prepare a uniform and complete oxidation confinement layer 11.

[0084] Among them, since the oxidation trench 20 only needs to provide the exposed surface required for the oxidation process, and there is an insulating region 30 arranged outside the oxidation trench 20 for insulation protection, the width w1 of the oxidation trench 20 does not need to be too large. And the insulating trench 200 is used to achieve isolation between adjacent arrays 100. Therefore, the width w0 of the insulating trench 200 is set to be larger, so that the insulating trench 200 itself provides a better isolation effect and is not easily broken down, reducing the leakage current between adjacent arrays 100. Then, in the device structure, the width w0 of the insulating trench 200 is greater than the width w1 of the oxidation trench 20.

[0085] In one embodiment, optionally, the oxidation trench 20 can be an annular oxidation trench surrounding the outer periphery of the light-emitting unit 10 to prepare a uniform and complete oxidation confinement layer 11.

[0086] In another embodiment, as Figure 1 shown, optionally, multiple spaced-apart oxidation trenches 20 can surround the outer periphery of each light-emitting unit 10 to increase the area ratio of the light-emitting units 10 per unit area and improve the unit power density of the VCSEL.

[0087] Furthermore, asFigure 1 As shown, in the same array 100, it is possible to arrange for two adjacent light-emitting units 10 to share an oxidation trench 20, so as to increase the density of the light-emitting units 10 and further improve the unit power density of the VCSEL.

[0088] Exemplarily, for each film layer of the vertical-cavity surface-emitting laser, the substrate 1000 can be a conductive substrate, a semi-insulating substrate, or an insulating substrate, depending on the specific design. The lower mirror layer 12 can be an N-type Distributed Bragg Reflector (N-DBR), and N-type doped Al x Ga 1-x As (x = 1 to 0) / GaAs material can be used for preparation. The active layer 13 can include quantum wells. The upper mirror layer 14 can be a P-type Distributed Bragg Reflector (P-DBR), and specifically, P-type doped Al x Ga 1-x As (x = 1 to 0) / GaAs material can be used for preparation. The ohmic metal layer 15 can be prepared using a conductive material such as metal. Further, an ohmic contact layer (not shown in the figure) can also be included between the ohmic metal layer 15 and the upper mirror layer 14 to reduce the ohmic contact resistance between the metal and the semiconductor. The passivation layer 16 can include materials such as silicon nitride and / or silicon oxide. Both the first electrode 17 and the second electrode 18 can be prepared using a conductive material such as metal.

[0089] In summary, in the vertical-cavity surface-emitting laser provided by the embodiment of the present invention, the insulation trench 200 can provide isolation between the arrays 100 to prevent the leakage between the arrays 100 from reducing the light-emitting efficiency. At the same time, the insulation trench 200 can provide a water vapor path for the oxidation of some of the light-emitting units 10. The oxidation trench 20 inside the array 100 only provides a water vapor path for the oxidation of the light-emitting units 10, and the area of the oxidation trench 20 can be as small as possible, as long as it can ensure the formation of the annular oxidation confinement layer 11. Therefore, the oxidation trench 20 is essentially a shallow trench, which helps to implement the ion implantation process, and can make the insulating region 30 formed by ion implantation completely cover the side walls and the bottom of the oxidation trench 20, providing a good insulation effect and avoiding device failure due to the breakdown of the oxidation trench 20. In other words, since the insulation protection at the oxidation trench 20 is provided by the additionally provided insulating region 30, the setting of the oxidation trench 20 only needs to consider the preparation requirements of the oxidation confinement layer 11, and less consideration needs to be given to the insulation performance of the oxidation trench 20 itself. Thus, the oxidation trench 20 can be set smaller, which is beneficial to improving the unit power density of the VCSEL.

[0090] It should be noted that the top - view cross - sectional shapes shown in the drawings of the embodiments of the present invention do not limit the present invention. The top - view cross - sectional shapes of the array 100 and the light - emitting unit 10 can be circular, polygonal, or any required shape; the top - view cross - sectional shape of the discrete oxidation trench 20 can be rectangular, other polygonal, or any required shape.

[0091] It should be understood that various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitations are imposed herein.

[0092] The above - mentioned specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub - combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A vertical cavity surface emitting laser, characterized in that, comprising: a substrate; a plurality of arrays disposed on the substrate; a plurality of insulating grooves surrounding the arrays; each of the arrays includes a plurality of light emitting units and a plurality of oxidation grooves, the light emitting unit includes at least one oxidation confinement layer, wherein the oxidation groove is disposed around at least a part of the outer periphery of the light emitting unit and exposes the oxidation confinement layer; the array further includes: a plurality of insulating regions corresponding to at least a part of the oxidation grooves; the insulating regions are disposed around the side walls and the bottom of the corresponding oxidation grooves.

2. The vertical cavity surface emitting laser according to claim 1, characterized in that, the insulating region includes a side wall insulating region in contact with the side wall of the corresponding oxidation groove, and a bottom insulating region in contact with the bottom of the corresponding oxidation groove; wherein, the insulating region is prepared by ion implantation; the depth of the bottom insulating region is less than or equal to the depth of the side wall insulating region; the depth of the side wall insulating region is greater than the depth of the oxidation groove.

3. The vertical cavity surface emitting laser according to claim 2, characterized in that, the depth of the bottom insulating region is greater than 0.5um.

4. The vertical cavity surface emitting laser according to claim 2, characterized in that, the side wall of the oxidation groove is perpendicular to the bottom of the oxidation groove; or, the cross-sectional shape of the oxidation groove is an inverted trapezoid or a trapezoid, and the angle range of the angle between the side wall of the oxidation groove and the bottom of the oxidation groove is: 80 - 145 degrees.

5. The vertical cavity surface emitting laser according to claim 4, characterized in that, during the preparation of the insulating region, ion implantation is performed along a direction perpendicular to the bottom of the oxidation groove; or, during the preparation of the insulating region, ion implantation is performed along a direction at a preset angle to the direction perpendicular to the bottom of the oxidation groove.

6. The vertical cavity surface emitting laser according to claim 1, characterized in that, the light emitting unit further includes a lower mirror, and the insulating groove exposes the lower mirror; the oxidation groove is an annular groove disposed around the outer periphery of the light emitting unit; or, a plurality of spaced oxidation grooves surround the outer periphery of each light emitting unit.

7. The vertical cavity surface emitting laser according to claim 6, characterized in that, in the same array, one oxidation groove is shared between two adjacent light emitting units; and / or, one insulating groove is shared between two adjacent arrays.

8. The vertical cavity surface emitting laser according to claim 6, characterized in that, for the light emitting units located at the peripheral position in the array, the oxidation groove semi - surrounds the outer periphery of the light emitting unit, and the insulating groove and the oxidation groove are jointly used to prepare the oxidation confinement layer to form the oxidation aperture of the light emitting unit.

9. The vertical cavity surface emitting laser according to any one of claims 1 - 8, characterized in that, the depth of the insulating groove is greater than the depth of the oxidation groove; the width of the insulating groove is greater than the width of the oxidation groove.

10. The vertical cavity surface emitting laser according to claim 1, wherein, the light emitting unit further includes an ohmic electrode, a passivation layer, a first electrode and a second electrode, wherein the first electrode is connected to the ohmic electrode through a through hole formed in the passivation layer corresponding to the ohmic electrode; the first electrode and the second electrode are configured to generate current and emit light in the light emitting unit corresponding to the first electrode when connected to an external power supply.

11. The vertical cavity surface emitting laser according to claim 10, wherein, the second electrode is disposed below the substrate; a plurality of the arrays share the same second electrode; in the same array, a plurality of the light emitting units share the same first electrode.

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