Signal generation circuit and signal generation device

Abstract

The invention discloses a signal generation circuit and a signal generation device, and relates to the field of circuits, the signal generation circuit comprises a plurality of signal generation units, for any signal generation unit, the duty ratio of an input signal can be adjusted according to a reference signal accessed by the signal generation unit, and then the signal with the adjusted duty ratio is output as an output signal; meanwhile, the output end of the previous signal generation unit is connected with the input end of the next signal generation unit, and an output signal output by the previous signal generation unit is used as an input signal of the next signal generation unit, so that the signal generation unit can generate a signal on the basis of the output signal of the previous signal generation unit; and further adjusting the duty ratio of the initial input signal and then outputting the initial input signal. Therefore, the output signals with different duty ratios are generated by the plurality of signal generation units, and a plurality of output signals with adjustable duty ratios and different output widths can be realized by selecting and setting different output nodes.

Description

Technical Field

[0001] The present invention relates to the field of circuits, and particularly to a signal generation circuit and a signal generation device. Background Art

[0002] With the continuous development of power electronics technology, circuits are also applied in a variety of different application scenarios to achieve various different functions. In some special cases, output signals with different duty cycles are required to meet different control requirements or different circuit functions, or to filter out glitch signals of a certain width by adjusting the duty cycle. Therefore, how to implement a circuit that can output output signals with different widths has become a technical problem that urgently needs to be solved at present. Summary of the Invention

[0003] The object of the present invention is to provide a signal generation circuit and a signal generation device. The signal generation unit can further adjust the duty cycle of the initial input signal based on the output signal of the previous signal generation unit and then output it. By using multiple signal generation units to generate output signals with different duty cycles and selecting different output nodes, multiple output signals with adjustable duty cycles and different output widths can be achieved.

[0004] To solve the above technical problem, the present invention provides a signal generation circuit, including:

[0005] N signal generation units, the N signal generation units are connected in series, and the output end of the previous signal generation unit is connected to the input end of the next signal generation unit; wherein, the input end of the first signal generation unit receives the initial input signal, and the output end of any one of the signal generation units is used as the output end of the signal generation circuit; N is a natural number not less than 1;

[0006] The signal generation unit is used to adjust the duty cycle of the initial input signal based on the reference signal received by itself to generate an output signal with a preset duty cycle.

[0007] Optionally, for any one of the signal generation units, the first reference terminal of the signal generation unit receives a first reference clock signal, and the second reference terminal receives a second reference clock signal, and the first reference clock signal and the second reference clock signal are opposite; the periods of the first reference clock signal and the second reference clock signal are both less than the period of the initial input signal;

[0008] The signal generation unit is specifically used to control the level inversion of the input signal received based on the signal edges of the first reference clock signal and the second reference clock signal to adjust the duty cycle of the initial input signal.

[0009] Optionally, it further includes:

[0010] A reference clock signal generation module, the input end of the reference clock signal generation module is connected to a preset clock signal, the first output end of the reference clock signal generation module is respectively connected to the first reference ends of each of the signal generation units, and the second output end of the reference clock signal generation module is respectively connected to the second reference ends of each of the signal generation units, for generating a first reference clock signal and a second reference clock signal.

[0011] Optionally, the reference clock signal generation module includes:

[0012] A first inverter, the input end of the first inverter is connected to a preset clock signal and serves as the first output end of the reference clock signal generation module, and the output end of the first inverter serves as the second output end of the reference clock signal generation module.

[0013] Optionally, the signal generation unit includes:

[0014] A signal inversion control module, the input end of the signal inversion control module is connected to a corresponding input signal, the first reference end of the signal inversion control module is connected to a first reference clock signal, the second reference end of the signal inversion control module is connected to a second reference clock signal, the signal inversion control module is used to detect a preset signal edge of the first reference clock signal and the second reference clock signal, and control the first output sub-signal to flip to the level of the input signal according to the detection result of the first reference clock signal and the level of the input signal connected, and control the second output sub-signal to flip to the level of the input signal according to the detection result of the second reference clock signal and the level of the input signal connected; wherein, the level of the input signal includes a first level and a second level, the states of the first level and the second level are opposite, the first output end of the signal inversion control module outputs the first output sub-signal, and the second output end outputs the second output sub-signal;

[0015] A signal processing module, the first input end of the signal processing module is connected to the first output end of the signal inversion control module, the second input end of the signal processing module is connected to the second output end of the signal inversion control module, the signal processing module is used to determine the time period when both the first output sub-signal and the second output sub-signal are at the first level, and use the time period as the first level duration of the output signal to generate the output signal with the preset duty cycle.

[0016] Optionally, the preset signal edge is a rising edge, and the signal inversion control module includes:

[0017] A first flip-flop, the input terminal of the first flip-flop being the input terminal of the signal inversion control module, the signal terminal of the first flip-flop being the first reference terminal of the signal inversion control module, the first flip-flop being configured to control the first output sub-signal to flip to a first level when the rising edge of the first reference clock signal is detected and the input signal connected is at a first level, and to control the first output sub-signal to flip to a second level when the rising edge of the first reference clock signal is detected and the input signal connected is at a second level;

[0018] A second flip-flop, the input terminal of the second flip-flop being connected to the input terminal of the first flip-flop, the signal terminal of the second flip-flop being the second reference terminal of the signal inversion control module, the second flip-flop being configured to control the second output sub-signal to flip to a first level when the rising edge of the second reference clock signal is detected and the input signal connected is at a first level, and to control the second output sub-signal to flip to a second level when the rising edge of the second reference clock signal is detected and the input signal connected is at a second level.

[0019] Optionally, the signal processing module is a logic gate circuit, and the logic gate circuit is configured to output the logical operation result of the first output sub-signal and the second output sub-signal as the output signal of the signal processing module.

[0020] Optionally, the logic gate circuit includes:

[0021] A NAND gate, the first input terminal of the NAND gate being connected to the first output terminal of the signal inversion control module, the second input terminal of the NAND gate being connected to the second output terminal of the signal inversion control module;

[0022] A second inverter, the input terminal of the second inverter being connected to the output terminal of the NAND gate, and the output terminal of the second inverter being the output terminal of the signal generation circuit.

[0023] Optionally, the logic gate circuit is an AND gate, the first input terminal of the AND gate being connected to the first output terminal of the signal inversion control module, the second input terminal of the AND gate being connected to the second output terminal of the signal inversion control module, and the output terminal of the AND gate being the output terminal of the signal generation circuit.

[0024] To solve the above technical problems, the present invention further provides a signal generation device, including an input signal generation module and the signal generation circuit as described above, and the output terminal of the input signal generation module is connected to the input terminal of the signal generation circuit.

[0025] The present invention provides a signal generation circuit, which includes a plurality of signal generation units. For any one signal generation unit, it can adjust the duty cycle of the input signal according to the reference signal it accesses, and then output the signal with the adjusted duty cycle as the output signal. At the same time, the output end of the previous signal generation unit is connected to the input end of the next signal generation unit, and the output signal output by the previous signal generation unit serves as the input signal of the next signal generation unit, enabling the signal generation unit to further adjust the duty cycle of the initial input signal on the basis of the output signal of the previous signal generation unit and then output it. Thus, different duty cycle output signals can be generated by using multiple signal generation units, and by selecting and setting different output nodes, multiple output signals with adjustable duty cycles and different output widths can be achieved.

[0026] The present invention also provides a signal generation device, which has the same beneficial effects as the above-mentioned signal generation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the prior art and the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1 It is a schematic structural diagram of a signal generation circuit provided by the present invention;

[0029] Figure 2 It is a schematic structural diagram of a signal generation circuit when the number of signal generation units provided by the present invention is 2;

[0030] Figure 3 It is a schematic structural diagram of a signal generation unit provided by the present invention;

[0031] Figure 4 It is a signal timing diagram of a signal generation circuit provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] The core of the present invention is to provide a signal generation circuit and a signal generation device. The signal generation unit can further adjust the duty cycle of the initial input signal on the basis of the output signal of the previous signal generation unit and then output it. By using multiple signal generation units to generate output signals with different duty cycles, and by selecting and setting different output nodes, multiple output signals with adjustable duty cycles and different output widths can be achieved.

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0034] Please refer to Figure 1 , Figure 1 , which is a schematic structural diagram of a signal generation circuit provided by the present invention; wherein, OUTN is the output signal of the Nth signal generation unit, and IN0 is the initial input signal; to solve the above technical problems, the present invention provides a signal generation circuit, including:

[0035] N signal generation units A, the N signal generation units A are connected in series, and the output end of the previous signal generation unit A is connected to the input end of the next signal generation unit A; wherein, the input end of the first signal generation unit A is connected to the initial input signal IN0, and the output end of any one signal generation unit A is used as the output end of the signal generation circuit; N is a natural number not less than 1.

[0036] The signal generation unit A is used to adjust the duty cycle of the initial input signal IN0 based on the reference signal accessed by itself to generate an output signal with a preset duty cycle.

[0037] It can be understood that, in order to implement an output signal with an adjustable duty cycle, the present application sets N signal generation units A in the signal generation circuit. The N signal generation units A are connected in series in sequence. At the same time, each signal generation unit A can, based on the reference signal accessed by itself, increase or decrease the duty cycle of the input signal by a preset value and then output it. Therefore, under the action of the first signal generation unit A on the initial input signal IN0, its duty cycle is adjusted by a first preset value, and the first signal generation unit A outputs a first output signal. The first output signal is used as an input signal and input into the second signal generation unit A. The second signal generation unit A further adjusts the duty cycle of its corresponding input signal, that is, the input signal, to a second preset value and then outputs it. The ith signal generation unit A adjusts the duty cycle of its corresponding input signal, that is, the output signal of the (i - 1)th signal generation unit, to the ith preset value and then outputs it. The second output signal output by the second signal generation unit A is the output signal after the duty cycle of the initial input signal IN0 is adjusted by the first preset value and the second preset value in sequence. The ith output signal output by the ith signal generation unit A is the output signal after the duty cycle of the initial input signal IN0 is adjusted by the first preset value, the second preset value... the ith preset value in sequence.

[0038] It is not difficult to understand that the N signal generation units A in the signal generation circuit output N output signals with different duty cycles. At this time, the output ends of any one or more signal generation units A can be used as the output end of the signal generation circuit according to requirements, so that the signal generation circuit can output an output signal with a preset duty cycle or multiple different duty cycles based on the same initial input signal, realizing output signals with different widths, thereby realizing a signal generation circuit with an adjustable output duty cycle.

[0039] It should be noted that the specific value of the preset duty cycle and the adjustment method of the output width of the signal generation circuit are not particularly limited in this application. Several signal generation units A can be directly set in the signal generation circuit, and output signals with different preset duty cycles can be realized by adjusting the position of the output end of the signal generation circuit; or the output end of the signal generation circuit can be fixedly set as the output end of the last signal generation unit A, and then the number of signal generation units A in the signal generation circuit can be set according to the required preset duty cycle, so as to realize output signals with different preset duty cycles.

[0040] Furthermore, there are also various implementation methods for adjusting the position of the output end of the signal generation circuit or the number of signal generation units. As an optional embodiment, the signal generation circuit further includes N - 1 controllable switch tubes, and every two adjacent signal generation units are connected through a controllable switch tube. Among them, every two adjacent signal generation units are connected through a controllable switch tube, including: the output end of the previous signal generation unit is connected to the first end of the controllable switch tube, the second end of the controllable switch tube is connected to the input end of the next signal generation unit, and the control end of the controllable switch tube is connected to a switch control signal; each controllable switch tube is used to control the signal generation unit to output an output signal with a preset duty cycle according to the switch control signal connected thereto. By controlling the corresponding controllable switch tube to conduct, the access of the corresponding previous signal generation unit and the output of the corresponding output signal are realized. Taking the example that each signal generation unit A increases the duty cycle of the input signal by 10% and the duty cycle of the initial input signal IN0 is 40%, if an output signal with a duty cycle of 50% is to be output, only the controllable switch tube corresponding to the output end of the first signal generation unit needs to be conducted, and the other N - 2 switch tubes remain off; if an output signal with a duty cycle of 70% is to be output, the controllable switch tubes corresponding to the output ends of the first signal generation unit, the second signal generation unit, and the third signal generation unit need to be conducted simultaneously, and the other N - 4 switch tubes remain off.

[0041] Further, the number of signal generation units connected can be adjusted by connecting controllable switching tubes in parallel with each signal generation unit to generate output signals with different preset duty cycles. As an alternative embodiment, the signal generation circuit further includes N controllable switching tubes, and each signal generation unit is connected in parallel with a corresponding controllable switching tube. Among them, each signal generation unit being connected in parallel with a corresponding controllable switching tube includes: the first end of the i-th controllable switching tube is connected to the input end of the i-th signal generation unit, the second end of the i-th controllable switching tube is connected to the output end of the i-th signal generation unit, and the control end of the i-th controllable switching tube receives a switching control signal. Each controllable switching tube is used to control the on / off of the corresponding signal generation unit according to the switching control signal received by itself to generate an output signal with a preset duty cycle.

[0042] It should be noted that the specific types and implementation manners of the respective signal generation units A are not particularly limited in this application. The respective signal generation units A can be implemented in the same manner, and the duty cycle adjustment amounts of the respective signal generation units A are kept consistent, so as to implement all the signal generation units A using the same circuit topology, saving R & D costs and having stronger versatility; or they can be implemented in different manners, and the duty cycle adjustment amounts of the respective signal generation units A are different. The specific values and implementation manners of the duty cycle adjustment amounts of the respective signal generation units A, that is, the first preset value, the second preset value... the i-th preset value, are not particularly limited in this application. The i-th preset value can be a fixed time amount or a ratio in the form of a percentage, etc. The specific types and implementation manners of the initial input signal IN0 and the reference signals received by the respective signal generation units A are not particularly limited in this application and can be selected according to actual application requirements.

[0043] It can be understood that this application proposes an implementation manner with an adjustable output duty cycle, that is, an adjustable output width. The duty cycle and output width of the output signal of the signal generation circuit are adjusted by the signal generation units A connected in series, specifically by adjusting the position of the output end and / or the number of signal generation units A. If a glitch or other type of interference signal is input into the signal generation circuit as the initial input signal IN0, and the duty cycle adjustment amounts of the signal generation units A are uniformly set to decrease by a certain amount of duty cycle, it is possible to filter input signals of different widths, thereby achieving the functions of glitch filtering and interference signal elimination. The specific application scenarios of the signal generation circuit are not particularly limited in this application, and are not limited only to the generation of output signals with a specific duty cycle or an adjustable duty cycle and the filtering of glitch signals with a certain width.

[0044] The present invention provides a signal generation circuit, which includes several signal generation units A. For any signal generation unit A, it can adjust the duty cycle of the input signal according to the reference signal accessed by itself, and then output the signal with the adjusted duty cycle as the output signal. At the same time, the output end of the previous signal generation unit A is connected to the input end of the next signal generation unit A, and the output signal output by the previous signal generation unit A serves as the input signal of the next signal generation unit A, so that the signal generation unit A can further adjust the duty cycle of the initial input signal IN0 on the basis of the output signal of the previous signal generation unit A and then output it. Thus, multiple output signals with different duty cycles are generated by using multiple signal generation units A, and by selecting and setting different output nodes, multiple output signals with adjustable duty cycles and different output widths can be realized.

[0045] Based on the above embodiments: Please refer to Figure 2 , Figure 2 FIG. is a schematic structural diagram of a signal generation circuit when the number of signal generation units provided by the present invention is 2; wherein, IN is the input end of the signal generation unit, OUT is the output end of the signal generation unit, CKP is the first reference end of the signal generation unit, and CKN is the second reference end of the signal generation unit. Please refer to Figure 3 , Figure 3 FIG. is a schematic structural diagram of a signal generation unit provided by the present invention; Di1 is the first output sub-signal of the i-th signal generation unit, Di2 is the second output sub-signal of the i-th signal generation unit, i is a positive integer not greater than N, IN is the input signal of the signal generation unit, and OUT is the output signal of the signal generation unit. Please refer to Figure 4 , Figure 4 FIG. is a signal timing diagram of a signal generation circuit provided by the present invention.

[0046] As an optional embodiment, for any signal generation unit A, the first reference end of the signal generation unit A accesses the first reference clock signal CLKP, the second reference end accesses the second reference clock signal CLKN, and the first reference clock signal CLKP and the second reference clock signal CLKN are opposite; the periods of the first reference clock signal CLKP and the second reference clock signal CLKN are both less than the period of the initial input signal IN0;

[0047] The signal generation unit A is specifically configured to control the level inversion of the accessed input signal based on the signal edges of the first reference clock signal CLKP and the second reference clock signal CLKN to adjust the duty cycle of the initial input signal IN0.

[0048] It is not difficult to understand that the output signal of the signal generation unit A is generated based on the input signal it accesses. Therefore, the period of the output signal of the signal generation unit A will always be consistent with the period of the initial input signal IN0. Therefore, specifically, the method of controlling the level inversion of the input signal can be adopted to adjust the high-level duration of the output signal, so as to realize the adjustment of the duty cycle of the input signal it accesses, and further realize the adjustment of the duty cycle of the initial input signal IN0. At this time, the signal generation unit A needs a reference as the trigger signal for controlling the level inversion. Therefore, a first reference clock signal CLKP and a second reference clock signal CLKN can be added. These two reference clock signals are respectively connected to the first reference terminal and the second reference terminal of each signal generation unit A. At the same time, a set of differential signals is set as the control signal, that is, the first reference clock signal CLKP and the second reference clock signal CLKN with opposite levels are set. The period of the first reference clock signal CLKP is equal to the period of the second reference clock signal CLKN. The signal generation unit A can achieve different level inversions by detecting different combinations of the signal edges of the first reference clock signal CLKP and the second reference clock signal CLKN, and control the level inversion of the input signal it accesses at different times.

[0049] It should be noted that the specific types and implementation methods of the first reference clock signal CLKP and the second reference clock signal CLKN are not particularly limited in this application. The specific values and correlation relationships of the periods of the reference clock signal and the initial input signal are not particularly limited in this application. The duty cycle of the output signal required by the final demand can be set and adjusted. The periods of the first reference clock signal CLKP and the second reference clock signal CLKN need to be set to be less than the period of the initial input signal IN0, so as to detect multiple signal edges of the first reference clock signal CLKP and / or the second reference clock signal CLKN within one period of the initial input signal IN0, so as to realize the level inversion of the input signal.

[0050] Specifically, the signal generation unit A can use two opposite reference clock signals it accesses as trigger signals to control the level inversion, so as to realize the adjustment of the high-level duration of the input signal it accesses, so as to adjust the duty cycle of the initial input signal IN0. It has high flexibility, and the two opposite reference clock signals have stronger anti-interference ability, which can effectively ensure the accuracy and reliability of the final output signal.

[0051] As an alternative embodiment, it further includes:

[0052] A reference clock signal generation module, the input end of the reference clock signal generation module is connected to a preset clock signal, the first output end of the reference clock signal generation module is respectively connected to the first reference ends of each signal generation unit A, and the second output end of the reference clock signal generation module is respectively connected to the second reference ends of each signal generation unit A, for generating a first reference clock signal CLKP and a second reference clock signal CLKN.

[0053] It can be understood that the first reference clock signal CLKP and the second reference clock signal CLKN accessed by the signal generation unit A can be directly implemented by using existing clock signals, or a reference clock signal generation module can be added and set in the signal generation circuit to generate them. The reference clock signal generation module can generate two opposite reference clock signals based on a preset clock signal, so as to provide the first reference clock signal CLKP and the second reference clock signal CLKN required for each signal generation unit A to adjust the duty cycle. The specific type and implementation method of the preset clock signal are not particularly limited in this application.

[0054] Specifically, a reference clock signal generation module can be directly set in the signal generation circuit to generate the first reference clock signal CLKP and the second reference clock signal CLKN required for each signal generation unit A, better realizing the isolation and shielding between the reference clock signal and other circuits, reducing the influence of external interference on the reference clock signal, improving the anti-interference ability and reliability of the two reference clock signals accessed by the signal generation unit A, not relying on externally provided clock signals, being able to completely autonomously control the parameters of the two opposite clock signals, and flexibly adjusting the characteristics of the reference clock signal according to actual application requirements, improving the autonomy and controllability of the entire signal generation circuit, and ensuring the flexibility of the signal generation circuit.

[0055] As an optional embodiment, the reference clock signal generation module includes:

[0056] A first inverter INV1, the input end of the first inverter INV1 is connected to a preset clock signal and serves as the first output end of the reference clock signal generation module, and the output end of the first inverter INV1 serves as the second output end of the reference clock signal generation module.

[0057] It is not difficult to understand that the reference clock signal generation module can specifically be implemented by the first inverter INV1. The first inverter INV1 can invert the signal input to itself and then output it, realizing the inversion of the signal. Therefore, the first inverter INV1 can be directly used to invert the preset clock signal, so that the signal at the input end of the first inverter INV1 is used as the first reference clock signal CLKP, and the signal at the output end of the first inverter INV1 is used as the second reference clock signal CLKN; or the signal at the input end of the first inverter INV1 is used as the second reference clock signal CLKN, and the signal at the output end of the first inverter INV1 is used as the first reference clock signal CLKP. At this time, the period of the preset clock signal, that is, the periods of the first reference clock signal CLKP and the second reference clock signal CLKN, needs to be less than the period of the initial input signal IN0. The specific type and implementation manner of the first inverter INV1 are not particularly limited in this application.

[0058] Specifically, directly using the first inverter INV1 to generate two opposite reference clock signals based on the preset clock signal has a simple circuit structure, low cost, is easy to implement, has a small signal transmission delay, fast conversion speed, can ensure the stability and reliability of the two opposite reference clock signals, is easy to integrate, has good scalability and compatibility, and is conducive to the simple implementation of the entire signal generation circuit.

[0059] As an alternative embodiment, the signal generation unit A includes:

[0060] A signal inversion control module. The input end of the signal inversion control module is connected to the corresponding input signal. The first reference end of the signal inversion control module is connected to the first reference clock signal CLKP. The second reference end of the signal inversion control module is connected to the second reference clock signal CLKN. The signal inversion control module is used to detect the preset signal edges of the first reference clock signal CLKP and the second reference clock signal CLKN, and control the first output sub-signal to flip to the level of the input signal according to the detection result of the first reference clock signal CLKP and the level of the input signal connected, and control the second output sub-signal to flip to the level of the input signal according to the detection result of the second reference clock signal CLKN and the level of the input signal connected; wherein, the level of the input signal includes a first level and a second level, and the states of the first level and the second level are opposite. The first output end of the signal inversion control module outputs the first output sub-signal, and the second output end outputs the second output sub-signal;

[0061] A signal processing module, the first input end of the signal processing module is connected to the first output end of the signal inversion control module, and the second input end of the signal processing module is connected to the second output end of the signal inversion control module. The signal processing module is used to determine the time period when both the first output sub-signal and the second output sub-signal are at the first level, and use the time period as the first-level continuous time period of the output signal to generate an output signal with a preset duty cycle.

[0062] It can be understood that the signal inversion control module in the signal generation unit A can control the input signal to perform level inversion based on the first reference clock signal CLKP and the second reference clock signal CLKN respectively, so as to generate the corresponding first output sub-signal and second output sub-signal. Then, different combinations of the first output sub-signal and the second output sub-signal are processed by the signal processing module to generate output signals with different duty cycles. The signal processing module can specifically use the AND method to process the first levels of the two output sub-signals. The signal inversion control module uses the input signal connected to itself as a reference, and uses the preset signal edge of the first reference clock signal CLKP or the second reference clock signal CLKN as the trigger signal for controlling the level inversion. When detecting the preset signal edge of the first reference clock signal CLKP or the second reference clock signal CLKN, it controls the corresponding output sub-signal to invert the level to the current level of the input signal. Among them, the signal inversion control module is specifically used to detect the preset signal edges of the first reference clock signal CLKP and the second reference clock signal CLKN, and when detecting the preset signal edge of the first reference clock signal CLKP and the input signal connected to itself is at the first level, control the first output sub-signal to invert to the first level; when detecting the preset signal edge of the second reference clock signal CLKN and the input signal connected to itself is at the first level, control the second output sub-signal to invert to the first level; when detecting the preset signal edge of the first reference clock signal CLKP and the input signal connected to itself is at the second level, control the first output sub-signal to invert to the second level; when detecting the preset signal edge of the second reference clock signal CLKN and the input signal connected to itself is at the second level, control the second output sub-signal to invert to the second level.

[0063] It should be noted that for any signal generation unit A and the signal inversion control module therein, the input signal refers to the signal connected to its input end. The specific types and implementation methods of the signal inversion control module and the signal processing module are not particularly limited in this application. The specific implementation method of the preset signal edge is not particularly limited in this application, and the preset signal edge can specifically be a rising edge or a falling edge. The specific implementation methods of the first level and the second level are not particularly limited in this application. If the first level is a high level, the second level is a low level; if the first level is a low level, the second level is a high level.

[0064] Specifically, in the signal generation unit A, the signal inversion control module can be set to control the level inversion of the input signal, and the first output sub-signal and the second output sub-signal are respectively inverted and generated based on the first reference clock signal CLKP and the second reference clock signal CLKN, so that the signal processing module can adjust the duty cycle of the output signal through the combined processing of the two output sub-signals.

[0065] As an alternative embodiment, the preset signal edge is the rising edge, and the signal inversion control module includes:

[0066] A first flip-flop, the input terminal of the first flip-flop is used as the input terminal of the signal inversion control module, the signal terminal of the first flip-flop is used as the first reference terminal of the signal inversion control module, and the first flip-flop is used to control the first output sub-signal to flip to the first level when detecting the rising edge of the first reference clock signal CLKP and the input signal connected is at the first level, and control the first output sub-signal to flip to the second level when detecting the rising edge of the first reference clock signal CLKP and the input signal connected is at the second level;

[0067] A second flip-flop, the input terminal of the second flip-flop is connected to the input terminal of the first flip-flop, the signal terminal of the second flip-flop is used as the second reference terminal of the signal inversion control module, and the second flip-flop is used to control the second output sub-signal to flip to the first level when detecting the rising edge of the second reference clock signal CLKN and the input signal connected is at the first level, and control the second output sub-signal to flip to the second level when detecting the rising edge of the second reference clock signal CLKN and the input signal connected is at the second level.

[0068] It is not difficult to understand that the signal inversion control module can specifically use flip-flops to detect the preset signal edge of the reference clock signal. At the same time, considering that the first output sub-signal and the second output sub-signal need to be generated respectively, the first flip-flop and the second flip-flop are respectively set in the signal inversion control module. The first flip-flop is used to detect the rising edge of the first reference clock signal CLKP to generate the first output sub-signal, and the second flip-flop is used to detect the rising edge of the second reference clock signal CLKN to generate the second output sub-signal. The specific types and implementation methods of the first flip-flop and the second flip-flop are not particularly limited in this application. For example, Figure 3 As shown, it can be implemented in the form of D flip-flops. The first flip-flop is implemented by the first D flip-flop D1, and the second flip-flop is implemented by the second D flip-flop D2. D is the input terminal of the D flip-flop, clk is the clock terminal of the D flip-flop, and Q is the output terminal of the D flip-flop.

[0069] Specifically, a trigger can be used to accurately locate the signal edge of the reference clock signal. Once the trigger detects a valid signal edge and updates the output state, the output state will remain stable before a new valid edge arrives, without being affected by the noise or transient interference in the input signal, ensuring the stability and reliability of the corresponding output sub-signal. It is convenient to integrate and is beneficial to implementing multiple signal generation units A.

[0070] As an alternative embodiment, the signal processing module is a logic gate circuit, and the logic gate circuit is used to output the logical operation result of the first output sub-signal and the second output sub-signal as the output signal of the signal processing module.

[0071] It can be understood that the signal processing module can specifically perform different combinations of logical operations on the first output sub-signal and the second output sub-signal through a logic gate circuit, thereby changing the high and low level durations of the output signal, and further adjusting the duty cycle. The specific type and implementation method of the logic gate circuit are not particularly limited in this application.

[0072] Specifically, the logic gate circuit can effectively implement different logical operation functions, thereby realizing different combinations of the first output sub-signal and the second output sub-signal to generate output signals with different duty cycles; the signal processing speed of the logic gate circuit is fast, and its stability and anti-interference ability are strong, which can effectively ensure the reliable output of the output signal.

[0073] As an alternative embodiment, the logic gate circuit is an AND gate. The first input terminal of the AND gate is connected to the first output terminal of the signal flip control module, the second input terminal of the AND gate is connected to the second output terminal of the signal flip control module, and the output terminal of the AND gate is used as the output terminal of the signal generation circuit.

[0074] It is not difficult to understand that in an application scenario where it is necessary to reduce the duty cycle of the initial input signal, the logic gate circuit can directly use an AND gate to achieve this. By means of AND operation, the high level durations of the first output sub-signal and the second output sub-signal are further shortened to achieve the function of quickly decreasing the duty cycle. The specific type and implementation method of the AND gate are not particularly limited in this application.

[0075] Specifically, different logic gate circuits can be selected according to different application scenarios to process the output sub-signal. Specifically, the reduction of the duty cycle of the output signal can be achieved through the setting of the AND gate, which is simple, effective, and easy to implement.

[0076] As an alternative embodiment, the logic gate circuit includes:

[0077] A NAND gate, the first input terminal of the NAND gate is connected to the first output terminal of the signal inversion control module, and the second input terminal of the NAND gate is connected to the second output terminal of the signal inversion control module;

[0078] A second inverter INV2, the input terminal of the second inverter INV2 is connected to the output terminal of the NAND gate, and the output terminal of the second inverter INV2 serves as the output terminal of the signal generation circuit.

[0079] It can be understood that in order to improve the flexibility and versatility of the signal generation circuit, a series-connected NAND gate and a second inverter INV2 can also be used to replace the AND gate to implement a logic gate circuit. The NAND gate will perform a NAND operation on the first output sub-signal and the second output sub-signal and then output it to the second inverter INV2 for inversion, and output the operation signal to the second inverter INV2 for further processing, which can effectively improve the driving ability of the output signal of the final signal generation unit A and optimize the signal transmission quality in the signal generation unit A. By changing the power supply voltage of the second inverter INV2 or adding a variable resistor or capacitor to the output terminal or feedback loop of the inverter, etc., the driving of the output signal can also be further adjusted, so that the signal generation unit A and the signal generation circuit can adapt to different load requirements and different application environments.

[0080] As a specific embodiment, taking the case where two signal generation units are provided in the signal generation circuit as an example, the initial input signal IN is connected to the first signal generation unit and serves as the input signal of the first signal generation unit. The output signal OUT1 of the first signal generation unit also serves as the input signal of the second signal generation unit at the same time. The output signal OUT2 of the second signal generation unit can be set as the final output signal of the signal generation circuit. The first reference clock signal CLKP and the second reference clock signal CLKN are two opposite clock signals, and their periods are both T1, and their signal frequencies are higher than the frequency of the initial input signal IN. The period of the initial input signal IN is T2, so T1 < T2. The internal structures of the two signal generation units are both as Figure 3 shown.

[0081] Taking the preset signal edge as the rising edge as an example, for any signal generation unit, when its input signal passes through the signal generation unit, such as Figure 3As shown, the input signal IN connected to the input end of the signal generation unit is respectively input into two D flip-flops. The clock end of the first D flip-flop is connected to the first reference clock signal CLKP, and the clock end of the second D flip-flop is connected to the second reference clock signal CLKN. After the two D flip-flops collect the rising edge of the corresponding first reference clock signal CLKP or the rising edge of the second reference clock signal CLKN, they respectively output a first output sub-signal and a second output sub-signal to the NAND gate, and then pass through the second inverter, and finally output the output signal OUT of the entire signal generation unit from the output end of the signal generation unit.

[0082] The signal timing diagram when the input signal passes through the signal generation unit is as Figure 4 shown. The input signal IN is output as OUT after passing through the signal generation unit. The first flip-flop D1 samples the level of the input signal IN connected to the input end of the D flip-flop when the first reference clock signal CLKP changes from 0 to 1 (rising edge). That is, for the first signal generation unit, its first output sub-signal D11 goes high when the first rising edge of the first reference clock signal CLKP comes after the input signal IN becomes high level, and goes low when the first rising edge of the first reference clock signal CLKP comes after the input signal IN becomes low level. The second flip-flop D2 samples the level of the input signal IN connected to the D flip-flop end when the second reference clock signal CLKN changes from 0 to 1 (rising edge). That is, for the first signal generation unit, its second output sub-signal D12 goes high when the first rising edge of the second reference clock signal CLKN comes after the input signal IN becomes high level, and goes low when the first rising edge of the second reference clock signal CLKN comes after the input signal IN becomes low level. After performing NAND and inversion operations on the first output sub-signal D11 and the second output sub-signal D12, the output signal OUT1 of the first signal generation unit is obtained. That is, the initial input signal is output as OUT1 after passing through the first signal generation unit, and at this time, the high-level interval of OUT1 is T1, that is, the duty cycle of the output signal OUT1 becomes T1 / T2. Similarly, the signal OUT1 is used as the input signal to pass through the second signal generation unit. The first flip-flop in the second signal generation unit outputs the first output sub-signal D21, and the second flip-flop in the second signal generation unit outputs the second output sub-signal D22. After calculation, the output signal OUT2 of the second signal generation unit is obtained, and the high-level interval of the output signal OUT2 becomes T1 / 2. Then the duty cycle of the output signal OUT2 is T1 / 2*T2.

[0083] Further, if N signal generation units as Figure 3 shown are set in the signal generation circuit, after the initial input signal passes through N signal generation units, the output signal of the Nth signal generation unit is OUTN. Then the duty cycle of OUTN is: T1 / (2 N-1*T2). Therefore, in circuit applications, by setting and selecting appropriate nodes as the output terminals of the signal generation circuit, or by setting the number of different signal generation units, the duty cycle of the output signal of the final signal generation circuit can be changed accordingly, and the input signal can be converted into a signal with an adjustable duty cycle. It is not difficult to find that after being processed by the signal generation unit multiple times, the high-level interval of the initial input signal will continuously become smaller. When the duty cycle is very small, that is, the high-level time is very short, especially when the duration of the high level is less than the setup time of a flip-flop (for example, the setup time of a D flip-flop is generally within 1 ns), the flip-flop cannot capture this very narrow high-level interval, and the whole process is equivalent to filtering out the glitch signal, which can be used to implement glitch filtering.

[0084] Specifically, the signal generation unit can be implemented by adopting a circuit architecture including a flip-flop, a NAND gate, and a second inverter. This architecture implementation is simple, does not require additional complex circuits, can be implemented by common logic units, the whole circuit architecture is easy to integrate, has a small area and low cost, can be widely applied to the signal generation circuit with an adjustable duty cycle, and can meet the non-ideal changes of the initial input signal IN0 caused by process deviations by setting different output node selections, and has strong robustness. In addition, it can also be applied to the glitch filtering circuit, and has certain versatility and practical value. The working state of the digital circuit is relatively stable, less affected by environmental factors, and can effectively ensure the stability and reliability of the output signal.

[0085] To solve the above technical problems, the present invention also provides a signal generation device, including an input signal generation module and the signal generation circuit as described above, and the output terminal of the input signal generation module is connected to the input terminal of the signal generation circuit.

[0086] It is not difficult to understand that the input signal generation module can be set in the signal generation device to generate initial input signals with different periods according to requirements, and the generated initial input signals are then input into the signal generation circuit to generate output signals with an adjustable duty cycle. The specific type and implementation manner of the input signal generation module are not particularly limited in this application. The specific setting quantity of the signal generation units in the signal generation circuit and the setting position of the output node of the output signal of the signal generation circuit are not particularly limited in this application, and can be set and adjusted according to actual application requirements.

[0087] For the introduction of a signal generation device provided by the present invention, please refer to the embodiments of the above signal generation circuit, and the present invention will not be elaborated here.

[0088] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts among the embodiments can be referred to each other. It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the existence of another identical element in the process, method, article or device comprising the said element.

[0089] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A signal generating circuit, characterized in that: include: N signal generating units, the N signal generating units are connected in series, and the output end of the previous signal generating unit is connected to the input end of the next signal generating unit; wherein the input end of the first signal generating unit is connected to the initial input signal, and the output end of any signal generating unit is used as the output end of the signal generating circuit; N is a natural number not less than 1; The signal generating unit is used for adjusting the duty cycle of the initial input signal based on the reference signal connected to the unit to generate an output signal with a preset duty cycle.

2. The signal generating circuit according to claim 1, wherein: For any of the signal generating units, a first reference terminal of the signal generating unit is connected to a first reference clock signal, and a second reference terminal is connected to a second reference clock signal, the first reference clock signal and the second reference clock signal are opposite; a period of the first reference clock signal and a period of the second reference clock signal are both smaller than a period of the initial input signal; The signal generating unit is specifically used to control the level flipping of the input signal connected based on the signal edges of the first reference clock signal and the second reference clock signal, so as to adjust the duty cycle of the initial input signal.

3. The signal generating circuit according to claim 2, wherein: Also includes: A reference clock signal generating module, wherein the input end of the reference clock signal generating module is connected to a preset clock signal, the first output end of the reference clock signal generating module is respectively connected to the first reference end of each of the signal generating units, and the second output end of the reference clock signal generating module is respectively connected to the second reference end of each of the signal generating units, for generating a first reference clock signal and a second reference clock signal.

4. The signal generating circuit according to claim 3, wherein: The reference clock signal generating module comprises: A first inverter, wherein an input end of the first inverter is connected to a preset clock signal and serves as a first output end of the reference clock signal generating module, and an output end of the first inverter serves as a second output end of the reference clock signal generating module.

5. The signal generating circuit according to any one of claims 2 to 4, characterized in that: The signal generating unit comprises: A signal flip control module, wherein the input end of the signal flip control module is connected to a corresponding input signal, the first reference end of the signal flip control module is connected to a first reference clock signal, and the second reference end of the signal flip control module is connected to a second reference clock signal. The signal flip control module is used to detect preset signal edges of the first reference clock signal and the second reference clock signal, and control the first output sub-signal to flip to the level of the input signal according to the detection result of the first reference clock signal and the level of the connected input signal, and control the second output sub-signal to flip to the level of the input signal according to the detection result of the second reference clock signal and the level of the connected input signal; wherein the level of the input signal includes a first level and a second level, and the states of the first level and the second level are opposite, and the first output end of the signal flip control module outputs the first output sub-signal, and the second output end outputs the second output sub-signal; A signal processing module, wherein the first input end of the signal processing module is connected to the first output end of the signal flip control module, and the second input end of the signal processing module is connected to the second output end of the signal flip control module. The signal processing module is used to determine a time period in which the first output sub-signal and the second output sub-signal are both at a first level, and use the time period as a first level duration period of the output signal to generate an output signal with a preset duty cycle.

6. The signal generating circuit according to claim 5, characterized in that: The preset signal edge is a rising edge, and the signal flip control module includes: a first trigger, wherein an input end of the first trigger serves as an input end of the signal flip control module, a signal end of the first trigger serves as a first reference end of the signal flip control module, and the first trigger is used to control the first output sub-signal to flip to the first level when a rising edge of the first reference clock signal is detected and the connected input signal is at a first level, and to control the first output sub-signal to flip to the second level when a rising edge of the first reference clock signal is detected and the connected input signal is at a second level; A second trigger, the input end of the second trigger is connected to the input end of the first trigger, the signal end of the second trigger serves as the second reference end of the signal flip control module, the second trigger is used to control the second output sub-signal to flip to the first level when the rising edge of the second reference clock signal is detected and the connected input signal is at the first level, and to control the second output sub-signal to flip to the second level when the rising edge of the second reference clock signal is detected and the connected input signal is at the second level.

7. The signal generating circuit according to claim 5, characterized in that: The signal processing module is a logic gate circuit, and the logic gate circuit is used to output the logic operation result of the first output sub-signal and the second output sub-signal as the output signal of the signal processing module.

8. The signal generating circuit according to claim 7, wherein: The logic gate circuit comprises: A NAND gate, wherein a first input terminal of the NAND gate is connected to a first output terminal of the signal flip control module, and a second input terminal of the NAND gate is connected to a second output terminal of the signal flip control module; A second inverter, wherein the input end of the second inverter is connected to the output end of the NAND gate, and the output end of the second inverter serves as the output end of the signal generating circuit.

9. The signal generating circuit according to claim 7, wherein: The logic gate circuit is an AND gate, the first input end of the AND gate is connected to the first output end of the signal flip control module, the second input end of the AND gate is connected to the second output end of the signal flip control module, and the output end of the AND gate serves as the output end of the signal generating circuit.

10. A signal generating device, characterized in that: It comprises an input signal generating module and a signal generating circuit as claimed in any one of claims 1 to 9, wherein the output end of the input signal generating module is connected to the input end of the signal generating circuit.

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