Super junction LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with double gates

Abstract

The invention provides a super junction LDMOS device with double gates, which comprises a substrate, a source region, a drain region, a gate region and a super junction structure region, and is characterized in that the gate region comprises a first gate and a second gate. The first grid electrode and the second grid electrode use a conducting medium wrapped by a high-dielectric-constant material, a sandwich structure of the conducting medium-HK-P-well can be generated, a channel of the sandwich structure is of a longitudinal structure, and when the grid electrodes are in a pressurized state, namely in a device starting state, the structure can be regarded as a capacitor to accumulate a certain number of electrons at the edge, close to HK, of the P-well, so that the performance of the device is improved. Therefore, the on-resistance of the channel is reduced, and the current is increased. The dual-gate structure can also increase the current paths of the N region and the P-well region, and the on-resistance is effectively reduced through the parallel connection characteristic of multiple current paths.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to a super junction LDMOS device with a double gate. Background Art

[0002] The Lateral Diffused Metal Oxide Semiconductor Field Effect Transistor (LDMOS) is a key technology for high-voltage integrated circuits and power integrated circuits, and has the advantages of fast switching speed, easy driving, low driving power, and low switching power consumption. For many years, it has been developing towards high breakdown voltage (BV) and low specific on-resistance (Ron,sp). A higher breakdown voltage requires the device to have a longer drift region length and a lower doping concentration in the drift region, which results in a higher on-resistance of the device.

[0003] The super junction LDMOS device (SJ-LDMOS) is an improved LDMOS device, that is, the low-doped N-type drift region of the traditional LDMOS device is replaced by a group of alternately arranged N-type pillar regions and P-type pillar regions. By introducing multiple PN junctions laterally, the charges in the drift region can be completely depleted at a relatively low turn-off voltage, and the breakdown voltage is only related to the depletion layer thickness and the critical electric field. Therefore, under the same withstand voltage, the doping concentration of the drift region of the super junction structure can be increased by an order of magnitude, greatly reducing the on-resistance. Moreover, when the voltage increases, the distribution of the electric field is relatively uniform, reducing the risk of breakdown caused by concentration at a certain point. By depleting the drift region, the super junction LDMOS device can achieve a lower electric field strength at high voltages, improving the breakdown voltage of the device.

[0004] The field plate technology adjusts the electric field distribution between the source and drain of the LDMOS. The position and geometry of the field plate will significantly affect the spatial distribution of the electric field. A well-designed field plate structure can achieve a uniform distribution of the electric field in the drift region by reducing the surface peak electric field and enhancing the lateral electric field, thereby effectively improving the breakdown voltage of the LDMOS device.

[0005] When the SJ-LDMOS device is in the off state, the N-type columns in the superjunction drift region are not only depleted by the adjacent P-type columns but also depleted by the P-type high-resistance substrate. This process results in incomplete depletion of the P-type columns, limiting the superjunction breakdown voltage region to withstand a higher breakdown voltage and weakening the overall device performance. This phenomenon is called the substrate-assisted depletion effect (see reference: I.Y. Park and C.A.T. Salama, “Super Junction LDMOS Transistors-Implementing super junction LDMOS transistors to overcome substrate depletion effects”, IEEE Circuits and Devices Magazine, pp. 10-15, Nov.-Dec. 2006).

[0006] The utility model patent with the publication number CN221201181U discloses a superjunction LDMOS structure, including: a first-conductivity-type substrate, a second-conductivity-type epitaxial layer. The surface of the second-conductivity-type epitaxial layer is provided with a superjunction region, and the superjunction region includes multiple superjunction layers. The multiple superjunction layers are distributed in parallel in the second-conductivity-type epitaxial layer along the vertical direction. The superjunction layer is composed of second-conductivity-type doped regions and first-conductivity-type doped regions that are alternately distributed one by one along the longitudinal direction. By increasing the proportion of the lateral superjunction in the drift region, the depletion function of the device is further improved, and the on-resistance of the device is reduced. However, there is still room for further reduction of the on-resistance of the superjunction LDMOS. Summary of the Invention

[0007] To solve the above technical problems existing in the prior art, the present invention provides a superjunction LDMOS device with a dual gate, which can improve the breakdown voltage of the LDMOS device and reduce the on-resistance of the LDMOS device.

[0008] The present invention provides a superjunction LDMOS device with a dual gate, including a substrate, a source region, a drain region, a gate region, and a superjunction structure region. A P-well is provided below the source region and on one side of the source region close to the drain region. The superjunction structure region is located above the substrate. The drain region and the P-well are respectively embedded in the superjunction structure region. The source region is embedded in the P-well.

[0009] The gate region includes a first gate and a second gate. The first gate is located above the superjunction structure region and contacts the source region and the side of the P-well away from the drain region on one side. The second gate is located above the P-well and extends above the superjunction structure region between the P-well and the drain region.

[0010] The bottom surface of the first gate and the side in contact with the source region and the P-well are wrapped with a high dielectric constant material (HK), and the bottom surface of the second gate is wrapped with a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than SiO 2 The dielectric constant of .

[0011] Preferably, a field oxide layer is further provided on the super junction structure region between the P-well and the drain region, for isolating the source region and the drain region to prevent unnecessary current from flowing therebetween.

[0012] Further preferably, the field oxide layer is a shallow trench isolation (STI) structure provided in the super junction structure region between the P-well and the drain region, and the shallow trench isolation structure is filled with SiO 2 The shallow trench isolation structure is wrapped with a layer of high dielectric constant material on the surface in contact with the super junction structure region. 2 Significant difference in dielectric constant, most of the electric flux tends to pass through Si rather than SiO 2 , this structure will generate a new electric field peak, making the surface electric field more uniform. HK can effectively alleviate the electric field concentration phenomenon in Si, thereby further depleting the super junction structure area. This structure can effectively improve the withstand voltage of the super junction structure area, further increase the doping concentration of the N region in this area, and thus reduce the on-resistance.

[0013] Further preferably, the second gate extends toward the drain region to the upper surface of the field oxide layer to serve as a field plate of the super junction LDMOS device. At the same time, HK can alleviate the electric field peak at the edge of the second gate, making the electric field on the device surface more uniform. This structure combined with the shallow trench isolation structure can enhance this effect.

[0014] Further preferably, the width of the overlapping region between the second gate and the field oxide layer is between 1 / 4 and 3 / 4 of the width of the field oxide layer.

[0015] Preferably, the conductive medium in the first gate and the second gate is Al, and the high dielectric constant material is Si 3 N 4 、Al 2 O 3 , Y 2 O 3 ,La 2 O 3 、 2 O 5 、TiO 2 , HfO 2 and ZrO 2 One or more of .

[0016] Preferably, the source region is composed of a P + region and an N + region, where the P + region is located in the middle of the two N + regions and is interconnected; the drain region is composed of an N + region.

[0017] Preferably, the superjunction structure region is a longitudinally alternating arrangement of N-type doped regions and P-type doped regions.

[0018] Preferably, the substrate is a SOI substrate. The SOI substrate includes a P-type silicon substrate and a SOI layer located above the P-type silicon substrate. The SOI layer is silicon dioxide. The SOI substrate can effectively avoid the substrate-assisted depletion effect in the SJ structure, improve the longitudinal breakdown voltage characteristics of the device, and at the same time utilize the dielectric constant difference between silicon dioxide and silicon to assist in depleting the lower half of the SJ structure, improve the lateral breakdown voltage, increase the doping concentration of the N region, and reduce the on-resistance.

[0019] The present invention also provides an application of the above superjunction LDMOS device with double gates in power devices, such as being applicable to high-power devices such as automotive electronics and machine tools.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] (1) The first gate and the second gate use a conductive medium wrapped by a high-k material, which can generate a sandwich structure of conductive medium - HK - P-well. When the gate is under pressure, that is, when the device is in the on state, this structure can be regarded as a capacitor accumulating a certain number of electrons at the edge of the P-well close to HK, thereby reducing the on-resistance of the channel and increasing the current.

[0022] (2) The double-gate structure can increase the current paths in the N region and the P-well region, and effectively reduce the on-resistance through the parallel characteristics of multiple current paths. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a three-dimensional structural schematic diagram of the superjunction LDMOS device with double gates of the present invention.

[0024] Figure 2 is Figure 1 a three-dimensional structural schematic diagram of the internal structure perspective. DETAILED DESCRIPTION OF THE INVENTION

[0025] As Figures 1 - 2As shown in the figure, this embodiment provides a superjunction LDMOS device with a double gate, including a substrate, a source region (Source), a drain region (Drain), a gate region (Gate), and a superjunction structure region. A P-well is provided below the source region and on one side of the source region close to the drain region.

[0026] The source region is composed of a P + region and an N + region, where the P + region is located in the middle of the two N + regions and are connected to each other. The drain region is composed of an N + region.

[0027] The superjunction structure region is located above the substrate. The superjunction structure region is a longitudinally alternating arrangement of N-type doped regions and P-type doped regions. The drain region and the P-well are respectively embedded on the superjunction structure region, and the source region is embedded on the P-well.

[0028] A field oxide layer is also provided between the P-well and the drain region on the superjunction structure region. The field oxide layer is a shallow trench isolation structure (STI) of the superjunction structure region between the P-well and the drain region, and the shallow trench isolation structure is filled with SiO 2 . Due to the significant difference in the dielectric constants of Si and SiO 2 , most of the electric flux tends to pass through Si rather than SiO 2 , and this structure will generate new electric field peaks, making the surface electric field more uniform.

[0029] A high-k dielectric material (HK) is coated on the surface of the shallow trench isolation structure in contact with the superjunction structure region. The high-k dielectric material is a material with a dielectric constant greater than that of SiO 2 , such as Si 3 N 4 、Al 2 O 3 、Y 2 O 3 、La 2 O 3 、Ta 2 O 5 、TiO 2 、HfO 2 and ZrO 2 or more of them. HK can effectively relieve the electric field concentration phenomenon in Si, thereby further depleting the superjunction structure region. This structure can effectively improve the breakdown voltage of the superjunction structure region and further increase the doping concentration of the N region in this area, thereby reducing the on-resistance.

[0030] The gate region includes a first gate and a second gate. The conductive medium in the first gate and the second gate is Al. The first gate is located above the superjunction structure region and contacts one side of the source region and the side of the P-well away from the drain region on one side; the second gate is located above the P-well and extends above the superjunction structure region between the P-well and the drain region;

[0031] The bottom surface of the first gate and the surface in contact with the source region and the P-well are coated with a high-k dielectric material (HK), and the bottom surface of the second gate is coated with a high-k dielectric material.

[0032] The second gate extends towards the drain region to the upper surface of the field oxide layer and serves as the field plate of the superjunction LDMOS device. The width of the overlapping region between the second gate and the field oxide layer is between 1 / 4 and 3 / 4 of the width of the field oxide layer. At the same time, HK can relieve the electric field peak at the edge of the second gate, making the surface electric field of the device more uniform. This structure combined with the shallow trench isolation structure can enhance this effect.

[0033] The substrate is an SOI substrate. The SOI substrate includes a P-type silicon substrate and an SOI layer located above the P-type silicon substrate. The SOI layer is silicon dioxide. The SOI substrate is usually obtained by fabricating a single-crystal silicon thin film on silicon dioxide. The SOI substrate can effectively avoid the substrate-assisted depletion effect in the SJ structure, improve the longitudinal breakdown voltage characteristics of the device, and at the same time, utilize the dielectric constant difference to assist in depleting the lower half of the SJ structure, improve the lateral breakdown voltage, increase the doping concentration of the N region, and reduce the on-resistance.

[0034] This superjunction LDMOS device with a dual gate can be applied to high-power devices such as automotive electronics and machine tools.

[0035] Working principle:

[0036] When the potentials of the first gate and the second gate of the LDMOS device are 0, the device is in the off state, and the high voltage at the drain will be entirely borne by the N-type highly doped region in the superjunction structure region. When a voltage comes, the superjunction structure region set in this device will be depleted pairwise of NPNP, thereby enhancing the depletion degree of this region. The shallow trench isolation structure will generate a new electric field peak, making the surface electric field more uniform. The HK on the bottom surface of the second gate can relieve the electric field peak at the edge of the second gate, making the surface electric field of the device more uniform, thereby effectively increasing the breakdown voltage of the LDMOS device. And the HK on the surface where the shallow trench isolation structure contacts the superjunction structure region can effectively relieve the electric field concentration phenomenon in Si, thereby further depleting the superjunction structure region. This structure can effectively increase the breakdown voltage of the superjunction structure region, further increase the doping concentration of the N region in this region, thereby reducing the on-resistance.

[0037] The silicon dioxide insulating layer in the SOI substrate isolates the active silicon layer from the substrate. In this way, the substrate is not electrically coupled to the active region, avoiding the occurrence of the substrate-assisted depletion effect. Due to the presence of the insulating layer, SOI devices have a smaller parasitic capacitance, which helps to improve the switching speed and efficiency of the devices.

[0038] Since the gate at 0 potential has an accumulation effect, it can be depleted even when the concentration of the P-type highly doped region is lower. Therefore, the same breakdown voltage rating as that of the traditional superjunction LDMOS can be obtained, and at the same time, the concentration of the P-type highly doped region in this structure can be reduced. The reduction in the concentration of the P-type highly doped region can increase the channel concentration in the on-state of the device, thereby reducing the value of the on-resistance.

[0039] When the potential of the first gate of the LDMOS device is at a high potential, the device is in the on-state, and a longitudinal channel is formed in the P-well. Carriers longitudinally pass through the part of the P-well close to the first gate and reach the superjunction structure region to form a carrier path; when the potential of the second gate is at a high potential, a transverse channel is formed in the P-well. Carriers transversely pass through the part of the P-well close to the second gate and reach the superjunction structure region to form a carrier path; when the potentials of both the first gate and the second gate are at high potentials, the channels in both directions are opened simultaneously, increasing the path for carriers to flow from the drain to the source, which is equivalent to adopting a form of parallel connection of multiple current paths, thereby reducing the on-resistance.

[0040] In addition, the first gate and the second gate use a conductive medium wrapped by a high-k material, which can produce a sandwich structure of conductive medium - HK - P-well. In the on-state, this structure can be regarded as a capacitor accumulating a certain number of electrons at the edge of the P-well close to HK, thereby reducing the on-resistance of the channel and increasing the current.

Claims

1. A super junction LDMOS device with dual gates, comprising a substrate, a source region, a drain region, a gate region and a super junction structure region, wherein a P-well is provided below the source region and on a side of the source region close to the drain region, characterized in that: The super junction structure region is located above the substrate, the drain region and the P-well are respectively embedded in the super junction structure region, and the source region is embedded in the P-well; The gate region includes a first gate and a second gate, wherein the first gate is located above the super junction structure region and one side of the first gate contacts the source region and the side of the P-well away from the drain region; the second gate is located above the P-well and extends to the super junction structure region between the P-well and the drain region; The bottom surface of the first gate and the side in contact with the source region and the P-well are wrapped with a high dielectric constant material, and the bottom surface of the second gate is wrapped with a high dielectric constant material, and the dielectric constant of the high dielectric constant material is greater than the dielectric constant of SiO2.

2. The super junction LDMOS device with dual gates according to claim 1, characterized in that: A field oxide layer is also provided on the super junction structure region between the P-well and the drain region.

3. The super junction LDMOS device with dual gates according to claim 2, characterized in that: The field oxide layer is a shallow trench isolation structure of the super junction structure region between the P-well and the drain region, the shallow trench isolation structure is filled with SiO2, and the shallow trench isolation structure is wrapped with a layer of high dielectric constant material on the surface in contact with the super junction structure region.

4. The super junction LDMOS device with dual gates according to claim 3, characterized in that: The second gate extends toward the drain region to the upper surface of the field oxide layer.

5. The super junction LDMOS device with dual gates according to claim 4, characterized in that: The width of the overlapping region between the second gate and the field oxide layer is between 1 / 4 and 3 / 4 of the width of the field oxide layer.

6. The super junction LDMOS device with dual gates according to claim 1, characterized in that: The conductive medium in the first gate and the second gate is Al, and the high dielectric constant material is one or more of Si3N4, Al2O3, Y2O3, La2O3, Ta2O5, TiO2, HfO2 and ZrO2.

7. The super junction LDMOS device with dual gates according to claim 1, characterized in that: The source region is composed of P + Area and N + The area is composed of + The area is located between two N + The drain region is composed of N + District composition.

8. The super junction LDMOS device with dual gates according to claim 1, characterized in that: The substrate is an SOI substrate, which includes a P-type silicon substrate and an SOI layer located above the P-type silicon substrate.

9. The super junction LDMOS device with dual gates according to claim 1, characterized in that: The super junction structure region is an N-type doping region and a P-type doping region which are alternately arranged vertically.

10. Application of the super junction LDMOS device with dual gates according to any one of claims 1 to 9 in power devices.

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