Method for constructing micro-coarsening structure, micro-coarsening structure and micro light-emitting diode chip applied to micro-coarsening structure

Abstract

The invention relates to the technical field of light emitting diodes, and provides a method for constructing a micro-coarsening structure and the structure. The method comprises the following steps: providing a to-be-treated surface layer; growing a metal layer on the surface layer to be treated; performing high-temperature annealing on the metal layer to agglomerate metal to form metal particles; and taking the metal particles as a mask, and etching the surface layer to be treated to generate a micro coarsening structure. The coarsening granularity size, depth and speed of the micro coarsening structure generated by the method are controllable, and the coarsening granularity size and depth can reach the size from dozens of # imgabs0 # to dozens of microns. Therefore, the method can be well suitable for coarsening the surface of a miniature light-emitting diode with small size and micron-level or submicron-level pixel size.

Description

Technical Field

[0001] The present invention generally relates to the technical field of light-emitting diodes (LEDs). Specifically, the present invention relates to a method for constructing a micro-roughened structure, the micro-roughened structure, and a micro light-emitting diode chip to which it is applied. Background Art

[0002] Micro light-emitting diodes (Micro-LEDs) are an emerging flat panel display technology. It consists of countless tiny LEDs, and each LED is a pixel point. These pixel points are very small, usually only dozens of micrometers or even smaller. Compared with traditional LCD and OLED displays, Micro-LEDs have advantages such as higher brightness, faster response speed, wider color gamut, and longer lifespan.

[0003] For traditional LEDs, roughening the surface of the LED can effectively improve its light extraction efficiency. Traditional LED roughening methods usually use wet etching. However, this method has problems such as relatively large etching granularity, and it is difficult to precisely control the etching depth, rate, and granularity, which poses a huge challenge to the miniaturization and refinement manufacturing of Micro-LEDs.

[0004] Specifically, the limitations of wet etching are mainly reflected in the following aspects: insufficient etching accuracy: Wet etching often uses chemical solutions for corrosion, and the reaction process is not easy to control, resulting in a relatively large surface roughness of the etching, making it difficult to meet the requirements of Micro-LED for micro-nano scale fine structures; poor selectivity: Wet etching has poor selectivity for different materials, easily causing side etching and over-etching, affecting the performance and reliability of the device; environmental pollution: The chemical waste liquid generated during the wet etching process pollutes the environment, which is not conducive to green manufacturing; complex process: In order to obtain the desired etching effect, multiple experiments and adjustment of process parameters are often required, and the process flow is complex and the cycle is long.

[0005] As a new display technology, Micro-LED puts forward higher requirements for the miniaturization and high-density integration of devices. Since the traditional wet etching process can no longer meet these needs, it is urgent to develop new roughening technologies to achieve the efficient and precise manufacturing of Micro-LEDs. Summary of the Invention

[0006] To solve the above problems in the prior art, embodiments of the present invention propose a method for constructing a micro-roughened structure, which is characterized by including the following steps:

[0007] Step 01: Provide a surface layer to be processed;

[0008] Step 02: Grow a metal layer on the surface layer to be processed;

[0009] Step 03: Perform high-temperature annealing on the metal layer to agglomerate it to form metal particles;

[0010] Step 04: Use the metal particles as a mask to etch the surface layer to be processed to generate a micro-roughened structure.

[0011] In an embodiment of the present invention, it is stipulated that in Step 02, the thickness of the metal layer is 1 nm to 10 μm.

[0012] In an embodiment of the present invention, it is stipulated that the material of the metal layer is one or more of Au, Ag, Cu, Al, Sn, AuGe, and Ni.

[0013] In an embodiment of the present invention, it is stipulated that in Step 03, the process parameters of the high-temperature annealing include: the temperature is 200 °C to 500 °C, the time is 10 s to 30 min, and the atmosphere includes N 2 , Ar, O 2 and H 2 one or more of them.

[0014] In an embodiment of the present invention, it is stipulated that in Step 04, the etching gas used for etching includes: Cl 2 , BCl 3 , Ar, CF 4 , CHF 3 , SF 6 , O 2 , N 2 , HF, and CH 4 one or more of them.

[0015] In an embodiment of the present invention, it is stipulated that the process used for etching is: ICP, ALE, or RIE dry etching.

[0016] In an embodiment of the present invention, it is stipulated that the particle size of the metal particles is 1 nanometer to 10 micrometers.

[0017] In an embodiment of the present invention, it is stipulated that in Step 04, the generated micro-roughened structure includes multiple roughened particles; the particle size of the roughened particles is 1 nanometer to 10 micrometers.

[0018] In an embodiment of the present invention, it is stipulated that in Step 04, the depth of the micro-roughened structure is 1 nanometer to 100 micrometers.

[0019] In an embodiment of the present invention, it is stipulated that the bottom of the surface layer to be processed further has a material layer;

[0020] Step 04 further includes: using the surface layer to be processed with the micro-roughened structure as a mask to continue etching the material layer at the bottom of the surface layer to be processed.

[0021] In one embodiment of the present invention, it is stipulated that after step 04, it further includes: removing the metal particles.

[0022] In one embodiment of the present invention, it is stipulated that the surface layer to be treated is the top of the light-emitting region in a micro light-emitting diode chip; the light-emitting region includes an array composed of micro light-emitting mesa surfaces.

[0023] In one embodiment of the present invention, it is stipulated that the surface layer to be treated is located on the top surface of the micro light-emitting mesa surface; or the surface layer to be treated is located on the top of the micro light-emitting mesa surface and the top between the micro light-emitting mesa surfaces;

[0024] The top of the micro light-emitting mesa surface is a semiconductor material layer, or the top of the micro light-emitting mesa surface is a dielectric layer, or the top of the micro light-emitting mesa surface is a transparent conductive layer;

[0025] The top between the micro light-emitting mesa surfaces is a dielectric layer or a transparent conductive layer.

[0026] In one embodiment of the present invention, it is stipulated that the material of the semiconductor material layer is one or more of GaN, InP, AlInP, AlGaInP, and GaP; the material of the dielectric layer is SiO 2 , SiNx, SiON, Al 2 O 3 , TiO 2 , and one or more of MgF; the transparent conductive material is one or more of ITO, AZO, and a metal layer.

[0027] An embodiment of the present invention further provides a micro light-emitting diode chip, including:

[0028] A light-emitting region; the light-emitting region includes an array composed of micro light-emitting mesa surfaces;

[0029] A micro-roughened structure, located on the top of the light-emitting region.

[0030] In one embodiment of the present invention, it is stipulated that the micro-roughened structure is located on the top surface of the micro light-emitting mesa surface; or the surface layer to be treated is located on the top of the micro light-emitting mesa surface and the top between the micro light-emitting mesa surfaces.

[0031] The top of the micro light-emitting mesa surface is a semiconductor material layer, or the top of the micro light-emitting mesa surface is a dielectric layer, or the top of the micro light-emitting mesa surface is a transparent conductive layer;

[0032] The top between the micro light-emitting mesa surfaces is a dielectric layer or a transparent conductive layer.

[0033] In one embodiment of the present invention, it is stipulated that the material of the semiconductor material layer is one or more of GaN, InP, AlInP, AlGaInP, and GaP; the material of the dielectric layer is SiO 2 , SiNx, SiON, Al 2 O 3 , TiO 2 and one or more of MgF; the transparent conductive material is one or more of ITO, AZO, and a metal layer; the generated micro-roughened structure includes a plurality of roughened particles; the particle size of the roughened particles is 1 nm to 10 um; alternatively, the depth of the micro-roughened structure is 1 nm to 100 um.

[0034] The present invention has at least the following beneficial effects: By this method, the particle size, depth, and rate of the micro-roughened structure can be controlled, and the particle size and depth of the roughening can reach to several tens of microns. Therefore, it can be well applied to the roughening of the surface of micro light-emitting diodes with small sizes and pixel sizes in the micron or sub-micron range. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] To further clarify the advantages and features of the embodiments of the present invention, more specific descriptions of the embodiments of the present invention will be presented with reference to the accompanying drawings. It can be understood that these drawings only depict typical embodiments of the present invention and will not be considered as limiting its scope. In the drawings, for clarity, the same or corresponding components will be denoted by the same or similar reference numerals.

[0036] Figure 1 FIG. shows a schematic flow chart of a method for constructing a micro-roughened structure in an embodiment of the present invention.

[0037] Figure 2A -E shows a schematic structural diagram of the construction process of a micro-roughened structure in an embodiment of the present invention.

[0038] Figure 3 FIG. shows a schematic flow chart of a method for constructing a micro-roughened structure in another embodiment of the present invention.

[0039] Figure 4A -H shows a schematic structural diagram of the construction process of a micro-roughened structure in another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0040] It should be noted that the components in the drawings may be exaggerated for illustration purposes and are not necessarily to scale. In the drawings, the same or functionally identical components are provided with the same reference numerals.

[0041] In the present invention, unless otherwise specified, the expressions "arranged on", "arranged above", and "arranged over" do not exclude the presence of intermediate elements therebetween. In addition, "arranged on or above" only represents the relative positional relationship between two components, and in certain cases, such as after reversing the product direction, it can also be converted to "arranged under or below", and vice versa.

[0042] In the present invention, each embodiment is only intended to illustrate the solution of the present invention and should not be construed as restrictive.

[0043] In the present invention, unless otherwise specified, the quantifiers "a" and "one" do not exclude the scenario of multiple elements.

[0044] It should also be noted here that in the embodiments of the present invention, for the sake of clarity and simplicity, only a part of the components or assemblies may be shown. However, those of ordinary skill in the art can understand that, under the teaching of the present invention, the required components or assemblies can be added according to the specific scenario needs. Additionally, unless otherwise stated, the features in different embodiments of the present invention can be combined with each other. For example, a certain feature in the second embodiment can be used to replace the corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment also falls within the scope of the disclosure or the scope of the record of the present application.

[0045] It should also be noted here that within the scope of the present invention, the terms "identical", "equal", "equal to", etc. do not mean that the two numerical values are absolutely equal, but allow a certain reasonable error. That is to say, the said terms also cover "substantially identical", "substantially equal", "substantially equal to". By analogy, in the present invention, the directional terms "perpendicular to", "parallel to", etc. also cover the meanings of "substantially perpendicular to" and "substantially parallel to".

[0046] In addition, the numbering of the steps of each method of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps can be executed in different orders.

[0047] The present invention will be further described below with reference to the accompanying drawings in conjunction with the specific embodiments.

[0048] Figure 1 The flowchart of a method for constructing a micro-roughened structure in an embodiment of the present invention is shown. Figures 2A - 2E The structural schematic diagram of the construction process of the micro-roughened structure in an embodiment of the present invention is shown. As Figure 1 and shown in FIG. 2, the method includes the following steps:

[0049] Step 101: Provide the surface layer 201 to be processed.

[0050] Step 102: Grow a metal layer 202 on the surface layer 201 to be processed.

[0051] Step 103: Perform high-temperature annealing on the metal layer 202 so that the metal in the metal layer agglomerates to form metal particles 203.

[0052] Step 104: Use the metal particles 203 as a mask to etch the surface layer 201 to be processed to generate a micro-roughened structure 204.

[0053] The following specifically describes each step of this embodiment.

[0054] Figure 2A The structural schematic diagram after performing step 101 is shown. In step 101, a surface layer 201 to be processed is provided. In some embodiments, the surface layer 201 to be processed may be the top of the light-emitting region in a micro light-emitting diode chip, and the light-emitting region includes an array composed of micro light-emitting mesa. In some embodiments, the surface layer 201 to be processed is located on the top surface of the micro light-emitting mesa; or the surface layer 201 to be processed is located on the top of the micro light-emitting mesa and the top between the micro light-emitting mesas. The top of the micro light-emitting mesa is a semiconductor material layer. Alternatively, the top of the micro light-emitting mesa is a dielectric layer. Alternatively, the top of the micro light-emitting mesa is a transparent conductive layer. The top between the micro light-emitting mesas is a dielectric layer or a transparent conductive layer.

[0055] In some embodiments, the material of the semiconductor material layer is one or more of GaN, InP, AlInP, AlGaInP, and GaP. The material of the dielectric layer is SiO 2 , SiNx, SiON, Al 2 O 3 , TiO 2 and one or more of MgF. The transparent conductive material is one or more of indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), and a metal layer.

[0056] Figure 2B The structural schematic diagram after performing step 102 is shown. In step 102, a metal layer 202 is grown on the surface layer 201 to be processed. Among them, vapor deposition, sputtering, atomic layer deposition, or other metal deposition methods can be used to grow the metal layer 202 on the surface layer 201 to be processed. The material can be selected from one or more of elemental metals or alloys such as Au, Ag, Cu, Al, Sn, AuGe, Ni, etc. The thickness of the generated metal layer 202 can be 1 nanometer to 10 micrometers.

[0057] Figure 2CShows a schematic structural diagram after performing step 103. In step 103, the metal layer 202 is subjected to high-temperature annealing, causing the metal in the metal layer to agglomerate to form metal particles 203. At this time, at least a part of the surface layer 201 to be processed below the metal layer 202 will be exposed. The particle size of the metal particles 203 formed by the high-temperature annealing process can be from 1 nanometer to 10 micrometers, and it can be adjusted by adjusting the process parameters of the high-temperature annealing. The process parameters of the high-temperature annealing include: the temperature is from 200°C to 500°C, the time is from 10 s to 30 min, and the atmosphere includes N 2 , Ar, O 2 and H 2 or one or more of them. In addition, although Figure 2C shows the shape and position of the metal particles 203 schematically, those skilled in the art should understand that it is only for illustration and should not be regarded as a limitation. The shape of the metal particles 203 can be any regular or irregular shape, and the spacing and arrangement between different metal particles 203 can also be arbitrary and irregular.

[0058] Figure 2D Shows a schematic structural diagram after performing step 104. In step 104, the metal particles 203 are used as a mask to etch the surface layer 201 to be processed to generate a micro-roughened structure 204. In some embodiments, ICP, ALE or RIE dry etching can be used to etch the surface layer to be processed. By adjusting the process parameters of the etching process, the etching rate can be controlled, and the particle size of the roughened particles of the micro-roughened structure and the depth of the micro-roughened structure can be adjusted. In some embodiments, the etching gas for the etching process includes: Cl 2 , BCl 3 , Ar, CF 4 , CHF 3 , SF 6 , O 2 , N 2 , HF and CH 4 or one or more of them. In some embodiments, the generated micro-roughened structure includes a plurality of roughened particles, and the particle size of the roughened particles can be from 1 nanometer to 10 micrometers. In some embodiments, the depth of the micro-roughened structure can be from 1 nanometer to 100 micrometers. In addition, although Figure 2D shows the shape and position of the roughened particles of the micro-roughened structure 204 schematically, those skilled in the art should understand that it is only for illustration and should not be regarded as a limitation. The shape of the roughened particles can be any regular or irregular shape, and the spacing and arrangement between different roughened particles can also be arbitrary and irregular, which will be affected by the etching process.

[0059] Return Figure 1, in some embodiments of the present invention, after step 104, the method for constructing the micro-roughened structure may further include step 105 of removing the metal particles 203.

[0060] Figure 2E Fig. shows the schematic structural diagram after performing step 105. In step 105, the metal particles 203 are removed.

[0061] The particle size, depth, and rate of roughening of this method are controllable, and the particle size and depth of roughening can reach a size of dozens of microns. It can be well applied to the roughening of the surface of micro light-emitting diodes with small sizes and micron- or sub-micron-sized pixel sizes.

[0062] In the above embodiment, the agglomerated metal layer is directly used as a mask, and then the surface layer to be processed is etched to generate a micro-roughened structure. In addition, in another embodiment of the present invention, a dielectric layer may also be grown on the surface layer to be processed first, and after the metal layer is agglomerated, it is used as a mask to etch the dielectric layer first, and then the etched dielectric layer is used as a mask to etch the surface layer to be processed to generate a micro-roughened structure.

[0063] Figure 3 Fig. shows the schematic flow diagram of a method for constructing a micro-roughened structure in another embodiment of the present invention. Figures 4A - 4H Fig. shows the schematic structural diagram of the construction process of the micro-roughened structure in another embodiment of the present invention. As Figure 3 shown in Fig. and Fig. 4, this method includes the following steps:

[0064] Step 301: Provide a surface layer 201 to be processed.

[0065] Step 302: Grow a dielectric layer 401 on the surface layer 201 to be processed.

[0066] Step 303: Grow a metal layer 202 on the dielectric layer 401.

[0067] Step 304: Perform high-temperature annealing on the metal layer 202 so that the metal in the metal layer agglomerates to form metal particles 203.

[0068] Step 305: Use the metal particles 203 as a mask to etch the dielectric layer 401 to generate an etched dielectric layer 402.

[0069] Step 306: Remove the metal particles 203.

[0070] Step 307: Use the etched dielectric layer 402 as a mask to etch the surface layer 201 to be processed to generate a micro-roughened structure 204.

[0071] Step 308, remove the etched dielectric layer 402.

[0072] The following specifically describes each step of this embodiment.

[0073] Figure 4A The structural schematic diagram after performing step 301 is shown. In step 301, a surface layer 201 to be processed is provided. In some embodiments, the surface layer 201 to be processed may be the top of the light-emitting region in a micro light-emitting diode chip, and the light-emitting region includes an array composed of micro light-emitting mesa. In some embodiments, the surface layer 201 to be processed is located on the top surface of the micro light-emitting mesa; or the surface layer 201 to be processed is located on the top of the micro light-emitting mesa and the top between the micro light-emitting mesas. The top of the micro light-emitting mesa is a semiconductor material layer. Alternatively, the top of the micro light-emitting mesa is a dielectric layer. Alternatively, the top of the micro light-emitting mesa is a transparent conductive layer. The top between the micro light-emitting mesas is a dielectric layer or a transparent conductive layer.

[0074] In some embodiments, the material of the semiconductor material layer is one or more of GaN, InP, AlInP, AlGaInP, and GaP. The material of the dielectric layer is SiO 2 , SiNx, SiON, Al 2 O 3 , TiO 2 , and MgF. The transparent conductive material is one or more of indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), and a metal layer.

[0075] Figure 4B The structural schematic diagram after performing step 302 is shown. In step 302, a dielectric layer 401 is grown on the surface layer 201 to be processed, and the dielectric layer 401 can be grown on the surface layer 201 to be processed by physical vapor deposition, chemical vapor deposition, or other methods. The material of the dielectric layer includes SiO 2 , SiNx, SiON, and TiO 2 . In some embodiments, the dielectric layer 401 may also be a transparent conductive layer such as ITO or AZO.

[0076] Figure 4C The structural schematic diagram after performing step 303 is shown. In step 303, a metal layer 202 is grown on the dielectric layer 401. A metal deposition method such as evaporation, sputtering, atomic layer deposition, or other methods can be used to grow the metal layer 202 on the dielectric layer 401. The material can be selected from one or more of elemental metals or alloys such as Au, Ag, Cu, Al, Sn, AuGe, and Ni. The thickness of the generated metal layer 202 can be 1 nanometer to 10 micrometers.

[0077] Figure 4D shows a schematic structural diagram after performing step 304. In step 304, the metal layer 202 is subjected to high-temperature annealing, causing the metal in the metal layer to agglomerate to form metal particles 203. At this time, at least a part of the dielectric layer 401 below the metal layer 202 will be exposed. The particle size of the metal particles 203 formed by the high-temperature annealing process is 1 nanometer to 10 micrometers, and it can be adjusted by adjusting the process parameters of the high-temperature annealing. The process parameters of the high-temperature annealing include: the temperature is 200°C to 500°C, the time is 10 s to 30 min, and the atmosphere includes N 2 , Ar, O 2 and H 2 or one or more of them. In addition, although Figure 4D shows the shape and position of the metal particles 203 schematically, those skilled in the art should understand that it is only for illustration and should not be regarded as a limitation. The shape of the metal particles 203 can be any regular or irregular shape, and the spacing and arrangement between different metal particles 203 can also be arbitrary and irregular.

[0078] Figure 4E shows a schematic structural diagram after performing step 305. In step 305, the metal particles 203 are used as a mask to etch the dielectric layer 401 to generate an etched dielectric layer 402. At this time, at least a part of the surface layer 201 to be processed below the dielectric layer 401 will be exposed. In some embodiments, ICP, ALE or RIE dry etching can be used to etch the dielectric layer 401. By adjusting the process parameters of the etching process, the etching rate can be controlled, and the particle size of the roughening particles of the micro-roughened structure and the depth of the micro-roughened structure can be adjusted. In some embodiments, the etching gas for the etching process includes: Cl 2 , BCl 3 , Ar, CF 4 , CHF 3 , SF 6 , O 2 , N 2 , HF and CH 4 or one or more of them. In some embodiments, the generated micro-roughened structure includes a plurality of roughening particles, and the particle size of the roughening particles can be 1 nanometer to 10 micrometers. In some embodiments, the depth of the micro-roughened structure can be 1 nanometer to 100 micrometers. In addition, although Figure 4E shows the structure and shape of the etched dielectric layer 402 schematically, those skilled in the art should understand that it is only for illustration and should not be regarded as a limitation. The shape and structure of the etched dielectric layer 402 can be any regular or irregular shape and structure, which will be affected by the etching process.

[0079] Figure 4F The structural schematic diagram after performing step 306 is shown. In step 306, the metal particles 203 are removed.

[0080] Figure 4G The structural schematic diagram after performing step 307 is shown. In step 307, the etched dielectric layer 402 is used as a mask to etch the surface layer to be processed 201 to generate a micro-roughened structure 204. In some embodiments, ICP, ALE or RIE dry etching can be used to etch the surface layer to be processed. By adjusting the process parameters of the etching process, the etching rate can be controlled, and the particle size of the roughening particles of the micro-roughened structure and the depth of the micro-roughened structure can be adjusted. The etching gas of the etching process includes: Cl 2 , BCl 3 , Ar, CF 4 , CHF 3 , SF 6 , O 2 , N 2 , HF and CH 4 of one or more. In some embodiments, the generated micro-roughened structure includes a plurality of roughening particles, and the particle size of the roughening particles can be from 1 nanometer to 10 micrometers. In some embodiments, the depth of the micro-roughened structure can be from 1 nanometer to 100 micrometers. In addition, although Figure 4F shows the shape and position of the roughening particles of the micro-roughened structure 204, those skilled in the art should understand that it is only for illustration and should not be used as a limitation. The shape of the roughening particles can be any regular or irregular shape, and the spacing and arrangement between different roughening particles can also be arbitrary and irregular, which will be affected by the etching process.

[0081] Figure 4H The structural schematic diagram after performing step 308 is shown. Step 308: Remove the etched dielectric layer 402, and the method for removing the etched dielectric layer 402 includes: dry etching or wet etching.

[0082] In this embodiment, first, the metal layer is agglomerated and used as a mask to etch the dielectric layer, and then the etched dielectric layer is used as a mask to etch the surface layer to be processed to generate a micro-roughened structure.

[0083] In an embodiment of the present invention, a micro-roughened structure is further proposed, which is constructed according to the above method.

[0084] In one embodiment of the present invention, a micro light emitting diode (Micro-LED) is further proposed, which includes an epitaxial surface and a surface light emitting layer, wherein at least one of the epitaxial surface and the surface light emitting layer has a micro-roughened structure constructed according to the method. This Micro-LED can be used in a Micro-LED array of a Micro-LED chip.

[0085] The micro light emitting diode chip includes an integrated circuit (IC) backplane and an active region disposed on the integrated circuit backplane. The active region includes a pixel array formed by micro light emitting diodes, and the pixel array includes a plurality of micro light emitting diode pixels. Each pixel may include one or more micro light emitting diodes. That is, each micro light emitting diode can form at least a part of the pixel elements on the micro light emitting diode chip. For example, each pixel may include a micro light emitting diode of one color, whereby the active region of the micro light emitting diode chip is a monochromatic pixel array. Or, each pixel may include two or more colors of micro light emitting diodes, whereby the active region of the micro light emitting diode chip is a color pixel array.

[0086] In some embodiments, the IC backplane can be electrically connected to each micro light emitting diode in the micro light emitting diode array through separate metal interconnections. In some embodiments, each micro light emitting diode can be individually electrically controlled by the IC backplane. In some embodiments, the IC backplane can be electrically connected to the electrodes of the micro light emitting diode chip through metal interconnections. In some embodiments, a dielectric layer can be formed in the gaps between the micro light emitting diodes. In some embodiments, the dielectric layer can also be formed in the gaps between the interconnections.

[0087] In some embodiments, the IC backplane is provided with a driving circuit array. Each driving circuit is a pixel driver. In some cases, the driving circuit is a thin film transistor pixel driver or a silicon CMOS pixel driver. The driving circuit forms a separate pixel driver to control the operation of a separate multi-color Micro-LED pixel.

[0088] The micro light emitting diode chip includes a plurality of micro light emitting diode arrays, and each micro light emitting diode array includes a plurality of micro light emitting diodes. The driving mode of the micro light emitting diodes is, for example, passive matrix (PM) driving, wherein the cathodes of all the micro light emitting diodes in each array are commonly connected to a cathode line NL, and the micro light emitting diodes with the same number in each array are respectively connected to corresponding anode lines PL. Thus, the on / off and light emission brightness of each light emitting diode can be individually controlled by controlling the signals on the corresponding cathode line and anode line.

[0089] In some embodiments, each micro - light - emitting diode in the micro - light - emitting diode array may include a micron - scale light - emitting mesa structure. In some embodiments, the micron - scale light - emitting mesa structure may include, from bottom to top, a first - type epitaxial layer (or the first epitaxial layer), a light - emitting layer, and a second - type epitaxial layer (or the second epitaxial layer). That is to say, in the three - layer structure, the first - type epitaxial layer is closest to the IC backplane; the light - emitting layer is located above the first - type epitaxial layer and is farther from the IC backplane; the second - type epitaxial layer is located above the light - emitting layer and is the farthest from the IC backplane. In some embodiments, the light - emitting layer is formed by a plurality of stacked quantum well layers, especially superlattice - stacked quantum well layers. Preferably, the superlattice - stacked quantum well layers include multiple pairs of quantum well layers stacked with quantum barrier layers. In one embodiment of the present invention, the quantum well layer is an InGaN / GaN multiple quantum well layer or an InGaN / AlGaN multiple quantum well layer or an InGaAs / AlGaAs multiple quantum well layer. In one embodiment of the present invention, the light - emitting layer further includes an electron - blocking layer, and the electron - blocking layer is disposed on a first side of the light - emitting layer, and the first side refers to the side along which electrons migrate out of the light - emitting layer.

[0090] In some embodiments, the first - type epitaxial layer is a semiconductor material of a first conductivity type and includes a plurality of semiconductor layers. The main matrix material of the first - type epitaxial layer may be, but is not limited to, composed of materials such as Ga, N, As, P, In, or Al, etc. In addition, the first - type epitaxial layer may include, from top to bottom, but is not limited to, a waveguide layer, a confinement layer, a transition layer, and a window layer; in addition, an ohmic contact layer may be formed below the window layer. In some embodiments, the second - type epitaxial layer is a semiconductor material of a second conductivity type and includes a plurality of semiconductor layers. The main matrix material of the second - type epitaxial layer may be, but is not limited to, composed of materials such as Ga, N, As, P, In, or Al, etc. In addition, the first - type epitaxial layer may include, from top to bottom, but is not limited to, a confinement layer and a waveguide layer; in addition, in some embodiments, an ohmic contact layer may be formed on the confinement layer. In one embodiment of the present invention, the first - type epitaxial layer is an N - type GaN layer or an N - type AlGaN layer, and the second - type epitaxial layer is a P - type GaN layer or a P - type AlGaN layer. In another embodiment of the present invention, the first - type epitaxial layer may also be a P - type GaN layer or a P - type AlGaN layer, and the second - type epitaxial layer is an N - type GaN layer or an N - type AlGaN layer. In the embodiments of the present invention, the semiconductor light - emitting mesa 501 is in a stepped or trapezoidal shape. In some embodiments, the micron - scale light - emitting mesa structure can emit red light, blue light, green light, or any other color of light.

[0091] In some embodiments, a top conductive layer may be formed on the top surface of the micro - light - emitting diode array. In some embodiments, the top conductive layer may be shared by all the micro - light - emitting diodes in the micro - light - emitting diode array.

[0092] In one embodiment of the present invention, the top conductive layer can be shared by all the micro light-emitting diodes in the micro light-emitting diode array. In one embodiment of the present invention, the top conductive layer is disposed above the micro light-emitting diode array and contacts and covers the top of each light-emitting mesa, and is in electrical contact with the second epitaxial layer of the light-emitting mesa, so as to connect the second epitaxial layers of the respective semiconductor light-emitting mesas 1 in series, and it is a transparent conductive layer.

[0093] In one embodiment of the present invention, the micro light-emitting diode array further includes a passivation isolation layer. The passivation isolation layer covers the surface and the side surface of the light-emitting mesa, but exposes at least a part of the surface of the second epitaxial layer, and the top conductive layer is disposed on the surface of the passivation isolation layer. In one embodiment of the present invention, the passivation isolation layer can be formed by CVD depositing SiO 2 or ALD depositing Al 2 O 3 film to effectively reduce the chip leakage rate. In some embodiments of the present invention, the passivation isolation layer only covers the side surface of the light-emitting mesa, but does not cover the top surface of the light-emitting mesa, and the highest point of the passivation isolation layer is flush with the top surface of the light-emitting mesa. In these embodiments, the continuous top conductive layer covering the top of the light-emitting mesa is in a horizontal or substantially horizontal planar shape. In some embodiments of the present invention, the passivation isolation layer not only covers the side surface of the light-emitting mesa, but also covers the edge part of the top surface of the light-emitting mesa, and thus there is a protrusion at the top edge of the light-emitting mesa, and then the continuous top conductive layer covering it also forms a protrusion at the top edge of the light-emitting mesa.

[0094] As described above, there are partitions between the pixel points formed by each light-emitting mesa. A second electrode is provided at the partition, and the second electrode is disposed on the surface of the top conductive layer. In an embodiment of the present invention, the second electrode is an annular reflective electrode, which is arranged around the light-emitting mesa, and is formed by magnetron sputtering or evaporation. For example, its material can be made of Al or Al alloy metal as the sidewall reflective mirror surface, and the electrode stack metal can be metal materials such as Ni, Al, Ti, Ni, Pt, Au, etc. In an embodiment of the present invention, the second electrodes are interconnected. In some embodiments of the present invention, deep trenches are provided at the partitions between adjacent light-emitting mesas. The deep trenches penetrate through the micro light-emitting diode array, and the second electrode is disposed at the deep trenches. In some embodiments of the present invention, no deep trenches are provided at the partitions between adjacent light-emitting mesas, but a passivation isolation layer and a top conductive layer are directly formed. Therefore, the surface of the top conductive layer between adjacent light-emitting mesas is a horizontal or substantially horizontal plane. The second electrode is formed here, and its morphological interface is trapezoidal or approximately trapezoidal, and the surface of the second electrode is not higher than the highest point of the continuous top conductive layer.

[0095] In an embodiment of the present invention, the micro light-emitting diode array is bonded to the driving backplane through a metal bonding layer and is electrically connected to the IC copper pillars on the driving backplane. In an embodiment of the present invention, the IC copper pillars include first IC copper pillars and second IC copper pillars, wherein the first IC copper pillars are electrically connected to the first epitaxial layer of the semiconductor light-emitting module one by one. The second IC copper pillars are electrically connected to the first electrode 6. In an embodiment of the present invention, the polarity of the first electrode is opposite to that of the second electrode. In an embodiment of the present invention, each semiconductor light-emitting module has a common first electrode. The first electrode can be, for example, a P electrode or an anode electrode, and the second electrode is an electrode with a polarity opposite to that of the first electrode 506, such as an N electrode or a cathode electrode. In an embodiment of the present invention, the first and second electrodes and their connecting components can be made of materials such as graphene, ITO, aluminum-doped zinc oxide (AZO), or fluorine-doped tin oxide (FTO) or any combination of the above materials. In another embodiment of the present invention, the first and second electrodes and their connecting components can be made of non-transparent or transparent conductive materials, such as indium tin oxide (ITO).

[0096] In some embodiments, the light-emitting layer may include at least one quantum well layer. In some embodiments, the micro light-emitting diode array may include a single-layer micro light-emitting diode structure. In some embodiments, the micro light-emitting diode array may include a multi-layer vertically stacked micro light-emitting diode structure.

[0097] In some embodiments, the micro light-emitting diode array may include micro light-emitting diodes of one or more colors. In some embodiments, the pitch of the micro light-emitting diode array, i.e., the minimum center-to-center distance between the micro light-emitting diodes, may be between about 2 micrometers and about 50 micrometers. In some embodiments, the number of pixels on the micro light-emitting diode chip may be between several thousand and several million.

[0098] In some embodiments, a microlens is disposed above the micro light-emitting diode array, and the lateral dimension of the bottom of the microlens is larger than the lateral dimension of the light-emitting region of the micro light-emitting diode, or the lateral dimension of the bottom of the microlens may be smaller than or equal to the lateral dimension of the light-emitting region of the micro light-emitting diode.

[0099] In some embodiments, one microlens may cover one or more micro light-emitting diodes without a lens. A plurality of microlenses constitute a microlens array. The microlenses in the microlens array are generally the same. Examples of microlenses include spherical microlenses, aspherical microlenses, Fresnal microlenses, and cylindrical microlenses. Each microlens in the microlens array of the micro light-emitting diode chip 102 may be the same or different in terms of shape, curvature, optical power, size, base, spacing, etc.

[0100] In some embodiments, the microlens may be made of various materials that are transparent to the light of each wavelength emitted by the micro light-emitting diode. Exemplary transparent materials for the microlens include polymers and dielectric materials. In some embodiments, the dielectric material includes one or more materials, such as silicon oxide, silicon nitride, silicon carbide, titanium oxide, zirconium oxide, aluminum oxide, etc. In some embodiments, the microlens is made of a photoresist. In some embodiments, the microlens is directly deposited on the surface of the micro light-emitting diode by chemical vapor deposition (CVD) technology.

[0101] Although the embodiments of the present invention have been described above, it should be understood that they are presented only as examples and not as limitations. It will be apparent to those skilled in the relevant art that various combinations, variations, and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the width and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined only by the appended claims and their equivalents.

Claims

1. A method for constructing a micro-coarsening structure, comprising the following steps: Step 01: Provide the surface layer to be processed; Step 02: growing a metal layer on the surface layer to be processed; Step 03: performing high temperature annealing on the metal layer to aggregate the metal layer to form metal particles; Step 04: Using the metal particles as a mask, etching the surface layer to be processed to generate a micro-roughened structure.

2. The method for constructing a micro-roughened structure according to claim 1, characterized in that: In step 02, the thickness of the metal layer is 1 nanometer to 10 micrometers.

3. The method for constructing a micro-roughened structure according to claim 1, characterized in that: The material of the metal layer is one or more of Au, Ag, Cu, Al, Sn, AuGe and Ni.

4. The method for constructing a micro-roughened structure according to claim 1, characterized in that: In step 03, the process parameters of the high temperature annealing include: a temperature of 200° C. to 500° C., a time of 10 s to 30 min, and an atmosphere including one or more of N 2 , Ar, O 2 and H 2 .

5. The method for constructing a micro-roughened structure according to claim 1, characterized in that: In step 04, the etching gas used for etching includes: one or more of Cl2, BCl3, Ar, CF4, CHF3, SF6, O2, N2, HF and CH4.

6. The method for constructing a micro-roughened structure according to claim 1, characterized in that: The etching process used is: ICP, ALE or RIE dry etching.

7. The method for constructing a micro-roughened structure according to claim 1, characterized in that: The particle size of the metal particles is 1 nanometer to 10 micrometers.

8. The method for constructing a micro-roughened structure according to claim 1, characterized in that: In step 04, the generated micro-roughened structure includes a plurality of roughened particles; the particle size of the roughened particles is 1 nanometer to 10 micrometers.

9. The method for constructing a micro-roughened structure according to claim 1, characterized in that: In step 04, the depth of the micro-roughened structure is 1 nanometer to 100 micrometers.

10. The method for constructing a micro-roughened structure according to claim 1, characterized in that: The bottom of the surface layer to be processed also has a material layer; Step 04 also includes: using the surface layer to be processed with the micro-roughened structure as a mask, continuing to etch the material layer at the bottom of the surface layer to be processed.

11. The method for constructing a micro-roughened structure according to claim 1, characterized in that: After step 04, the method further includes: removing the metal particles.

12. The method for constructing a micro-roughened structure according to claim 1, characterized in that: The surface layer to be processed is the top of the light-emitting area in the micro-light-emitting diode chip; the light-emitting area includes an array composed of micro-light-emitting mesas.

13. The method for constructing a micro-roughened structure according to claim 12, characterized in that: The surface layer to be processed is located on the top surface of the micro-light-emitting mesas; or the surface layer to be processed is located on the top of the micro-light-emitting mesas and the top between the micro-light-emitting mesas; The top of the micro-light-emitting mesa is a semiconductor material layer, or the top of the micro-light-emitting mesa is a dielectric layer, or the top of the micro-light-emitting mesa is a transparent conductive layer; The top between the micro light-emitting mesas is a dielectric layer or a transparent conductive layer.

14. The method for constructing a micro-roughened structure according to claim 13, characterized in that: The material of the semiconductor material layer is one or more of GaN, InP, AlInP, AlGaInP and GaP; the material of the dielectric layer is one or more of SiO2, SiNx, SiON, Al2O3, TiO2 and MgF; the transparent conductive material is one or more of ITO, AZO and a metal layer.

15. A micro light emitting diode chip, characterized in that: include: Luminous area; The light-emitting area includes an array of micro-light-emitting mesas; The micro-roughened structure is located on the top of the light emitting region.

16. The micro light emitting diode chip according to claim 15, characterized in that: The micro-roughened structure is located on the top surface of the micro-light-emitting mesas; or the surface layer to be processed is located on the top of the micro-light-emitting mesas and the top between the micro-light-emitting mesas. The top of the micro-light-emitting mesa is a semiconductor material layer, or the top of the micro-light-emitting mesa is a dielectric layer, or the top of the micro-light-emitting mesa is a transparent conductive layer; The top between the micro light-emitting mesas is a dielectric layer or a transparent conductive layer.

17. The method for constructing a micro-roughened structure according to claim 16, characterized in that: The material of the semiconductor material layer is one or more of GaN, InP, AlInP, AlGaInP and GaP; the material of the dielectric layer is one or more of SiO2, SiNx, SiON, Al2O3, TiO2 and MgF; the transparent conductive material is one or more of ITO, AZO and a metal layer; the generated micro-roughened structure includes a plurality of roughened particles; the particle size of the roughened particles is 1 nanometer to 10 micrometers; or, the depth of the micro-roughened structure is 1 nanometer to 100 micrometers.

Images