Multi-process substrate processing for enhanced substrate doping

Abstract

A method of doping a substrate may include exposing a substrate surface of a semiconductor substrate to plasma cleaning; performing deposition of a dopant layer on the substrate surface using a plasma source after the plasma cleaning, the dopant layer comprising a dopant element; and exposing the substrate to an implant process while the dopant layer is disposed on the surface of the substrate, where the implant process introduces an ionic species comprising a dopant element into the substrate, where the substrate is maintained under vacuum for a process duration across the plasma cleaning, deposition of the dopant layer, and the implant process, and wherein at least a portion of the dopant layer is implanted into the substrate during an implantation process.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of priority based on U.S. Patent Application No. 17 / 980,900, filed on November 4, 2022. The disclosure of the prior application is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to methods of doping a substrate, and more particularly, to methods of performing three - dimensional doping. Background Art

[0004] As semiconductor devices, such as logic devices and memory devices, continue to scale down to smaller dimensions, it is becoming increasingly problematic to fabricate semiconductor devices using traditional processes and materials. In one example, new methods for doping semiconductor structures are being investigated to replace ion implantation. For example, in future generations of technology, transistors may be formed from three - dimensional structures such as a gate all - around structure (HGAA) where an active region is formed using so - called nanowires. Doping of such advanced devices may require ion implantation in which dopant ions are introduced into a substrate, followed by annealing to activate the dopants. Among various challenges, there is a particular need to achieve very high dopant activation while maintaining a shallow junction depth of the dopants compatible with the dimensions of advanced devices.

[0005] In view of these and other considerations, the present disclosure has been provided. Summary of the Invention

[0006] This Summary of the Invention is provided to introduce a series of concepts in a simplified form that are further described below in the Detailed Description. This Summary of the Invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to help determine the scope of the claimed subject matter.

[0007] In one embodiment, a method of doping a substrate may include: exposing a substrate surface of a semiconductor substrate to plasma cleaning; and after plasma cleaning, performing deposition of a dopant layer on the substrate surface using a plasma source, wherein the dopant layer comprises a dopant element. The method may include: exposing the substrate to an implantation process when the dopant layer is disposed on the substrate surface, wherein the implantation process introduces an ion species comprising the dopant element into the substrate. The semiconductor substrate may be maintained under vacuum during a process duration spanning plasma cleaning, deposition of the dopant layer, and the implantation process, wherein at least a portion of the dopant layer is implanted into the substrate during the implantation process.

[0008] In another embodiment, a method of doping a substrate may include: disposing a single-crystalline semiconductor material on a surface of the substrate; and exposing the surface of the substrate to plasma cleaning, wherein a native oxide is removed from the surface of the substrate. The method may include: performing deposition of a dopant layer containing a dopant element on the substrate surface using a plasma source after the plasma cleaning. The method may also include: exposing the substrate to an implantation process when the dopant layer is disposed on the surface of the substrate, wherein the implantation process introduces an ion species containing the dopant element into the substrate. The substrate may be maintained under vacuum during a process duration spanning the plasma cleaning, the deposition of the dopant layer, and the implantation process, wherein at least a portion of the dopant layer is implanted into the substrate during the implantation process.

[0009] In yet another embodiment, a method of doping a semiconductor substrate may include: disposing the semiconductor substrate in a beam-line ion implanter; and exposing the surface of the semiconductor to plasma cleaning. The method may include performing deposition of a dopant layer containing a dopant element on the substrate surface using a plasma source after the plasma cleaning. The method may include: exposing the semiconductor substrate to an implantation process when the dopant layer is disposed on the substrate surface, wherein the implantation process introduces an ion species containing the dopant element into the semiconductor substrate. The semiconductor substrate may be maintained in the beam-line ion implanter under vacuum during a process duration spanning the plasma cleaning, the deposition of the dopant layer, and the implantation process, wherein at least a portion of the dopant layer is driven into the semiconductor substrate during the implantation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A-1E Illustrates exemplary operations involved in doping a substrate according to embodiments of the present disclosure.

[0011] Figure 2A-2B Illustrates exemplary dopant profiles for boron and phosphorus, respectively, for a substrate processed according to embodiments of the present disclosure.

[0012] Figure 3 Illustrates an exemplary ion implanter according to some embodiments of the present disclosure.

[0013] Figure 4 Illustrates an exemplary process flow. DETAILED DESCRIPTION

[0014] The present embodiment will now be described more fully hereinafter with reference to the accompanying drawings, in which some embodiments are shown. The subject matter of the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the subject matter to those skilled in the art. In all the drawings, the same reference numerals refer to the same elements.

[0015] In embodiments of the present disclosure, the inventors have discovered novel ways to facilitate improved doping of semiconductor structures (such as single-crystalline semiconductor materials). In various non-limiting embodiments, suitable semiconductor structures include silicon, silicon-germanium alloy (SiGe), or silicon-phosphorus alloy.

[0016] Figure 1A-1E An exemplary operation involved in doping a substrate according to an embodiment of the present disclosure is shown. Specifically turning to Figure 1A , a first example is shown in which a semiconductor substrate 100 is provided in an ion implantation device 102 or system. In some non-limiting embodiments, the ion implantation device 102 may represent a beam-line ion implanter or other device suitable for performing ion implantation. The ion implantation device 102 may include one or more chambers or locations for accommodating the semiconductor substrate 100 during various processes to be performed.

[0017] Although the semiconductor substrate 100 is located within the ion implantation device 102, it is understood that high vacuum conditions are maintained. For example, during ion implantation of the semiconductor substrate 100, a vacuum level of less than 10-3 Torr may be maintained in the end station that accommodates the semiconductor substrate 100. According to non-limiting embodiments of the present disclosure, during other processing operations (such as plasma-based operations), a vacuum level of less than 10-1 Torr may be maintained, while during idle periods, a vacuum level of less than 10-4 Torr may be maintained. Additionally, during the Figure 1A - Figure 1E operations shown, exposure to ambient gaseous species external to the ion implantation device 102 may be excluded.

[0018] At the stage shown in Figure 1A , the semiconductor substrate 100 may be placed into the ion implantation device after having been processed through a plurality of operations to synthesize a device (such as a logic device, a memory device, or other devices that undergo implantation processing for doping purposes). In the example shown, the semiconductor substrate 100 includes a substrate base 104 formed of a single-crystalline semiconductor material. In some embodiments, the semiconductor substrate 100 may also include a native oxide layer 106 disposed on the surface 105. As Figure 1AAs shown, according to various embodiments of the present disclosure, the substrate pedestal 104 and the native oxide layer 106 may represent any suitable portion of a semiconductor substrate, including a patterned region of a semiconductor device, such as a source / drain region. The native oxide layer 106 may represent a layer formed after processing to remove any other material from the surface of the substrate pedestal 104. Formation of a native oxide on silicon and similar semiconductors is well known in the art and will not be discussed in detail herein. However, even when single-crystalline silicon is processed to remove any oxide or other non-silicon material from its outer surface, a native oxide may tend to form when exposed to an oxygen-containing (including water vapor) atmosphere, such as the environment outside a vacuum processing tool. Additionally, native oxides tend to be self-limiting in thickness, such that in some non-limiting embodiments, the thickness of the native oxide layer 106 may be assumed to not exceed 4 nanometers to 8 nanometers.

[0019] Turning to Figure 1B , a subsequent example is shown in which the surface 105 of the semiconductor substrate 100 is exposed to a plasma cleaning operation. Initially, the surface 105 may be covered by a native oxide (represented by the native oxide layer 106) up to several nanometers thick. In some embodiments, the plasma cleaning operation may employ a plasma source 110 located in an ion implantation device 102. The plasma source 110 may represent any suitable device for generating a plasma and, in some examples, may represent a radical source. In any case, the plasma source 110 may generate cleaning species 108, which may represent a combination of ions and neutrals, including radicals.

[0020] In the case where the cleaning species 108 includes ions, during the plasma cleaning operation, the energy of the ions may be maintained below 100 electron volts, such as in the range of several electron volts to 30 electron volts in some non-limiting embodiments. In some embodiments, the cleaning species 108 may represent known reactive species that tend to undergo chemical reactions to etch the native oxide layer 106 (even when the energy of such reactive species is on the order of several electron volts). In various embodiments, the cleaning species 108 may selectively etch the native oxide layer 106 relative to the substrate pedestal 104. As such, due to the low energy of the cleaning species 108, the native oxide layer 106 may be removed from the substrate pedestal 104 with little or no etching of the substrate pedestal 104 and little or no damage to the substrate pedestal 104.

[0021] According to some embodiments, Figure 1B the illustrated plasma cleaning operation may be achieved by generating hydrogen species in the plasma chamber of the plasma source 110 and directing the hydrogen species to the surface 105 when the substrate is at a cleaning temperature between room temperature and 100 degrees Celsius. The hydrogen species may be provided to the plasma chamber, for example, by supplying H 2produced by a gas. In this way, surface 105 can represent a "clean" semiconductor surface that presents silicon species to the environment within ion implantation device 102 and has minimal or no foreign species, such as oxygen or carbon, on surface 105.

[0022] In some embodiments, the plasma cleaning operation can involve multiple sub-operations. For example, a first plasma cleaning sub-operation can be carried out by generating a cleaning species from a plasma source, and the cleaning species reacts to remove part or all of the native oxide layer 106. For example, such a cleaning species can be a species different from hydrogen. Then, a second plasma cleaning sub-operation can involve generating a hydrogen plasma and directing hydrogen species to surface 105 to remove any residual oxides, carbon, or other contaminants and perform a final treatment of surface 105 with hydrogen passivation. In other instances, only hydrogen species can be used to carry out native oxide removal and hydrogen final treatment. In any case, the plasma cleaning operation can be completed by generating a hydrogen plasma and directing hydrogen species to surface 105 to form hydrogen passivation on surface 105. In other words, Figure 1B the illustrated plasma cleaning operation can be considered to involve a sub-operation of native oxide removal that occurs prior to the hydrogen final treatment of surface 105. Similarly, in some embodiments, "cleaning species" 108 can represent more than one species, such as a separate non-hydrogen species used to etch the native oxide layer 106 and a hydrogen species that hydrogen passivates surface 105 after the native oxide layer 106 has been removed.

[0023] Now turning to Figure 1C illustrates Figure 1B an example after the illustrated example, in which a dopant layer 116 is deposited on surface 105 of semiconductor substrate 100. The deposition can be carried out by plasma source 114 located within ion implantation device 102. In some embodiments, plasma source 114 may or may not be the same source as plasma source 110. The deposition of dopant layer 116 can be carried out by generating dopant species that contain a dopant element. According to some non-limiting embodiments, dopant species 112 can be ions or radicals and can be directed to surface 105 when semiconductor substrate 100 is at a substrate temperature between room temperature and -100 degrees Celsius. Dopant species 112 can be formed by providing a precursor gas to plasma source 110, and the precursor gas is a boron-containing species or a phosphorus-containing species, such as B 2 F 6 such as BF 3 or PF 3, the gas is ionized and decomposed to form an active species represented by dopant species 112. When condensation occurs to form dopant layer 116, dopant species 112 can further decompose to predominantly leave a dopant element (such as boron or phosphorus) to form dopant layer 116.

[0024] In various non-limiting embodiments of the present disclosure, dopant species 112 can be provided to surface 105 with an energy that can vary from several electron volts to 100 electron volts. In this way, the energy of dopant species 112 can be such that little sputtering occurs during the deposition of dopant species 112 and little damage is caused to regions at or near surface 105, including implantation of dopant species 112 and related collision cascades within substrate pedestal 104.

[0025] According to various embodiments, after deposition is complete, dopant layer 116 can have a thickness in the range of between 1 nanometer and 7 nanometers at the processing stage shown in Figure 1C . As discussed further below, this thickness can be customized according to various considerations, including the target dopant concentration in substrate pedestal 104 near surface 105, the target contact resistance of the device to be formed, the target junction depth of the source / drain junction to be formed, and other factors.

[0026] Now turning to Figure 1D , a subsequent example is shown, in which case when the dopant layer is disposed in ion implantation device 102, the semiconductor substrate 100 is exposed to an implantation process on surface 105 when the dopant layer is disposed on the substrate surface. In this way, the implantation process introduces ion species 118 containing a dopant element into semiconductor substrate 100, specifically into substrate pedestal 104. Note that, for example, ion species 118 can be provided as an ion beam in a beam line ion implanter. In some instances, ion species 118 can be provided as an analyzed ion beam containing the same dopant element as the dopant element of dopant layer 116. The analyzed ion beam can thus have a well-defined ion energy and composition of ion species 118.

[0027] In various non-limiting embodiments, depending on the material of ion species 118 and the thickness of dopant layer 116, ion species 118 can have an ion energy between 500 electron volts and 7 kiloelectron volts. This process is generally shown in Figure 1E and represents Figure 1DAn example after the example. In this example, most or all of the dopant layer 116 may not be present on the surface 105. Additionally, a doped layer 120 has been formed within the substrate pedestal 104. For example, the doped layer 120 can be formed by directly implanting the ion species 118 into the substrate pedestal 104 and driving dopant material from the dopant layer 116 into the substrate pedestal as a result of the impact collisions from the ion species 118. In other words, the implantation range of the ion species 118 can be greater than the thickness of the dopant layer 116 prior to the implantation process, such that at least some ions of the ion species 118 are directly implanted into the substrate pedestal 104. In this way, the doped layer 120 can represent a mixture of dopants from the dopant layer 116 and dopants from the ion species 118.

[0028] Note that, according to various embodiments, the operations of Figure 1B-1E can be repeated in a cyclic manner to achieve a target dopant dose within the substrate. In other words, plasma cleaning, deposition of the dopant layer, and the implantation process can be carried out as an implantation cycle, where the implantation cycle is repeated one or more times to implant the target dopant level into the substrate.

[0029] Turning to Figure 2A , which shows an experimental example of the dopant distribution of a semiconductor substrate processed according to an embodiment of the present disclosure, and specifically according to the Figure 1A-1E operations. Figure 2A A graph is presented showing the variation of boron concentration with depth in a silicon substrate. As described above, the silicon substrate has been processed, where plasma cleaning, boron deposition, and the implantation process have been sequentially carried out on the silicon substrate to introduce boron into the silicon substrate. Figure 2A A series of curves are shown using three different thicknesses of the dopant layer 116 (2 nanometers, 3 nanometers, and 4 nanometers), followed by ion implantation at 3 keV BF 2 and an ion dose of 5E15 / cm² and activation annealing at 1000 degrees Celsius. Figure 2A Also shown is a control curve of the boron dopant distribution of an ion implantation process carried out at 3 keV BF 2 and an ion dose of 5E15 / cm² without any dopant layer, followed by activation annealing at 1000 degrees Celsius. Note that in Figure 2AIn this case, the outer surface of the silicon substrate is represented by a depth of 0 along the X-axis. As shown in the figure, the boron concentration at a depth of 1 nanometer to 3 nanometers below the outer surface is very high, ranging from approximately 5E21 / cubic centimeter to 5E22 / cubic centimeter. In addition, within the thickness range of the dopant layer 116 shown, the boron concentration near the substrate surface increases as the thickness increases, specifically between a thickness of 2 nanometers and a thickness of 3 nanometers. In contrast, the boron concentration near the substrate surface of the control sample is relatively low, not exceeding 5E21 / cubic centimeter. Additionally, compared with the implanted sample without the dopant layer 116, the junction depth in the sample with the dopant layer 116 is shallower. Furthermore, the junction depth decreases as the dopant layer thickness increases to at least 4 nanometers.

[0030] Figure 2B Shows the dopant distribution for boron doping of a substrate processed according to an embodiment of the present disclosure, where additional curves ("adjusted") are added to Figure 2A those curves shown in. In this example, a substrate with a 3-nanometer dopant layer 116 has been processed according to Figure 1A to 1E the process of. In this case, the adjusted curve represents process conditions in which the implantation energy and boron dose are adjusted such that the junction depth substantially matches the depth of the control sample. However, the surface concentration of the boron dopant is much higher than the surface concentration of the control sample, indicating that the embodiments of the present disclosure provide a mechanism in which the junction depth can be adjusted independently of the dopant concentration (especially the dopant concentration near the surface, such as approximately 10 nanometers at the surface).

[0031] In other embodiments of the present disclosure, in order to better control the dopant concentration and junction depth, the above methods of in-situ plasma cleaning for phosphorus, in-situ plasma deposition of the dopant layer, and subsequent ion implantation can be used.

[0032] According to an embodiment of the present disclosure, the method outlined has been implemented on a device substrate, where various measurements have confirmed superior performance compared to a device implanted with dopants without performing operations such as Figure 1A-1E . Examples of improved properties include lower contact resistance in source / drain contacts formed on the doped substrate, improved on-current (I Figure 1A-1C ) in transistor devices, and reduced off-current (I ON ) as well as reduced off-current (I OFF ).

[0033] Without being bound by any particular theory, the improved dopant engineering achieved according to embodiments of the present disclosure (better control of surface dopant concentration, better control of junction depth) can be achieved in part by leaving a semiconductor surface with little or no native oxide thereon. During an ion implantation process, many silicon interstitials are generated in the bulk of the implanted semiconductor substrate. Even when the substrate temperature is at room temperature, these silicon interstitials travel within the semiconductor substrate. In the presence of a native oxide, the interstitials may be reflected back into the bulk of the semiconductor substrate, leading to defects, deactivation, and enhanced dopant diffusion. The multi-process substrate treatment disclosed herein solves this problem as described below. Plasma cleaning within the ion implantation equipment to remove the native oxide from the surface of the semiconductor substrate while maintaining the semiconductor substrate under high vacuum conditions will tend to keep the semiconductor surface free of native oxide prior to dopant deposition. Such a native-oxide-free surface can expose a rich layer of silicon dangling bonds, which will allow the silicon interstitials to undergo a final treatment at the surface. The results of such a final treatment can include higher dopant activation, fewer defects, and less interstitial-enhanced diffusion of dopant species. This reduction in the diffusion of dopants into the semiconductor substrate and the higher activation can be further enhanced by the presence of a deposited layer of dopants on the surface during the ion implantation of the dopant species. During the impact process that occurs as a result of the ion implantation, the surface concentration of the dopants can be increased without causing an excessive increase in the depth of the dopant profile in the semiconductor substrate, and thus a relatively low junction depth is formed. As best understood, this result is achieved because the entire series of processes (including plasma cleaning, deposition of the dopant layer, and ion implantation) are all performed on an integrated beamline architecture that maintains the substrate under ordinary vacuum.

[0034] Turn to Figure 3 , which shows in block form the architecture of an exemplary ion implantation system (shown as ion implanter 300) according to embodiments of the present disclosure. As described above, ion implanter 300 includes an ion source 302 to generate an ion beam 318 for implanting ion species 118. As is known in the art, ion implanter 300 can include various components for accelerating, decelerating, shaping, and filtering the ion beam. These components are illustrated as beamline 304. During ion implantation, a terminal station 306 is provided downstream of beamline 304 to accommodate substrate 110. Ion implanter 300 can include a plasma cleaning chamber 308 and a plasma doping chamber 310. These chambers can be a single chamber or can be separate chambers communicatively coupled to terminal station 306 such that semiconductor substrate 100 can be transferred between the different chambers while maintaining a vacuum environment to perform as Figure 1A-1CThe processes outlined in. In other embodiments, one or more of plasma source 110 and plasma source 114 may be included within end station 306.

[0035] Now turning to Figure 4 , an exemplary process flow 400 in accordance with embodiments of the present disclosure is shown. At block 402, an operation of setting a semiconductor substrate in an ion implantation device is performed, where the semiconductor substrate includes single-crystalline semiconductor material on a first surface. It will be appreciated that the first surface may have a native oxide coating extending several nanometers in the direction on the first surface. Thus, in this example, the first surface of the single-crystalline semiconductor material may be located several nanometers below the outer surface of the semiconductor substrate.

[0036] At block 404, a plasma cleaning operation is performed on the semiconductor substrate, where the native oxide is removed from the first surface of the semiconductor substrate. The plasma cleaning may be performed using a suitable species at a relatively low energy (e.g., several electron volts to several tens of electron volts). Examples of suitable species include hydrogen ions or hydrogen radicals and related species. In this way, the plasma cleaning can remove the native oxide without damaging the single-crystalline semiconductor material extending to the first surface.

[0037] At block 406, a deposition of a dopant layer is performed on the first surface while the semiconductor substrate is set in the ion implantation device. The deposition of the dopant layer may be performed using a plasma source that provides ion species or radical species at a relatively low energy (e.g., having an energy less than 100 electron volts). According to some non-limiting embodiments, the dopant layer may have a suitable thickness, such as 1 nanometer to 7 nanometers, or 2 nanometers to 4 nanometers.

[0038] At block 408, the substrate is exposed to an ion implantation process while the dopant layer is disposed on the first surface of the semiconductor substrate. The implantation process may involve ion species from a plasma source, where in some non-limiting embodiments, the ion energy may be up to 7 keV. In this operation, at least a portion of the dopant layer may be implanted into the semiconductor substrate. In other words, during the implantation process, the ion species may cause at least some atoms of the dopant layer to be driven into the semiconductor substrate directly beneath the dopant layer.

[0039] In summary, embodiments of the present disclosure convey the following advantages. The first advantage is that by performing a multi-process treatment for doping a substrate, higher activation of the dopant can be achieved with fewer defects and less dopant diffusion. The second advantage is that the dopant concentration can be increased while not affecting the depth of the dopant profile (e.g., the junction depth).

[0040] The scope of the present disclosure is not limited to the specific embodiments described herein. In fact, upon reading the foregoing description and the accompanying drawings, various other embodiments of the present disclosure and modifications to the present disclosure will be apparent to those of ordinary skill in the art in addition to those described herein. Accordingly, such other embodiments and modifications are intended to fall within the scope of the present disclosure. Further, although the present disclosure has been described herein in the context of specific embodiments in a specific environment for a specific purpose, those skilled in the art will recognize that the usefulness of the embodiments of the present disclosure is not limited thereto and that the embodiments can be beneficially implemented in any number of environments for any number of purposes. Accordingly, the following claims are intended to be construed to cover the full breadth and spirit of the present disclosure as described herein.

Claims

1. A method for doping a semiconductor substrate, comprising: exposing a substrate surface of the semiconductor substrate to plasma cleaning; performing deposition of a dopant layer containing a dopant element on the substrate surface using a plasma source after the plasma cleaning; and exposing the semiconductor substrate to an implantation process when the dopant layer is disposed on the substrate surface, wherein the implantation process introduces ionic species containing the dopant element into the substrate, wherein the substrate is maintained under vacuum during a process duration spanning the plasma cleaning, the deposition of the dopant layer, and the implantation process, and wherein at least a portion of the dopant layer is implanted into the substrate during the implantation process.

2. The method according to claim 1, wherein the substrate surface contains a native oxide before the plasma cleaning, and wherein the native oxide is removed after the plasma cleaning.

3. The method according to claim 1, wherein the plasma cleaning is accomplished by: generating hydrogen species in a plasma chamber; and directing the hydrogen species to the substrate surface when the substrate is at a cleaning temperature between room temperature and 100 degrees Celsius, wherein the substrate surface is finally treated with hydrogen passivation after the plasma cleaning.

4. The method according to claim 1, wherein the performing the deposition comprises: generating dopant species containing a dopant element in the plasma source; and directing the dopant species to the substrate surface when the substrate is at a substrate temperature between room temperature and -100 degrees Celsius.

5. The method according to claim 4, wherein the dopant species includes a boron-containing species or a phosphorus-containing species.

6. The method according to claim 4, wherein the dopant species contains energy from several electron volts to 100 electron volts.

7. The method according to claim 4, wherein the dopant layer has a thickness of 1 nanometer to 7 nanometers before the implantation process.

8. The method according to claim 1, wherein the dopant element is derived from a dopant species including BF3 or PF3, and wherein the ionic species contains an ion energy of less than 7 keV.

9. The method according to claim 7, wherein the implantation range of the ionic species is greater than the thickness of the dopant layer before the implantation process.

10. The method according to claim 1, wherein the plasma cleaning, the deposition of the dopant layer, and the implantation process are performed as an implantation cycle, and wherein the implantation cycle is repeated one or more times to implant a target dopant level into the semiconductor substrate.

11. A method for doping a substrate, comprising: providing a single crystal semiconductor material on a surface of the substrate; exposing the surface to plasma cleaning, wherein a native oxide is removed from the surface; After the plasma cleaning, a dopant layer containing a dopant element is deposited on the surface of the substrate using a plasma source; and when the dopant layer is disposed on the substrate surface, the substrate is exposed to an implantation process, wherein the implantation process introduces an ion species containing the dopant element into the substrate, wherein the substrate is maintained under vacuum during the process duration spanning the plasma cleaning, the deposition of the dopant layer, and the implantation process, and wherein at least a portion of the dopant layer is implanted into the substrate during the implantation process.

12. The method according to claim 11, wherein the plasma cleaning is accomplished by the following steps: generating hydrogen species in a plasma chamber; and directing the hydrogen species to the surface of the substrate when the substrate is at a cleaning temperature between room temperature and -100 degrees Celsius, wherein the surface of the substrate is finally treated with hydrogen passivation after the plasma cleaning.

13. The method according to claim 11, wherein the performing the deposition comprises: generating dopant species in the plasma source, the dopant species containing a dopant element; and directing the dopant species to the surface of the substrate when the substrate is at a substrate temperature between room temperature and 100 degrees Celsius.

14. The method according to claim 13, wherein the dopant species contains energy from several electron volts to 100 electron volts.

15. The method according to claim 11, wherein the dopant layer has a thickness of 1 nanometer to 7 nanometers before the implantation process, and wherein the implantation range of the ion species is greater than the thickness of the dopant layer before the implantation process.

16. A method for doping a semiconductor substrate, comprising: disposing the semiconductor substrate in a beam-line ion implanter; exposing the substrate surface of the semiconductor substrate to plasma cleaning; after the plasma cleaning, using a plasma source to perform deposition of a dopant layer containing a dopant element on the substrate surface; and when the dopant layer is disposed on the substrate surface, exposing the substrate to an implantation process, wherein the implantation process introduces an ion species containing the dopant element into the semiconductor substrate, wherein the substrate is maintained in the beam-line ion implanter under vacuum during the process duration spanning the plasma cleaning, the deposition of the dopant layer, and the implantation process, and wherein at least a portion of the dopant layer is driven into the semiconductor substrate during the implantation process.

17. The method according to claim 16, wherein the substrate surface contains a native oxide before the plasma cleaning, the native oxide is removed after the plasma cleaning, and the substrate surface is finally treated with hydrogen passivation after the plasma cleaning.

18. The method according to claim 16, wherein the performing the deposition comprises: A dopant species is generated in the plasma source, the dopant species including a dopant element; and directing the dopant species to the substrate surface while the semiconductor substrate is at a substrate temperature between room temperature and 100 degrees Celsius.

19. The method of claim 16, wherein the dopant layer has a thickness of from 1 nanometer to 7 nanometers prior to the implantation process, and wherein the implantation range of the ion species is greater than the thickness of the dopant layer prior to the implantation process.

20. The method of claim 16, wherein the plasma cleaning, the deposition of the dopant layer, and the implantation process are performed as an implantation cycle, wherein the implantation cycle is repeated one or more times to implant a target dopant level into the substrate.

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