PID (Proportion Integration Differentiation) control circuit and system and sine wave-like signal generation method

Abstract

The invention provides a PID control circuit and system and a sine wave-like signal generation method, and relates to the field of industrial control. The circuit comprises an IIR filter circuit, a switching circuit and a triangular wave generation circuit, and the triangular wave generation circuit generates a first triangular wave according to a preset parameter and inputs the first triangular wave to the switching circuit; the switching circuit configures an operation core of the IIR filter circuit into an integrator according to the first triangular wave, and switches the input of the IIR filter circuit into an instruction signal; when the operation core of the IIR filter circuit is an integrator, the IIR filter circuit generates a sine wave-like signal according to the instruction signal and inputs the sine wave-like signal to the switching circuit; the switching circuit configures an operation core of the IIR filter circuit as a PID controller, and switches the input of the IIR filter circuit into a sine wave-like signal; when an operation core of the IIR filter circuit is a PID controller, the IIR filter circuit generates and outputs a control signal for PID control according to the sine wave-like signal, so that logic resources and cost are saved.

Description

Technical Field

[0001] This application relates to the field of industrial control, and particularly to a PID control circuit, a system, and a method for generating a quasi-sine wave signal. Background Art

[0002] A proportional-integral-derivative (PID) controller is a linear controller that can form a control quantity by linearly combining the proportion, integral, and derivative of a control deviation, so as to control a controlled object, such as a power supply loop, a motor, etc. In a PID controller, in order to prevent the PID controller from entering a saturation output state, a sine transition method can be used to anti-saturate the input signal to ensure that the output signal of the PID controller can meet the system performance requirements.

[0003] In the above sine transition method, a sine wave needs to be generated. In the related art, a look-up table method or a coordinate rotation digital computer (CORDIC) iterative algorithm is usually used to generate a sine wave. However, the look-up table method requires adding a non-volatile memory in the PID controller to store the sampled point data after discretization of the sine wave. When generating a sine wave through the look-up table method, an additional multiplier is also required, increasing the cost and the consumption of logic resources. The CORDIC iterative algorithm requires adding multiple multipliers in the PID controller and going through multiple iterative calculations to obtain the required sine wave, consuming a large amount of logic resources and having a high cost. Summary of the Invention

[0004] This application provides a PID control circuit, a system, and a method for generating a quasi-sine wave signal to solve the problem of high cost and large consumption of logic resources in the existing sine transition, and achieves the purpose of saving logic resources and cost.

[0005] In a first aspect, this application provides a PID control circuit. The PID control circuit includes: an infinite impulse response (IIR) filter circuit, a switching circuit, and a triangular wave generation circuit. The input end of the triangular wave generation circuit receives a preset parameter, the input end of the switching circuit receives a command signal, the output end of the triangular wave generation circuit is connected to the input end of the switching circuit, the output end of the switching circuit is connected to the input end of the IIR filter circuit, and the output end of the IIR filter circuit is connected to the input end of the switching circuit;

[0006] The triangular wave generation circuit is configured to generate a first triangular wave according to the preset parameter and input the first triangular wave into the switching circuit;

[0007] A switching circuit, configured to configure the arithmetic core of the IIR filter circuit as an integrator according to a first triangular wave, and switch the input of the IIR filter circuit to an instruction signal;

[0008] An IIR filter circuit, configured to generate a quasi-sine wave signal according to the instruction signal when the arithmetic core of the IIR filter circuit is an integrator, and input the quasi-sine wave signal to the switching circuit, where the amplitude of the quasi-sine wave signal is consistent with the amplitude of the instruction signal;

[0009] The switching circuit is further configured to configure the arithmetic core of the IIR filter circuit as a PID controller, and switch the input of the IIR filter circuit to the quasi-sine wave signal;

[0010] The IIR filter circuit is further configured to generate and output a control signal according to the quasi-sine wave signal when the arithmetic core of the IIR filter circuit is a PID controller, and the control signal is used for PID control.

[0011] In some examples, the switching circuit includes an integration register group, a PID register group, and a selection circuit. The integration register group is configured to store a first coefficient group and receive and store the first triangular wave. The PID register group is configured to store a second coefficient group and receive and store the quasi-sine wave signal. The first input end of the selection circuit receives the instruction signal. The output end of the triangular wave generation circuit is connected to the input end of the integration register group. The output end of the integration register group is connected to the second input end of the selection circuit. The input end of the PID register group is connected to the output end of the IIR filter circuit. The output end of the PID register group is connected to the third input end of the selection circuit. The output end of the selection circuit is connected to the input end of the IIR filter circuit;

[0012] The selection circuit is configured to select and connect to the integration register group, so that the arithmetic core of the IIR filter circuit is configured as an integrator using the first coefficient group and the first triangular wave, and input the instruction signal to the IIR filter circuit;

[0013] Or,

[0014] The selection circuit is configured to select and connect to the PID register group, so that the arithmetic core of the IIR filter circuit is configured as a PID controller using the second coefficient group, and input the quasi-sine wave signal to the IIR filter circuit.

[0015] In some examples, the IIR filter circuit includes a first multiplier, a second multiplier, a third multiplier, a fourth multiplier, a fifth multiplier, a first intermediate register group, a second intermediate register group, a third intermediate register group, a clipping circuit, a first adder, a second adder, and a third adder;

[0016] The first output terminal of the selection circuit is connected to the first input terminal of the first multiplier. The second output terminal of the selection circuit is connected to the second input terminal of the first multiplier. The output terminal of the first multiplier is connected to the first input terminal of the first adder. The second input terminal of the first adder is connected to the output terminal of the first intermediate register bank. The third input terminal of the first adder is connected to the output terminal of the second intermediate register bank. The output terminal of the first adder is connected to the input terminal of the clipping circuit. The first output terminal of the clipping circuit is connected to the input terminal of the first intermediate register bank. The second output terminal of the clipping circuit outputs a quasi-sine wave signal or a control signal. The second output terminal of the clipping circuit is also connected to the first input terminal of the fourth multiplier. The second input terminal of the fourth multiplier is connected to the third output terminal of the selection circuit. The output terminal of the fourth multiplier is connected to the first input terminal of the third adder. The second input terminal of the third adder is connected to the output terminal of the third multiplier. The output terminal of the third adder is connected to the input terminal of the third intermediate register bank. The output terminal of the third intermediate register bank is connected to the first input terminal of the second adder. The second input terminal of the second adder is connected to the output terminal of the second multiplier. The third input terminal of the second adder is connected to the output terminal of the fifth multiplier. The output terminal of the second adder is connected to the input terminal of the second intermediate register bank. The first input terminal of the second multiplier is connected to the first output terminal of the selection circuit. The second input terminal of the second multiplier is connected to the fourth output terminal of the selection circuit. The first input terminal of the third multiplier is connected to the first output terminal of the selection circuit. The second input terminal of the third multiplier is connected to the fifth output terminal of the selection circuit. The first input terminal of the fifth multiplier is connected to the second output terminal of the clipping circuit. The second input terminal of the fifth multiplier is connected to the sixth output terminal of the selection circuit;

[0017] A selection circuit, configured to configure an arithmetic core of an IIR filter circuit through a first triangular wave and a first coefficient group, such that the first multiplier, the first adder, the first intermediate register bank, the second intermediate register bank, the fifth multiplier, and the clipping circuit form an integrator;

[0018] Or,

[0019] A selection circuit, configured to configure an arithmetic core of an IIR filter circuit through a second coefficient group, such that the first multiplier, the second multiplier, the third multiplier, the fourth multiplier, the fifth multiplier, the first intermediate register bank, the second intermediate register bank, the third intermediate register bank, the clipping circuit, the first adder, the second adder, and the third adder form a PID controller.

[0020] In some examples, the first coefficient group includes: a first coefficient, a second coefficient, a third coefficient, a fourth coefficient, and a fifth coefficient. The first coefficient is used to configure a first multiplier, the second coefficient is used to configure a second multiplier, the third coefficient is used to configure a third multiplier, the fourth coefficient is used to configure a fourth multiplier, and the fifth coefficient is used to configure a fifth multiplier;

[0021] Among them, the first coefficient is a first triangular wave, the second coefficient, the third coefficient, and the fourth coefficient are all 0, and the fifth coefficient is 1.

[0022] In some examples, when the arithmetic core of the IIR filter circuit is an integrator, the first transfer function of the IIR filter circuit is:

[0023]

[0024] Among them, h1(z) is the first transfer function, y1(z) is the z-domain expression of the output signal y1(t) in the time domain, x1(z) is the z-domain expression of the input signal x1(t) in the time domain, b0 is the first triangular wave, and z represents the transformation factor of the z-transform.

[0025] In some examples, the second coefficient group includes: a sixth coefficient, a seventh coefficient, an eighth coefficient, a ninth coefficient, and a tenth coefficient. The sixth coefficient is used to configure a first multiplier, the seventh coefficient is used to configure a second multiplier, the eighth coefficient is used to configure a third multiplier, the ninth coefficient is used to configure a fourth multiplier, and the tenth coefficient is used to configure a fifth multiplier;

[0026] Among them, the second coefficient group is determined according to a preset PID transfer function.

[0027] In some examples, when the arithmetic core of the IIR filter circuit is a PID controller, the second transfer function of the IIR filter circuit is:

[0028]

[0029] Among them, h2(z) is the second transfer function, y2(z) is the z-domain expression of the output signal y2(t) in the time domain, x2(z) is the z-domain expression of the input signal x2(t) in the time domain, b6 is the sixth coefficient, b7 is the seventh coefficient, b8 is the eighth coefficient, a9 is the ninth coefficient, a 10 is the tenth coefficient, and z represents the transformation factor of the z-transform.

[0030] In some examples, the IIR filter circuit further includes a distributor. The input end of the distributor is connected to the second output end of the clipping circuit, the first output end of the distributor is connected to the input end of the PID register group, and the second output end of the distributor outputs a control signal;

[0031] A distributor, configured to output a quasi-sine wave signal to a PID register group when the arithmetic core of an IIR filter circuit is an integrator.

[0032] Or,

[0033] A distributor, configured to output a control signal when the arithmetic core of an IIR filter circuit is a PID controller.

[0034] In some examples, the preset parameters include a transition time and an area parameter. The transition time is used to adjust the time span of the first triangular wave, and the area parameter is used to adjust the area of the first triangular wave. The area parameter satisfies Formula 1. Wherein, Formula 1 is S = 2 2N-2 ;

[0035] Wherein, S is the area parameter, and N is an integer greater than or equal to 0.

[0036] In a second aspect, the present application provides a PID control system. The PID control system includes the PID control circuit described in the first aspect and any one of the first aspect, and a controlled object.

[0037] In a third aspect, the present application provides a chip, including: the PID control circuit described in the first aspect and any one of the first aspect.

[0038] In a fourth aspect, the present application provides an electronic device, including: the chip described in the third aspect.

[0039] In a fifth aspect, the present application provides a method for generating a quasi-sine wave signal, including:

[0040] Generating a first triangular wave according to preset parameters;

[0041] Generating a quasi-sine wave signal according to the first triangular wave and an instruction signal, and the amplitude of the quasi-sine wave signal is consistent with the instruction signal.

[0042] In some examples, the preset parameters include a transition time and an area parameter. The transition time is used to adjust the time span of the first triangular wave, and the area parameter is used to adjust the area of the first triangular wave. The area parameter satisfies Formula 1. Wherein, Formula 1 is: S = 2 2N-2 ;

[0043] Wherein, S is the area parameter, and N is an integer greater than or equal to 0.

[0044] In some examples, generating a quasi-sine wave signal according to the first triangular wave and an instruction signal includes:

[0045] Multiplying the first triangular wave and the instruction signal to obtain a product of the first triangular wave and the instruction signal;

[0046] Integrating the product of the first triangular wave and the instruction signal to obtain an integration result;

[0047] Divide the integration result by the area of the first triangular wave to obtain a quasi-sine wave signal.

[0048] In this application, the switching circuit is used to configure the arithmetic core of the IIR filter circuit as an integrator, and the input of the IIR filter circuit is switched to the command signal, so that the IIR filter circuit realizes the integration function and obtains a quasi-sine wave signal, thereby realizing the sine transition of the command signal and realizing the anti-saturation of the command signal. The switching circuit is used to configure the arithmetic core of the IIR filter circuit as a PID controller, and the input of the IIR filter circuit is switched to the quasi-sine wave signal, thereby realizing the PID control based on the quasi-sine wave signal. Based on this, the same set of devices can be reused in two stages to respectively realize the anti-saturation function and the PID control function, realize the anti-saturation PID control with less logic resources, without the need to additionally use a non-volatile memory for storage, nor the need to add an additional multiplier, saving logic resources and cost overhead, and further saving the wiring area overhead. Brief Description of the Drawings

[0049] Figure 1 It is a schematic structural diagram of a PID control system provided by an embodiment of the present application.

[0050] Figure 2 It is a waveform schematic diagram of an input signal provided by an embodiment of the present application.

[0051] Figure 3 It is a schematic structural diagram of a PID control system provided by an embodiment of the present application.

[0052] Figure 4 It is a waveform schematic diagram of an input signal after linear transition provided by an embodiment of the present application.

[0053] Figure 5 It is a waveform schematic diagram of an input signal after sine transition provided by an embodiment of the present application.

[0054] Figure 6 It is a schematic structural diagram of a PID control circuit provided by an embodiment of the present application.

[0055] Figure 7 It is a waveform schematic diagram of a first triangular wave provided by an embodiment of the present application.

[0056] Figure 8 It is a schematic structural diagram of a PID control circuit provided by an embodiment of the present application.

[0057] Figure 9 It is a schematic structural diagram of a PID control circuit provided by an embodiment of the present application.

[0058] Figure 10 Flow chart of a method for generating a quasi-sine wave signal provided by an embodiment of the present application.

[0059] Figure 11 Flow chart of a method for generating a quasi-sine wave signal provided by an embodiment of the present application. Detailed implementation manners

[0060] In the present application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B may be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item)" or its similar expression refers to any combination of these items, including any combination of single item (item) or plural items (items). For example, at least one (item) of a alone, b alone, or c alone may represent: a alone, b alone, c alone, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b, and c, where a, b, and c may be single or multiple. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0061] The orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "upper", "lower", "left", "right", "front", "rear", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation to the present application.

[0062] The terms "connected" and "coupled" should be understood in a broad sense. For example, the "connection" or "coupling" of a circuit structure may refer not only to a physical connection, but also to an electrical connection or a signal connection. For example, it may be a direct connection, that is, a physical connection, or may be indirectly connected through at least one intermediate element, as long as the circuit is connected. It may also be the connection inside two elements; the signal connection may refer not only to the signal connection through a circuit, but also to the signal connection through a media medium. For example, radio waves. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0063] The PID controller is a component widely used in industrial control. For example, the PID controller can be applied to scenarios such as the loop control of a power supply and the motor drive control. The following will be combined with Figure 1 to introduce the basic structure of the PID control system.

[0064] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a PID control system provided by an embodiment of the present application.

[0065] As Figure 1 shown, the PID control system consists of a PID controller and a controlled object. Among them, the PID controller consists of a proportional part P, an integral part I, a derivative part D, an addition part S1, and an addition part S2. The input signal r(t) is input to the PID controller. The error signal e(t) is calculated through the addition part S1 and the output y(t) of the controlled object. The error signal e(t) passes through the proportional part P, the integral part I, the derivative part D, and the addition part S2 to obtain the control signal u(t). The control signal u(t) controls the controlled object, and the controlled object obtains the output signal y(t).

[0066] Among them, the controlled object can be, for example, a motor, an air conditioner, a water heater, or an electric furnace, etc.

[0067] In the above process, as Figure 2 shown, Figure 2 shows a waveform diagram of the input signal r(t) changing stepwise with time t. If the input signal r(t) changes stepwise, then the error signal e(t) will also change stepwise. If the amplitude of the step change is large or the gain of the PID controller is large, it will cause a large change in the component of the proportional part P. At the same time, the component of the integral part I will also be integrated to a very large value in a short time, resulting in a large output of the PID controller. Based on this, if the output of the PID controller exceeds the amplitude limit of the PID controller, it will cause the PID controller to enter the output saturation state, and the control loop of the PID controller is equivalent to an open-loop control, thus unable to meet the control requirements and performance requirements of the PID control system.

[0068] Furthermore, if the output of the PID controller changes violently, it will also cause the PID control system to oscillate and have poor stability.

[0069] In the related art, usually, an anti-windup link can be added to the PID control system to cope with the situation where the input signal r(t) changes stepwise.

[0070] Please refer to Figure 3 , Figure 3 which is a schematic structural diagram of a PID control system provided by an embodiment of the present application.

[0071] As Figure 3 shown, an anti-windup link can be cascaded after the input signal r(t) on the basis of the structure of the PID control system shown in Figure 1 to achieve anti-windup.

[0072] Among them, the anti-saturation link usually can adopt a linear transition method or a sine transition method to achieve anti-saturation of the input signal r(t).

[0073] The waveform of the input signal r(t) adopting the linear transition method is as Figure 4 shown, Figure 4 showing the waveform of the input signal r(t) adopting the linear transition method changing with time t. The waveform of the input signal r(t) adopting the sine transition method is as Figure 5 shown, Figure 5 showing the waveform of the input signal r(t) adopting the sine transition method changing with time t.

[0074] Among them, the first derivative of the input signal r(t) in the linear transition method is discontinuous, and the first derivative of the input signal r(t) in the sine transition method is continuous. When both the input signal r(t) and its first derivative are continuous, the impact on the PID control system is the smallest. Therefore, the effect of the sine transition method is better than that of the linear transition method.

[0075] In the sine transition method, a sine wave needs to be generated.

[0076] The following introduces two commonly used sine wave generation methods in related technologies.

[0077] Method 1, look-up table method.

[0078] Specifically, first, it is necessary to discretize a single-cycle sine wave with an amplitude of 1, an initial phase of 0, and a phase range of [0, 360]° to obtain multiple sampling point data, and store the multiple sampling point data in a non-volatile memory. When generating a sine wave, continuously reading out the multiple sampling point data in the non-volatile memory can obtain the sine wave, and multiplying the sine wave by the step amplitude of the input signal r(t) can achieve sine transition.

[0079] Method 2, CORDIC iterative algorithm.

[0080] Specifically, by performing multiple iterations to calculate the sine value corresponding to the required angle, and then multiplying it by the step amplitude of the input signal r(t), as the required angle increases, sine transition can be achieved.

[0081] However, in the above Method 1, generating a sine wave requires an additional non-volatile memory to store multiple sampling point data. If the discrete frequency of the sine wave is higher, the number of sampling points is more, so the storage capacity of the non-volatile memory required is higher, and the logic overhead will also increase with the increase of the discrete frequency, resulting in an increase in cost. In addition, Method 1 also needs to add a multiplier for multiplying the sine wave by the step amplitude of the input signal r(t), which will also increase the overhead of logic resources.

[0082] In the above-mentioned Method 2, the CORDIC algorithm is relatively complex. The algorithm itself consumes more logic resources and requires multiple iterations to calculate the sine value of the angle that meets the requirements. That is, its calculation frequency is n times the control frequency of the PID controller, where n is the number of iterations and n is a positive integer greater than or equal to 1, in order to update the sine value once per control period of each PID controller. For example, if the control frequency is 1 MHz and it takes 16 iterations to generate a sine value of the angle that meets the requirements each time, then the calculation frequency of the CORDIC algorithm is 16 MHz. This not only requires an additional high-frequency clock but also increases the timing burden. In addition, implementing the CORDIC algorithm also requires two additional multipliers and a storage unit for storing the generated sine value, which not only results in a higher cost of the PID controller but also increases the area of the PID controller.

[0083] Exemplarily, the present application provides a PID control circuit, a system, and a method for generating a quasi-sine wave signal. By reusing the devices in an infinite impulse response (IIR) filter circuit and reconfiguring the arithmetic core of the IIR filter circuit twice, the sine transition of the input signal and the PID control are respectively realized, so as to implement a PID controller with an anti-saturation link with less logic resource consumption and lower cost.

[0084] Next, with reference to specific embodiments, the PID control circuit provided by the present application will be introduced in detail.

[0085] Please refer to Figure 6 , Figure 6 which is a schematic structural diagram of a PID control circuit provided by an embodiment of the present application.

[0086] As Figure 6 shown, the PID control circuit includes: an IIR filter circuit 10, a switching circuit 20, and a triangular wave generation circuit 30.

[0087] Among them, the input end of the triangular wave generation circuit 30 receives preset parameters, and the input end of the switching circuit 20 receives an instruction signal.

[0088] Among them, the output end of the triangular wave generation circuit 30 is connected to the input end of the switching circuit 20, the output end of the switching circuit 20 is connected to the input end of the IIR filter circuit 10, and the output end of the IIR filter circuit 10 is connected to the input end of the switching circuit 20.

[0089] Among them, the instruction signal can also be referred to as an input signal or a reference signal. The instruction signal is a given value.

[0090] For example, in motor control, the command signal can be the current signal or the rotational speed signal of the motor.

[0091] For another example, in air conditioner control, the command signal can be the temperature difference signal, that is, the difference signal between the set temperature and the actual temperature.

[0092] Among them, the structure of the IIR filter circuit 10 can be direct form I, direct form II, cascade form or parallel form, etc.

[0093] Next, two stages of implementing PID control through the PID control circuit will be introduced.

[0094] Among them, the first stage is the anti-windup stage to achieve anti-windup of the command signal, and the second stage is the PID control stage to achieve PID control.

[0095] In the first stage, the triangular wave generation circuit 30 is used to generate a first triangular wave according to preset parameters and input the first triangular wave into the switching circuit 20. The switching circuit 20 is used to configure the arithmetic core of the IIR filter circuit 10 as an integrator according to the first triangular wave and switch the input of the IIR filter circuit 10 to the command signal. The IIR filter circuit 10 is used to generate a quasi-sine wave signal according to the command signal when the arithmetic core of the IIR filter circuit 10 is an integrator and input the quasi-sine wave signal into the switching circuit 20.

[0096] Among them, the preset parameters are used to limit the area and time span of the first triangular wave generated by the triangular wave generation circuit 30.

[0097] The time span of the first triangular wave is the transition time for anti-windup of the command signal.

[0098] Among them, the area of the first triangular wave can be a power of 2.

[0099] The triangular wave generation circuit 30 has various implementation manners.

[0100] In some examples, the triangular wave generation circuit 30 includes an up-down counter. The preset parameters include the transition time and the area parameter.

[0101] Among them, the transition time is used to adjust the time span of the first triangular wave. The area parameter is used to adjust the area of the first triangular wave.

[0102] Among them, the area parameter satisfies the following formula (1):

[0103] S = 2 2N-2 Formula (1);

[0104] Among them, S is the area parameter, and N is an integer greater than or equal to 0.

[0105] Among them, the transition time is (2a times the control period T, where a is an integer greater than or equal to 1 and less than or equal to N. The transition time is adjustable. Users can adjust the time span of the first triangular wave by adjusting the transition time according to their needs, and further adjust the transition duration of anti-saturation.

[0106] Among them, the control period T is the control period of the PID controller.

[0107] Among them, when the transition time is (2 a -1) times the control period T, the increment STEP of the addition and subtraction counter is 2 2N-2a , and the maximum value MAX of the addition and subtraction counter is 2 2N-a-1 . Among them, the units of STEP and MAX are: least significant bit (LSB).

[0108] For example, assume the area of the first triangular wave is 2 16 , then the area parameter is 2 16 , that is, N = 9. Then the relationship between the transition time, the increment STEP of the addition and subtraction counter, and the maximum value MAX of the addition and subtraction counter can be shown in Table 1 as follows.

[0109] Table 1

[0110]

[0111] When a = 3, the waveform of the first triangular wave generated by the triangular wave generation circuit 30 is as Figure 7 shown. In Figure 7 , the horizontal axis is time t, the vertical axis is the value code of the addition and subtraction counter, the area of the first triangular wave is 2 16 , the increment STEP of the addition and subtraction counter is 2 12 , and the maximum value MAX of the addition and subtraction counter is 2 14 .

[0112] Based on this, by configuring the transition time of the addition and subtraction counter, the time span of the first triangular wave can be adjusted, thereby further adjusting the transition time of anti-saturation. By configuring the area of the first triangular wave, that is, configuring the area parameter of the addition and subtraction counter, the adjustable gears of the transition time can be changed. For example, as shown in Table 1, when N = 9, there are 9 adjustable gears for the transition time. Another example is that if N = 12, there are 12 adjustable gears for the transition time. By changing the preset parameters of the triangular wave generation circuit 30, the transition time of anti-saturation can be adjusted simply and quickly without a complex mechanism.

[0113] In some other examples, the triangular wave generating circuit 30 includes a signal generator, such as SG-8038. The preset parameters include: waveform, frequency, and amplitude. Through the signal generator, the required first triangular wave can be directly generated conveniently and quickly.

[0114] After generating the first triangular wave, the triangular wave generating circuit inputs the first triangular wave into the switching circuit 20.

[0115] Based on this, the switching circuit 20 can configure the coefficients of each arithmetic device in the IIR filter circuit 10 based on the first triangular wave, such as the coefficients of one or more multipliers, so as to configure the arithmetic core of the IIR filter circuit 10 as an integrator, enabling the IIR filter circuit 10 to implement an integration function with the first triangular wave as one of the coefficients. The switching circuit 20 also switches the input of the IIR filter circuit 10 to the command signal.

[0116] Among them, the switching circuit 20 can be implemented by one or more registers and one or more multiplexers.

[0117] One or more registers are used to store the coefficients for configuring the arithmetic core of the IIR filter circuit 10, and one or more multiplexers are used to select different coefficients to configure the IIR filter circuit 10. Among them, the number of registers is related to the number of multipliers in the IIR filter circuit 10.

[0118] Thus, when the arithmetic core of the IIR filter circuit 10 is an integrator, the IIR filter circuit 10 processes the command signal, provides a sine waveform with the first triangular wave, and provides an amplitude with the command signal, obtaining a quasi-sine wave signal with an amplitude consistent with the command signal.

[0119] Among them, the amplitude of the quasi-sine wave signal is consistent with the amplitude of the command signal. The quasi-sine wave signal is the command signal after sine transition. The quasi-sine wave signal is a kind of sine wave, and both the quasi-sine wave signal and the first derivative of the quasi-sine wave signal are continuous.

[0120] After obtaining the quasi-sine wave signal, the IIR filter circuit 10 inputs the quasi-sine wave signal into the switching circuit 20.

[0121] So far, the PID control circuit completes the anti-saturation of the command signal, obtaining the command signal after sine transition, that is, the quasi-sine wave signal.

[0122] In the second stage, the switching circuit 20 is used to configure the arithmetic core of the IIR filter circuit 10 as a PID controller and switch the input of the IIR filter circuit 10 to the quasi-sine wave signal. The IIR filter circuit 10 is used to generate and output a control signal according to the quasi-sine wave signal when the arithmetic core of the IIR filter circuit is a PID controller, and the control signal is used for PID control.

[0123] When the switching circuit 20 receives a quasi-sine wave signal, the switching circuit 20 configures the arithmetic core of the IIR filter circuit 10 as a PID controller and uses the quasi-sine wave signal as the input of the IIR filter circuit 10, so that the IIR filter circuit 10 realizes the PID control function. Thus, the IIR filter circuit 10 generates a control signal according to the quasi-sine wave signal, and this control signal can be used for PID control.

[0124] Since the quasi-sine wave signal is an instruction signal with a sine transition, as the input of the IIR filter circuit 10 whose arithmetic core is configured as a PID controller, it can make both the input signal of the PID controller and the first derivative of the input signal continuous, thereby reducing the impact on the PID controller and avoiding the PID controller from entering the output saturation state, enabling the PID controller to achieve the control requirements and meet the performance requirements.

[0125] In the embodiment of the present application, in the above two stages, the quasi-sine wave signal and the control signal are both obtained through the IIR filter circuit 10. In the anti-saturation stage, the switching circuit 20 configures the arithmetic core of the IIR filter circuit 10 as an integrator and switches the input of the IIR filter circuit 10 to the instruction signal, so that the IIR filter circuit 10 realizes the integration function and obtains the quasi-sine wave signal, thereby realizing the sine transition of the instruction signal and achieving the anti-saturation of the instruction signal. In the PID control stage, the switching circuit 20 configures the arithmetic core of the IIR filter circuit 10 as a PID controller and switches the input of the IIR filter circuit 10 to the quasi-sine wave signal, thereby realizing the PID control based on the quasi-sine wave signal. Based on this, the same set of devices can be reused in the two stages to respectively realize the anti-saturation function and the PID control function, use fewer logic resources to realize the anti-saturation PID control, without the need to additionally use a non-volatile memory for storage, nor the need to add an additional multiplier, saving logic resources and cost overhead, and further saving the wiring area overhead.

[0126] Based on the above exemplary description, a detailed structure of the switching circuit 20 is introduced below.

[0127] Please refer to Figure 8 , Figure 8 which is a schematic structural diagram of a PID control circuit provided by an embodiment of the present application.

[0128] As Figure 8 shown, the switching circuit 20 includes an integration register group 201, a PID register group 202, and a selection circuit 203.

[0129] Among them, the integral register group 201 is used to store the first coefficient group and receive and store the first triangular wave. The first coefficient group and the first triangular wave are used to configure the arithmetic core of the IIR filter circuit 10 as an integrator.

[0130] Among them, the PID register group 202 is used to store the second coefficient group and receive and store the sine-wave-like signal. The second coefficient group is used to configure the arithmetic core of the IIR filter circuit 10 as a PID controller.

[0131] Among them, the first input end of the selection circuit 203 receives an instruction signal.

[0132] Among them, the output end of the triangular wave generation circuit 30 is connected to the input end of the integral register group 201, the output end of the integral register group 201 is connected to the second input end of the selection circuit 203, the input end of the PID register group 202 is connected to the output end of the IIR filter circuit 10, the output end of the PID register group 202 is connected to the third input end of the selection circuit 203, and the output end of the selection circuit 203 is connected to the input end of the IIR filter circuit 10.

[0133] In the above first stage, the selection circuit 203 is used to gate to the integral register group 201, so that the arithmetic core of the IIR filter circuit 10 is configured as an integrator using the first coefficient group and the first triangular wave, and the instruction signal is input to the IIR filter circuit 10.

[0134] In the above second stage, the selection circuit 203 is used to gate to the PID register group 202, so that the arithmetic core of the IIR filter circuit 10 is configured as a PID controller using the second coefficient group, and the sine-wave-like signal is input to the IIR filter circuit 10. At the same time, the selection circuit 203 also needs to mask the instruction signal.

[0135] Among them, the selection circuit 203 can be implemented by one or more multiplexers. During the multi-channel data transfer process, the multiplexer can select one of them for transmission according to needs.

[0136] For example, for a device A that needs to be configured in the IIR filter circuit 10, the output end of a multiplexer M is connected to the input end of the device A, and the multiple input ends of the multiplexer M are respectively connected to the register 1 that stores the coefficient corresponding to the device A in the integral register group 201 and the register 2 that stores the coefficient corresponding to the device A in the PID register group 202. When it is necessary to configure the IIR filter circuit 10 as an integrator, for the device A, the multiplexer M gates to the register 1 and inputs the coefficient in the register 1 to the device A. After each device that needs to be configured is configured in the above manner, the IIR filter circuit 10 is configured as an integrator.

[0137] When the IIR filter circuit 10 needs to be configured as a PID controller, for device A, the multiplexer M is gated to register 2, and the coefficients in register 2 are input to device A. After each device to be configured is configured in the above manner, the IIR filter circuit 10 is configured as a PID controller.

[0138] It should be noted that the present application does not limit the number of input terminals of the multiplexer. For example, the multiplexer can be a two-input one-output multiplexer. Of course, the multiplexer can also be a multi-input one-output multiplexer.

[0139] Among them, the integration register group 201 may include one register, that is, multiple coefficients in the first coefficient group and the first triangular wave can be stored in the same register, or the integration register group 201 may include multiple registers, that is, multiple coefficients in the first coefficient group and the first triangular wave can be stored in multiple registers respectively. The present application does not limit this.

[0140] Similarly, the PID register group 202 may include one register, that is, multiple coefficients in the second coefficient group and the quasi-sine wave signal can be stored in the same register, or the PID register group 202 may include multiple registers, that is, multiple coefficients in the second coefficient group and the quasi-sine wave signal can be stored in multiple registers respectively. The present application does not limit this.

[0141] Based on this, through the register and the multiplexer, the switching circuit 20 can realize various configurations of the arithmetic core of the IIR filter circuit 10, so that the IIR filter circuit 10 can realize the integration function, thereby anti-saturating the command signal, and can realize the PID control function, thereby realizing the PID control based on the command signal, without using a relatively expensive non-volatile memory and adding a multiplier, and the register and the multiplexer have low cost and simple logic, further saving logic resources and cost overhead.

[0142] Based on the above exemplary description, taking the biquadratic IIR filter structure as an example, a detailed structure of the IIR filter circuit 10 is introduced.

[0143] Please refer to Figure 9 , Figure 9 which is a schematic structural diagram of a PID control circuit provided by an embodiment of the present application.

[0144] As Figure 9As shown, the IIR filter circuit 10 includes a first multiplier M1, a second multiplier M2, a third multiplier M3, a fourth multiplier M4, a fifth multiplier M5, a first intermediate register bank P1, a second intermediate register bank P2, a third intermediate register bank P3, a clipping circuit CF, a first adder A1, a second adder A2, and a third adder A3.

[0145] Among them, the first output terminal 4 of the selection circuit 203 is connected to the first input terminal of the first multiplier M1, the second output terminal 5 of the selection circuit 203 is connected to the second input terminal of the first multiplier M1, the output terminal of the first multiplier M1 is connected to the first input terminal of the first adder A1, the second input terminal of the first adder A1 is connected to the output terminal of the first intermediate register bank P1, the third input terminal of the first adder A1 is connected to the output terminal of the second intermediate register bank P2, the output terminal of the first adder A1 is connected to the input terminal of the clipping circuit CF, the first output terminal of the clipping circuit CF is connected to the input terminal of the first intermediate register bank P1, the second output terminal of the clipping circuit CF outputs a quasi-sine wave signal or a control signal, the second output terminal of the clipping circuit CF is further connected to the first input terminal of the fourth multiplier M4, the second input terminal of the fourth multiplier M4 is connected to the third output terminal 9 of the selection circuit 203, the output terminal of the fourth multiplier M4 is connected to the first input terminal of the third adder A3, the second input terminal of the third adder A3 is connected to the output terminal of the third multiplier M3, the output terminal of the third adder A3 is connected to the input terminal of the third intermediate register bank P3, the output terminal of the third intermediate register bank P3 is connected to the first input terminal of the second adder A2, the second input terminal of the second adder A2 is connected to the output terminal of the second multiplier M2, the third input terminal of the second adder A2 is connected to the output terminal of the fifth multiplier M5, the output terminal of the second adder A2 is connected to the input terminal of the second intermediate register bank P2, the first input terminal of the second multiplier M2 is connected to the first output terminal 4 of the selection circuit 203, the second input terminal of the second multiplier M2 is connected to the fourth output terminal 7 of the selection circuit 203, the first input terminal of the third multiplier M3 is connected to the first output terminal 4 of the selection circuit 203, the second input terminal of the third multiplier M3 is connected to the fifth output terminal 8 of the selection circuit 203, the first input terminal of the fifth multiplier M5 is connected to the second output terminal of the clipping circuit CF, and the second input terminal of the fifth multiplier M5 is connected to the sixth output terminal 6 of the selection circuit 203.

[0146] Among them, the first output terminal 4 of the selection circuit 203 outputs an instruction signal. The second output terminal 5 of the selection circuit 203 outputs a coefficient for configuring the first multiplier M1. The third output terminal 9 of the selection circuit 203 outputs a coefficient for configuring the fourth multiplier M4. The fourth output terminal 7 of the selection circuit 203 outputs a coefficient for configuring the second multiplier M2. The fifth output terminal 8 of the selection circuit 203 outputs a coefficient for configuring the third multiplier M3. The sixth output terminal 6 of the selection circuit 203 outputs a coefficient for configuring the fifth multiplier M5.

[0147] It should be noted that the above coefficients refer to the coefficients stored in the integration register group 201 in the first stage and the coefficients stored in the PID register group 202 in the second stage.

[0148] Among them, the first intermediate register group P1, the second intermediate register group P2, and the third intermediate register group P3 are all used to store intermediate operation results.

[0149] In some examples, the first intermediate register group P1, the second intermediate register group P2, and the third intermediate register group P3 each include two intermediate registers and a multiplexer. The two intermediate registers are respectively used to store the intermediate results generated during the operation when the operation core of the IIR filter circuit 10 is configured as an integrator, and the intermediate results generated during the operation when the operation core of the IIR filter circuit 10 is configured as a PID controller. The multiplexer is used to select the corresponding intermediate register to store or output the corresponding intermediate result during the operation, so as to avoid confusing the intermediate results formed in the first stage or the second stage.

[0150] In the above first stage, the selection circuit 203 is used to configure the operation core of the IIR filter circuit 10 through the first triangular wave and the first coefficient group, so that the first multiplier M1, the first adder A1, the first intermediate register group P1, the second intermediate register group P2, the fifth multiplier M5, and the clipping circuit CF form an integrator.

[0151] In some examples, the first coefficient group includes: a first coefficient, a second coefficient, a third coefficient, a fourth coefficient, and a fifth coefficient. The first coefficient is used to configure the first multiplier M1. The second coefficient is used to configure the second multiplier M2. The third coefficient is used to configure the third multiplier M3. The fourth coefficient is used to configure the fourth multiplier M4. The fifth coefficient is used to configure the fifth multiplier M5.

[0152] Among them, the first coefficient is the first triangular wave, the second coefficient, the third coefficient, and the fourth coefficient are all 0, and the fifth coefficient is 1.

[0153] As a result, the second multiplier M2, the third multiplier M3, the fourth multiplier M4, the third adder A3, and the third intermediate register bank P3 are masked, such that the first multiplier M1, the first adder A1, the first intermediate register bank P1, the second intermediate register bank P2, the fifth multiplier M5, and the clipping circuit CF form an integrator.

[0154] When the operation core of the IIR filter circuit 10 is an integrator, the first transfer function of the IIR filter circuit 10 satisfies the following formula two:

[0155]

[0156] Wherein, h1(z) is the first transfer function, y1(z) is the z-domain expression of the output signal y1(t) in the time domain, x1(z) is the z-domain expression of the input signal x1(t) in the time domain, b0 is the first triangular wave, and z represents the transformation factor of the z-transform.

[0157] Among them, the first transfer function represents the function that can be achieved when the operation core of the IIR filter circuit 10 is an integrator. When the operation core of the IIR filter circuit 10 is an integrator, the input signal x1(t) in the time domain can be the signal input to the IIR filter circuit 10, and the output signal y1(t) in the time domain can be the signal output by the IIR filter circuit 10.

[0158] Among them, y1(z) represents the signal obtained by transforming the output signal y1(t) in the time domain to the frequency domain through the Laplace transform and then to the z-domain through the Z-transform. x1(z) represents the signal obtained by transforming the input signal x1(t) in the time domain to the frequency domain through the Laplace transform and then to the z-domain through the Z-transform.

[0159] The coefficient of the first multiplier M1 is the first triangular wave. The first input terminal of the first multiplier M1 receives the command signal output from the fourth output terminal 4 of the selection circuit 203. The first multiplier multiplies the first triangular wave by the command signal to obtain the product of the first triangular wave and the command signal. The product is integrated by the integrator to obtain an integration result, and the integration result is divided by the area of the first triangular wave through the clipping circuit CF to obtain a quasi-sine wave signal.

[0160] Among them, the input signal x1(t) in the time domain in the above formula two can be the command signal, and the output signal y1(t) in the time domain in the above formula two can be the integration result. The command signal and the integration result satisfy the relationship shown in formula two.

[0161] Among them, when the area of the first triangular wave is 2 2N-2When the truncation bit number of the amplitude limiting and truncation circuit CF is set to 2N - 2, the arithmetic shift of 2N - 2 bits can be performed on the integration result through the amplitude limiting and truncation circuit CF, so as to implement the above division operation and obtain a quasi-sine wave signal.

[0162] Based on this, by configuring the operation core of the IIR filter circuit 10 as an integrator, the structure of the IIR filter circuit 10 is reused to process the command signal for sine transition to obtain a quasi-sine wave signal. Moreover, the generated quasi-sine wave signal and the first derivative of the quasi-sine wave signal are continuous, and the impact is small when input into the PID controller, which helps to improve the control effect of the PID controller.

[0163] In the above second stage, the selection circuit 203 is used to configure the operation core of the IIR filter circuit 10 through the second coefficient group, so that the first multiplier M1, the second multiplier M2, the third multiplier M3, the fourth multiplier M4, the fifth multiplier M5, the first intermediate register group P1, the second intermediate register group P2, the third intermediate register group P3, the amplitude limiting and truncation circuit CF, the first adder A1, the second adder A2, and the third adder A3 form a PID controller.

[0164] In some examples, the second coefficient group includes: the sixth coefficient, the seventh coefficient, the eighth coefficient, the ninth coefficient, and the tenth coefficient. The sixth coefficient is used to configure the first multiplier M1, the seventh coefficient is used to configure the second multiplier M2, the eighth coefficient is used to configure the third multiplier M3, the ninth coefficient is used to configure the fourth multiplier M4, and the tenth coefficient is used to configure the fifth multiplier M5.

[0165] Among them, the second coefficient group is determined according to a preset PID transfer function.

[0166] Among them, the preset PID transfer function is determined according to the requirements of the controlled object, and the preset PID transfer function is used to implement PID control.

[0167] When the operation core of the IIR filter circuit 10 is a PID controller, the second transfer function of the IIR filter circuit 10 satisfies the following formula three:

[0168]

[0169] Among them, h2(z) is the second transfer function, y2(z) is the z-domain expression of the output signal y2(t) in the time domain, x2(z) is the z-domain expression of the input signal x2(t) in the time domain, b6 is the sixth coefficient, b7 is the seventh coefficient, b8 is the eighth coefficient, a9 is the ninth coefficient, a 10 is the tenth coefficient, and z represents the transformation factor of the z-transform.

[0170] Among them, the second transfer function represents the function that can be achieved when the arithmetic core of the IIR filter circuit 10 is a PID controller. When the arithmetic core of the IIR filter circuit 10 is a PID controller, the input signal x2(t) in the time domain can be the signal input to the IIR filter circuit 10, and the output signal y2(t) in the time domain can be the signal output by the IIR filter circuit 10.

[0171] Among them, y2(z) represents the signal obtained by transforming the output signal y2(t) in the time domain to the frequency domain through the Laplace transform and then to the Z domain through the Z transform. x2(z) represents the signal obtained by transforming the input signal x2(t) in the time domain to the frequency domain through the Laplace transform and then to the Z domain through the Z transform.

[0172] The sinusoidal-like signal generated in the first stage is temporarily stored in the PID register bank 202. After the selection circuit 203 configures the arithmetic core of the IIR filter circuit 10 as a PID controller through the second coefficient group, the selection circuit 203 inputs the sinusoidal-like signal temporarily stored in the PID register bank 202 to the IIR filter circuit 10 through the first output terminal 4. Thus, the IIR filter circuit 10 uses the sinusoidal-like signal as the input of the PID controller, and after proportional, derivative, and integral operations, forms a control signal and inputs it to the controlled object, thereby realizing PID control. This sinusoidal-like signal is obtained by the sine transition of the command signal. The sinusoidal-like signal and the first derivative of the sinusoidal-like signal are continuous, which can improve the effect of PID control, ensure the stability of PID control and meet the performance requirements, and avoid system oscillation.

[0173] Among them, the input signal x2(t) in the time domain in the above formula three can be the sinusoidal-like signal, and the output signal y2(t) in the time domain in the above formula three can be the control signal. The sinusoidal-like signal and the control signal satisfy the relationship shown in formula three.

[0174] In some examples, the IIR filter circuit 10 further includes a distributor MUX1. The input end of the distributor MUX1 is connected to the second output end of the amplitude limiting and truncating circuit CF. The first output end of the distributor MUX1 is connected to the input end of the PID register bank 202, and the second output end of the distributor MUX1 outputs the control signal.

[0175] Among them, the distributor MUX1 is used to output the sinusoidal-like signal to the PID register bank 202 when the arithmetic core of the IIR filter circuit 10 is an integrator, or the distributor MUX1 is used to output the control signal when the arithmetic core of the IIR filter circuit 10 is a PID controller. Thus, in the first stage or the second stage, the IIR filter circuit 10 outputs the sinusoidal-like signal or the control signal respectively, avoiding signal confusion.

[0176] The embodiment of the present application also provides a method for generating a quasi-sine wave signal. Please refer to Figure 10 , Figure 10 which is a flowchart of a method for generating a quasi-sine wave signal provided in an embodiment of the present application. As Figure 10 shown, the method includes:

[0177] S101. Generate a first triangular wave according to preset parameters.

[0178] S102. Generate a quasi-sine wave signal according to the first triangular wave and an instruction signal.

[0179] Wherein, the amplitude of the quasi-sine wave signal is consistent with the instruction signal.

[0180] In some examples, the preset parameters include a transition time and an area parameter. The transition time is used to adjust the time span of the first triangular wave, and the area parameter is used to adjust the area of the first triangular wave. The area parameter satisfies the following formula (1):

[0181] S = 2 2N-2 Formula (1);

[0182] Wherein, S is the area parameter, and N is an integer greater than or equal to 0.

[0183] Based on the above exemplary description, please refer to Figure 11 , Figure 11 which is a flowchart of a method for generating a quasi-sine wave signal provided in an embodiment of the present application. As Figure 11 shown, the method includes:

[0184] S201. Multiply the first triangular wave by the instruction signal to obtain a product of the first triangular wave and the instruction signal.

[0185] S202. Integrate the product of the first triangular wave and the instruction signal to obtain an integration result.

[0186] S203. Divide the integration result by the area of the first triangular wave to obtain a quasi-sine wave signal.

[0187] By adjusting the transition time in the preset parameters, the time span of the first triangular wave can be adjusted. By configuring the area of the first triangular wave, that is, configuring the area parameter, the adjustable gear of the transition time can be changed. For example, as shown in Table 1 above, when N = 9, there are 9 adjustable gears for the transition time. For another example, if N = 12, there are 12 adjustable gears for the transition time. Thus, by adjusting the transition time of the first triangular wave, a quasi-sine wave signal with an adjustable transition time can be generated simply and quickly without a complex mechanism.

[0188] The embodiment of the present application also provides a PID control system. The PID control system includes a PID control circuit and a controlled object provided in any of the above embodiments.

[0189] An embodiment of the present application further provides a chip, which integrates the PID control circuit provided in any of the above embodiments.

[0190] An embodiment of the present application further provides an electronic device, including: the chip provided in the foregoing embodiment.

[0191] Those skilled in the art can understand that although some embodiments herein include certain features included in other embodiments, the combination of features of different embodiments means that it is within the scope of the present application and forms different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0192] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A proportional integral differential PID control circuit, characterized in that: The PID control circuit comprises: an infinite impulse response IIR filter circuit, a switching circuit and a triangular wave generating circuit, wherein the input end of the triangular wave generating circuit receives a preset parameter, the input end of the switching circuit receives a command signal, the output end of the triangular wave generating circuit is connected to the input end of the switching circuit, the output end of the switching circuit is connected to the input end of the IIR filter circuit, and the output end of the IIR filter circuit is connected to the input end of the switching circuit; The triangular wave generating circuit is used to generate a first triangular wave according to the preset parameters, and input the first triangular wave to the switching circuit; The switching circuit is used to configure the operation core of the IIR filter circuit as an integrator according to the first triangular wave, and switch the input of the IIR filter circuit to the instruction signal; The IIR filter circuit is used for generating a quasi-sine wave signal according to the instruction signal when the operation core of the IIR filter circuit is an integrator, and inputting the quasi-sine wave signal into the switching circuit, wherein the amplitude of the quasi-sine wave signal is consistent with the amplitude of the instruction signal; The switching circuit is further used to configure the operation core of the IIR filter circuit as a PID controller, and switch the input of the IIR filter circuit to the quasi-sine wave signal; The IIR filter circuit is also used to generate and output a control signal according to the quasi-sine wave signal when the operation core of the IIR filter circuit is a PID controller, and the control signal is used to perform PID control.

2. The PID control circuit according to claim 1, characterized in that: The switching circuit includes an integral register group, a PID register group and a selection circuit, wherein the integral register group is used to store a first coefficient group and receive and store the first triangular wave, the PID register group is used to store a second coefficient group and receive and store the quasi-sine wave signal, a first input end of the selection circuit receives the instruction signal, an output end of the triangular wave generation circuit is connected to an input end of the integral register group, an output end of the integral register group is connected to a second input end of the selection circuit, an input end of the PID register group is connected to an output end of the IIR filter circuit, an output end of the PID register group is connected to a third input end of the selection circuit, and an output end of the selection circuit is connected to an input end of the IIR filter circuit; The selection circuit is used to select the integration register group so that the operation core of the IIR filter circuit is configured as an integrator using the first coefficient group and the first triangular wave, and input the instruction signal to the IIR filter circuit; or, The selection circuit is used to select the PID register group so that the operation core of the IIR filter circuit is configured as a PID controller using the second coefficient group, and the sine-wave-like signal is input to the IIR filter circuit.

3. The PID control circuit according to claim 2, characterized in that: The IIR filter circuit includes a first multiplier, a second multiplier, a third multiplier, a fourth multiplier, a fifth multiplier, a first intermediate register group, a second intermediate register group, a third intermediate register group, a limiter circuit, a first adder, a second adder and a third adder; The first output end of the selection circuit is connected to the first input end of the first multiplier, the second output end of the selection circuit is connected to the second input end of the first multiplier, the output end of the first multiplier is connected to the first input end of the first adder, the second input end of the first adder is connected to the output end of the first intermediate register group, the third input end of the first adder is connected to the output end of the second intermediate register group, the output end of the first adder is connected to the input end of the limiter circuit, the first output end of the limiter circuit is connected to the input end of the first intermediate register group, the second output end of the limiter circuit outputs the quasi-sine wave signal or the control signal, the second output end of the limiter circuit is also connected to the first input end of the fourth multiplier, the second input end of the fourth multiplier is connected to the third output end of the selection circuit, the output end of the fourth multiplier is connected to the first input end of the third adder, and the second output end of the third adder is connected to the first input end of the third adder. an input end connected to the output end of the third multiplier, an output end of the third adder connected to the input end of the third intermediate register group, an output end of the third intermediate register group connected to the first input end of the second adder, a second input end of the second adder connected to the output end of the second multiplier, a third input end of the second adder connected to the output end of the fifth multiplier, an output end of the second adder connected to the input end of the second intermediate register group, a first input end of the second multiplier connected to the first output end of the selection circuit, a second input end of the second multiplier connected to the fourth output end of the selection circuit, a first input end of the third multiplier connected to the first output end of the selection circuit, a second input end of the third multiplier connected to the fifth output end of the selection circuit, a first input end of the fifth multiplier connected to the second output end of the limiter circuit, and a second input end of the fifth multiplier connected to the sixth output end of the selection circuit; The selection circuit is used to configure the operation core of the IIR filter circuit through the first triangular wave and the first coefficient group, so that the first multiplier, the first adder, the first intermediate register group, the second intermediate register group, the fifth multiplier and the limiter circuit form an integrator; or, The selection circuit is used to configure the operation core of the IIR filter circuit through the second coefficient group, so that the first multiplier, the second multiplier, the third multiplier, the fourth multiplier, the fifth multiplier, the first intermediate register group, the second intermediate register group, the third intermediate register group, the limit clipping circuit, the first adder, the second adder and the third adder form a PID controller.

4. The PID control circuit according to claim 3, characterized in that: The first coefficient group includes: a first coefficient, a second coefficient, a third coefficient, a fourth coefficient and a fifth coefficient, the first coefficient is used to configure a first multiplier, the second coefficient is used to configure a second multiplier, the third coefficient is used to configure a third multiplier, the fourth coefficient is used to configure a fourth multiplier, and the fifth coefficient is used to configure a fifth multiplier; Among them, the first coefficient is the first triangular wave, the second coefficient, the third coefficient, and the fourth coefficient are all 0, and the fifth coefficient is 1.

5. The PID control circuit according to claim 3, characterized in that: The second coefficient group includes: a sixth coefficient, a seventh coefficient, an eighth coefficient, a ninth coefficient and a tenth coefficient, the sixth coefficient is used to configure the first multiplier, the seventh coefficient is used to configure the second multiplier, the eighth coefficient is used to configure the third multiplier, the ninth coefficient is used to configure the fourth multiplier, and the tenth coefficient is used to configure the fifth multiplier; The second coefficient group is determined according to a preset PID transfer function.

6. The PID control circuit according to any one of claims 3 to 5, characterized in that: The IIR filter circuit further comprises a distributor, wherein an input end of the distributor is connected to a second output end of the amplitude limiting circuit, a first output end of the distributor is connected to an input end of the PID register group, and a second output end of the distributor outputs the control signal; The distributor is used to output the quasi-sine wave signal to the PID register group when the operation core of the IIR filter circuit is an integrator, or, The distributor is used to output the control signal when the operation core of the IIR filter circuit is a PID controller.

7. The PID control circuit according to any one of claims 3 to 5, characterized in that: The preset parameters include a transition time and an area parameter, wherein the transition time is used to adjust the time span of the first triangular wave, and the area parameter is used to adjust the area of ​​the first triangular wave, and the area parameter satisfies formula 1; wherein formula 1 is: S=2 2N-2 ; Wherein, S is the area parameter, and N is an integer greater than or equal to 0.

8. A method for generating a quasi-sine wave signal, characterized in that: The method comprises: generating a first triangular wave according to preset parameters; A quasi-sine wave signal is generated according to the first triangular wave and the command signal, and the amplitude of the quasi-sine wave signal is consistent with the command signal.

9. The method according to claim 8, characterized in that The preset parameters include a transition time and an area parameter, wherein the transition time is used to adjust the time span of the first triangular wave, and the area parameter is used to adjust the area of ​​the first triangular wave, and the area parameter satisfies formula 1; wherein formula 1 is: S=2 2N-2 ; Wherein, S is the area parameter, and N is an integer greater than or equal to 0.

10. The method according to claim 8 or 9, characterized in that: The step of generating a quasi-sine wave signal according to the first triangular wave and the command signal comprises: multiplying the first triangular wave and the command signal to obtain a product of the first triangular wave and the command signal; Integrating the product of the first triangular wave and the command signal to obtain an integration result; The integration result is divided by the area of ​​the first triangular wave to obtain the quasi-sine wave signal.

11. A PID control system, characterized in that: The PID control system comprises a PID control circuit as described in any one of claims 1 to 7 and a controlled object.

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