Bridge and bridge circuit thereof

Abstract

The invention discloses a bridge and a bridge circuit thereof, the bridge circuit comprises an SPI interface, a bridge conversion chip, an isolation circuit, an enable circuit and a UART interface, the SPI interface is coupled and electrically connected with the bridge conversion chip, and the SPI interface is also electrically connected with an SPI interface of a host of a battery management system. A data port of the bridging conversion chip is coupled and electrically connected with the UART interface through an isolation circuit, the bridging conversion chip is further electrically connected with a data sending port of the UART interface through a corresponding enable circuit, the UART interface is further electrically connected with a UART interface of the AFE, and the host is used for configuring configuration parameters for the UART interface to communicate with the preset AFE; the SPI interface is used for transmitting an SPI signal between the host and the bridging conversion chip; the bridging conversion chip is used for converting UART signals and SPI signals; the isolation circuit is used for carrying out noise interference isolation on the UART signal converted by the bridging conversion chip; the enabling circuit is used for enabling a data sending port of the UART interface; and the UART is used for transmitting a UART signal between the AFE and the bridging conversion chip.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic device connection, and particularly to a bridge and its bridging circuit. Background Art

[0002] In related technologies, a battery acquisition chip AFE usually relies on a self - equipped dedicated bridge chip to communicate with a host. However, there are significant differences in the physical forms of these bridge chips, which leads to the need for the host to change and adjust its own hardware when adapting to different AFEs. This not only increases the complexity and cost of system integration, but also brings many inconveniences when upgrading or replacing the AFE, seriously affecting the development efficiency and flexibility of products.

[0003] Aiming at the problem that the bridge in the existing related technologies cannot meet the bridging requirements of different AFEs and hosts, no effective solution has been proposed yet. Summary of the Invention

[0004] In view of this, it is necessary to provide a bridge and its bridging circuit to at least solve the problem that the bridge in the related technologies cannot meet the bridging requirements of different AFEs and hosts.

[0005] In a first aspect, a technical solution adopted by the present invention is as follows: A bridging circuit of a bridge includes an SPI interface, a bridge conversion chip, an isolation circuit, an enabling circuit, and a UART interface. The SPI interface is electrically coupled to the bridge conversion chip, and the SPI interface is also electrically connected to the SPI interface of the host of the battery management system. The data port of the bridge conversion chip is electrically coupled to the UART interface through the isolation circuit. The bridge conversion chip is also electrically connected to the data sending port of the UART interface through the corresponding enabling circuit. The UART interface is also electrically connected to the UART interface of the AFE. Among them, the host is used to configure configuration parameters for the UART interface to communicate with a preset AFE; the SPI interface is used to transmit the SPI signal sent by the host to the bridge conversion chip, or transmit the SPI signal converted by the bridge conversion chip to the host; the bridge conversion chip is used to convert the received SPI signal into a UART signal, or convert the received UART signal into an SPI signal; the isolation circuit is used to isolate the noise interference of the UART signal converted by the bridge conversion chip; the enabling circuit is used to enable the data sending port of the UART interface to transmit the UART signal converted by the bridge conversion chip to the AFE; the UART is used to transmit the UART signal between the AFE and the bridge conversion chip.

[0006] In some of these embodiments, a power supply module is further included. The power supply module includes a linear voltage regulator chip. The input end of the linear voltage regulator chip is electrically connected to the battery port of the SPI interface. The output end of the linear voltage regulator chip is electrically connected to the external power supply I / O port of the bridging conversion chip through a series-connected first coupling resistor. Wherein, the linear voltage regulator chip is used to convert the first voltage output by the battery management system into a preset second voltage.

[0007] In some of these embodiments, the linear voltage regulator chip includes a three-terminal voltage regulator chip of the LD1117AG-3.3V model.

[0008] In some of these embodiments, the bridging conversion chip includes a dual SPI / UART bridging chip of the PI model.

[0009] In some of these embodiments, the isolation circuit includes a first isolation circuit and a second isolation circuit. The data port of the bridging conversion chip includes multiple groups of transceiver ports electrically connected to a plurality of the UART interfaces. Each two groups of the transceiver ports are docked with one of the UART interfaces. Each group of the transceiver ports includes a first transmission port and a first reception port. The two first transmission ports in each two groups of the transceiver ports are electrically connected to the transmission port of the corresponding UART interface through a first isolation circuit. The two first reception ports in each two groups of the transceiver ports are docked with the reception port of the corresponding UART interface through a second isolation circuit.

[0010] In some of these embodiments, the first isolation circuit includes a first isolation transformer. The first isolation transformer includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is electrically connected to the cathode of a first ESD protection diode and a first resistor respectively. The second input terminal is electrically connected to the cathode of a second ESD protection diode and a second resistor respectively. The other ends of the first resistor and the second resistor are electrically connected to a corresponding first transmission port respectively. The anodes of the first ESD protection diode and the second ESD protection diode are grounded. A first capacitor is connected in series between the first input terminal and the first output terminal. A second capacitor is connected in series between the second input terminal and the second output terminal. The first output terminal and the second output terminal are also electrically connected to the transmission ports corresponding to the corresponding UART interfaces respectively. The second isolation circuit includes an ESD protection diode and a second isolation transformer. The second isolation transformer includes a third input terminal, a fourth input terminal, a third output terminal, and a fourth output terminal. The third input terminal is electrically connected to the first anode of the ESD protection diode, the output terminal of a first RC filter circuit, and a third resistor respectively. The fourth input terminal is electrically connected to the second anode of the ESD protection diode, the output terminal of a second RC filter circuit, and a fourth resistor respectively. The other ends of the third resistor and the fourth resistor are both grounded. The input terminals of the first RC filter circuit and the second RC filter circuit are electrically connected to a corresponding first reception port respectively. A third capacitor is connected in series between the third input terminal and the third output terminal. A fourth capacitor is connected in series between the fourth input terminal and the fourth output terminal. The third output terminal and the fourth output terminal are also electrically connected to the reception ports corresponding to the corresponding UART interfaces respectively.

[0011] In some of these embodiments, both the first ESD protection diode and the second ESD protection diode include unidirectional electrostatic protection diodes of the TPESD5V0U1UA model. The ESD protection diode includes a bidirectional two-channel electrostatic protection diode of the PESD1CAN model, and / or both the first isolation transformer and the second isolation transformer include common mode inductors.

[0012] In some of these embodiments, the isolation circuit includes an ESD electrostatic protection diode and an isolation transformer. The isolation transformer includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is electrically connected to the first anode of the ESD electrostatic protection diode, the output terminal of the first RC filter circuit, and a first resistor respectively. The second input terminal is electrically connected to the second anode of the ESD electrostatic protection diode, the output terminal of the second RC filter circuit, and a second resistor respectively. The other ends of the first resistor and the second resistor are both grounded. The input terminals of the first RC filter circuit and the second RC filter circuit are electrically connected to a corresponding data port respectively. A first capacitor is connected in series between the first input terminal and the first output terminal, and a second capacitor is connected in series between the second input terminal and the second output terminal. The first output terminal and the second output terminal are also electrically connected to the corresponding data ports of the UART interfaces respectively.

[0013] In some of these embodiments, the ESD electrostatic protection diode includes a bidirectional two-channel electrostatic protection diode of the PESDCAN model, and / or the isolation transformer includes a common-mode inductor.

[0014] In some of these embodiments, two of the first transmission ports in every two groups of the transceiver ports are electrically connected to one enabling circuit. The enabling circuit includes two switching tubes. The controlled ends of the two switching tubes are both electrically connected to an enabling port of the bridge conversion chip. The input ends of the switching tubes are electrically connected to the cathode of a first diode and one of the first transmission ports respectively. The output ends of the switching tubes are electrically connected to the anode of the first diode and grounded. Among them, the switching tube is configured to control the on / off of the input end and the output end of the switching tube according to the level of the enabling signal output from the enabling port received by the input end; when the input end and the output end of the switching tube are disconnected, the corresponding first transmission port is enabled. When the input end and the output end of the switching tube are connected, the corresponding first transmission port is disabled.

[0015] In some of these embodiments, each enabling port is also electrically connected to the first voltage output port of the battery management system through a series-connected Schottky diode. Among them, the Schottky diode is used to rectify the enabling signal output along an enabling port of the bridge conversion chip.

[0016] In a second aspect, an embodiment of the present application further provides a bridge for communication connection between the host of the battery management system and the battery acquisition chip AFE, including a bridge plug. A bridge circuit is provided in the bridge plug. The bridge circuit includes the bridge circuit of the bridge in the first aspect.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: The embodiment of the present application provides a bridge and its bridging circuit. By setting an SPI interface, a bridging conversion chip, an isolation circuit, an enabling circuit, and a UART interface, and configuring the UART interface with configuration parameters for communicating with a preset AFE by the host, the SPI signal sent by the host is transmitted to the bridging conversion chip through the SPI interface, or the SPI signal converted by the bridging conversion chip is transmitted to the host. And the received SPI signal is converted into a UART signal by the bridging conversion chip, or the received UART signal is converted into an SPI signal; and the isolation circuit is used to isolate the noise interference of the UART signal converted by the bridging conversion chip, and the enabling circuit enables the data sending port of the UART interface to transmit the UART signal converted by the bridging conversion chip to the AFE, and connect with the AFE through the UART, and transmit the UART signal between the AFE and the bridging conversion chip, so as to realize the adaptation and modification of communication parameters through the host software, realize the adaptation of the host to communicate with different AFEs without changing the hardware, simplify the adaptation process between the AFE and the host, improve the scalability and compatibility of the system, and solve the problem that the bridge in the related technology cannot meet the bridging of different AFEs and the host. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is the structural block diagram of the bridging circuit in the embodiment of the present application; Figure 2 is the topological circuit diagram of the bridging conversion chip and the SPI interface in the embodiment of the present application; Figure 3 is the topological diagram of the isolation circuit and the UART interface in the embodiment of the present application; Figure 4 is the topological diagram of the enabling circuit in the embodiment of the present application; Figure 5 is the topological diagram of the voltage module in the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0020] It should be noted that when a component is referred to as "mounted on" another component, it can be directly mounted on the other component or there may also be an intermediate component. When a component is considered to be "disposed on" another component, it can be directly disposed on the other component or there may be an intermediate component at the same time. When a component is considered to be "fixed to" another component, it can be directly fixed to the other component or there may be an intermediate component at the same time.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this invention belongs. The terms used in the description of the present invention herein are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more of the related listed items.

[0022] Refer to Figures 1 to 5 , an embodiment of the present application provides a bridging circuit of a bridge, including an SPI interface 100, a bridge conversion chip 200, an isolation circuit 300, an enable circuit 400, and a UART interface 500. The SPI interface 100 is coupled and electrically connected to the bridge conversion chip 200. The SPI interface 100 is also electrically connected to the SPI interface of the host of the battery management system. The data port of the bridge conversion chip 200 is coupled and electrically connected to the UART interface 500 through the isolation circuit 300. The bridge conversion chip 200 is also electrically connected to the data sending port of the UART interface 500 through the corresponding enable circuit 400. The UART interface 500 is also electrically connected to the UART interface of the AFE. Among them, The host is used to configure configuration parameters for the UART interface 500 to communicate with a preset AFE.

[0023] In this embodiment, the host is disposed on one side of the Battery Management System (BMS) and is also the control core of the battery management system. The host communicates with the battery acquisition chip AFE through the bridging circuit and the corresponding bridge of the embodiment of the present application, and realizes the transmission of battery parameters (voltage, temperature, humidity) collected by the AFE.

[0024] In this embodiment, the bridge conversion chip 200 is initialized and configured through software on the host side, and the corresponding software driver and communication configuration parameters (such as baud rate, data frame, clock, start bit) are updated after replacing the AFE, so as to establish a communication link between the host and the corresponding AFE, quickly realize normal communication between the new AFE and the host, and meet the communication requirements of the host and different AFEs without changing the hardware facilities.

[0025] The SPI interface 100 is used to transmit the SPI signals sent by the host to the bridge conversion chip 200, or to transmit the SPI signals converted by the bridge conversion chip 200 to the host.

[0026] The SPI interface 100 is illustrated by the SPI interface connected to the host (refer to Figure 2 U42 in). The pin order of this SPI interface can be adapted and modified according to requirements. In this embodiment, the pins of the SPI interface include the power supply port VBAT, the bridge chip enable / disable port MCU_SHDNB, the chip select port CSB, the SPI data output port MISO, the SPI data input port MOSI, the interrupt request port IRQB, the clock port SCK, and the signal ground GND.

[0027] The bridge conversion chip 200 is used to convert the received SPI signals into UART signals, or to convert the received UART signals into SPI signals.

[0028] In this embodiment, the bridge conversion chip 200 includes a dual SPI / UART bridge chip of the PI22101 model. Refer to Figure 2 . The power supply port VBAT of the bridge conversion chip 200 is electrically connected to the power supply port VBAT of the SPI interface, and is also grounded through a filtering unit composed of a parallel capacitor C63 and a capacitor C64. The enable / disable port SHDNB of the bridge conversion chip 200 is electrically connected to the bridge chip enable / disable port MCU_SHDNB of the SPI interface through a series coupling resistor R40, and is also electrically connected to a filtering capacitor C60. The external power supply I / O port VIO of the bridge conversion chip 200 is electrically connected to the ground through parallel capacitors C61 and C62, and is electrically connected to the output terminal of the power supply module 600 after being electrically connected to a first coupling resistor R59. The MOSI port of the bridge conversion chip 200 is electrically connected to the SPI data input port MOSI of the SPI interface. The MISO port of the bridge conversion chip 200 is electrically connected to the SPI data output port MISO of the SPI interface, and is grounded through an electrically connected resistor R41.

[0029] In this embodiment, when the bridge transmits the signals sent by the host to the AFE, the bridge conversion chip 200 is used to convert the SPI signals sent by the host into UART signals and transmit them to the AFE along the corresponding UART interface 500. When the bridge uploads the battery parameters collected by the AFE to the host, the bridge conversion chip is used to convert the UART signals generated by the AFE into SPI signals and transmit them to the host along the SPI interface 100.

[0030] The isolation circuit 300 is used to isolate the noise interference of the UART signals converted by the bridge conversion chip 200.

[0031] In this embodiment, the isolation circuit 300 is used to perform electrostatic shielding isolation and remove clutter on the signal sent from the bridge conversion chip 200 to the AFE.

[0032] The enabling circuit 400 is used to enable the data sending port of the UART interface 500 to transmit the UART signal converted by the bridge conversion chip 200 to the AFE.

[0033] In this embodiment, when the bridge and the AFE perform data reception and transmission, the enabling circuit operates, that is, by enabling the enabling circuit 400, enabling the corresponding data sending port of the UART interface 500, and then starting to send data according to the preset parameters (baud rate, number of data bits, stop bits, parity bits, etc.); in this embodiment, before the corresponding data sending port is enabled, the data to be sent is written into the transmit FIFO of the bridge conversion chip 200. When the corresponding data sending port is enabled (or the corresponding UART is enabled), data transmission starts until there is no data in the transmit FIFO.

[0034] The UART 500 is used to transmit the UART signal between the AFE and the bridge conversion chip 200.

[0035] In the above bridge circuit, the host configures the configuration parameters for communicating with the preset AFE for the UART interface 500, transmits the SPI signal sent by the host to the bridge conversion chip 200 through the SPI interface 100, or transmits the SPI signal converted by the bridge conversion chip 200 to the host; the bridge conversion chip 200 performs the conversion between the SPI signal and the UART signal, and the isolation circuit 300 is used to isolate the noise interference of the UART signal converted by the bridge conversion chip 200; the enabling circuit 400 is used to enable the data sending port of the UART interface 500 to transmit the UART signal converted by the bridge conversion chip 200 to the AFE; connect to the AFE through the UART 500 and transmit the UART signal between the AFE and the bridge conversion chip 200, realize the adaptation and modification of communication parameters through the host software, realize the adaptation of the host and different AFEs for communication without changing the hardware, simplify the adaptation process of the AFE and the host, improve the scalability and compatibility of the system, and solve the problem that the bridge in the related technology cannot meet the bridging of different AFEs and the host.

[0036] It should be noted that in this embodiment, the dedicated chip part is encapsulated inside the plug. One end of the plug is provided with an interface for SPI connection with the host, and the other end has an interface for UART connection with the AFE. Through this design, when the AFE needs to be changed, the user only needs to replace the corresponding plug and make corresponding adjustments to the software of the host, without making any changes to the host hardware. This greatly simplifies the adaptation process between the AFE and the host, and improves the scalability and compatibility of the system.

[0037] In this embodiment, during the manufacturing process of the bridge, a dedicated chip with specific functions (corresponding to the bridge conversion chip 200) is encapsulated inside the bridge according to a predetermined circuit design, ensuring that the interface pins of the SPI module 100 at one end of the bridge are completely compatible with the SPI interface of the host in terms of physical connection and electrical characteristics, and the interface pins of the UART module 500 at the other end can be stably connected to the UART interface of the AFE; when initially connecting, both ends of the bridge are respectively connected to the host and the selected AFE, and the chip inside the plug is initialized and configured through the software on the host side to establish a communication link between the host and the AFE; when it is necessary to replace the AFE with a different model or specification, by disconnecting the original bridge from the host and the AFE, and then selecting the plug corresponding to the new AFE and reconnecting it to the host and the new AFE; subsequently, updating the corresponding software driver or configuration parameters on the host can quickly realize the normal communication between the new AFE and the host; when replacing the AFE connection in the bridge implemented in this application, there is no need to perform any soldering, disassembling or modifying operations on the hardware circuit of the host, which simplifies the adaptation process between the AFE and the host and improves the scalability and compatibility of the system.

[0038] In some of the embodiments, referring to Figure 5 , the bridge circuit further includes a power module, and the power module includes a linear voltage regulator chip U43. The input terminal (VIN) of the linear voltage regulator chip U43 is electrically connected to the battery port (VBAT) of the SPI interface 100, and the output terminal (VOUT) of the linear voltage regulator chip U43 is electrically connected to the external power I / O port (VIO) of the bridge conversion chip 200 through a series-connected first coupling resistor R59. Among them, the linear voltage regulator chip U43 is used to convert the first voltage (VBAT) output by the battery management system into a preset second voltage (VIO_3P3V).

[0039] In some of the alternative embodiments, the linear voltage regulator chip U43 includes, but is not limited to, a three-terminal voltage regulator chip of the LD1117AG-3.3V model.

[0040] In some of the embodiments, referring to Figures 2 to 4, the isolation circuit includes a first isolation circuit and a second isolation circuit. The data ports of the bridging conversion chip 200 include multiple groups of transceiver ports electrically connected to a plurality of UART interfaces 500. Each two groups of transceiver ports are docked with one UART interface 500. Each group of transceiver ports includes a first transmission port (TX0N, TX0P, TX1N, TX1P) and a first reception port (RX0N, RX0P, RX1N, RX1P). Two first transmission ports (TX0N and TX1N, TX0P and TX1P) in each two groups of transceiver ports are electrically connected to the corresponding transmission port of the corresponding UART interface 500 through a first isolation circuit. Two first reception ports (EX_TX0N and EX_TX1N, EX_TX0P and EX_TX1P) in each two groups of transceiver ports are docked with the reception port of the corresponding UART interface 500 through a second isolation circuit.

[0041] In this embodiment, referring to Figure 3 , the first isolation circuit includes a first isolation transformer (referring to Figure 3 XFR_0 and XFR_1 in Figure 3 ). The first isolation transformer includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is electrically connected to the cathodes of the first ESD protection diodes (referring to Figure 3 D2 and D9 in Figure 3 ) and the first resistors (referring to Figure 3 resistor R18 and resistor R31 in Figure 3 ). The second input terminal is electrically connected to the cathodes of the second ESD protection diodes (referring to Figure 3 D3 and D10 in Figure 3 ) and the second resistors (referring to Figure 3 resistor R19 and resistor R32 in Figure 3 ). The other ends of the first resistor and the second resistor are respectively electrically connected to a corresponding first transmission port (the first resistor corresponds to the first transmission ports TX0P and TX1P, and the first transmission ports corresponding to the second resistor are TX0N and TX1N). The anodes of the first ESD protection diode and the second ESD protection diode are grounded. A first capacitor (referring to Figure 3 C38 and C48 in Figure 3 ) is connected in series between the first input terminal and the first output terminal. A second capacitor (referring to Figure 3 C39 and C49 in Figure 3 ) is connected in series between the second input terminal and the second output terminal. The first output terminal and the second output terminal are also respectively electrically connected to the corresponding transmission ports of the corresponding UART interface 500 (the transmission ports corresponding to the first output terminal are EX_TX0P and EX_TX1P, and the transmission ports corresponding to the second output terminal are EX_TX0N and EX_TX1N); the second isolation circuit includes ESD protection diodes (referring to Figure 3 D8, D1 in Figure 3 ) and a second isolation transformer (referring to Figure 3XFR_2 and XFR_3 in it), the second isolation transformer includes a third input terminal, a fourth input terminal, a third output terminal and a fourth output terminal. The third input terminal is respectively connected to the first anode of the ESD electrostatic protection diode, the output terminal of the first RC filter circuit (in this embodiment, the first RC filter circuit includes a filter circuit composed of resistor R27 and capacitor C52 or a filter circuit composed of resistor R13 and capacitor C44) (corresponding to the end of resistor R27 far from capacitor C52 or the end of resistor R13 far from the end electrically connected to capacitor C44) and the third resistor (refer to Figure 3 resistors R28 and R15 in it), the fourth input terminal is respectively connected to the second anode of the ESD electrostatic protection diode, the output terminal of the second RC filter circuit (in this embodiment, the second RC filter circuit includes a filter circuit composed of resistor R29 and capacitor C53 or a filter circuit composed of resistor R16 and capacitor C45) and the fourth resistor (refer to Figure 3 resistors R30 and R17 in it). The other ends of the third resistor and the fourth resistor are both grounded. The input terminals of the first RC filter circuit and the second RC filter circuit are respectively electrically connected to a corresponding first receiving port (the first receiving ports corresponding to the first RC filter circuit are RX0P and RX1P, and the first receiving ports corresponding to the second RC filter circuit are RX0N and RX1N). A third capacitor (refer to Figure 3 capacitors C46 and C36 in it) is connected in series between the third input terminal and the third output terminal, and a fourth capacitor (refer to Figure 3 capacitors C47 and C37 in it) is connected in series between the fourth input terminal and the fourth output terminal. The third output terminal and the fourth output terminal are also respectively electrically connected to the receiving ports corresponding to the corresponding UART interface 500 (the receiving ports electrically connected to the third output terminal are EX_RX0P and EX_RX1P, and the receiving ports electrically connected to the fourth output terminal are EX_RX0N and EX_RX1N).

[0042] In some alternative embodiments, both the first ESD protection diode and the second ESD protection diode include, but are not limited to, unidirectional electrostatic protection diodes of the TPESD5V0U1UA model.

[0043] In some alternative embodiments, the ESD electrostatic protection diode includes, but is not limited to, bidirectional two-channel electrostatic protection diodes of the PESD1CAN model.

[0044] In some alternative embodiments, both the first isolation transformer and the second isolation transformer include, but are not limited to, common mode inductors.

[0045] In some of these embodiments, two first transmission ports in each two groups of transceiver ports are electrically connected to an enabling circuit 400. The enabling circuit 400 includes two switching tubes (in this embodiment, the two switching tubes are integrated into a dual-channel switching tube, refer toFigure 4 U34 and U41 in), the controlled ends of both switching tubes are electrically connected to an enable port of the bridging conversion chip 200 (refer to Figure 2 and Figure 4 VUART0 and VUART1 in), the input ends of the switching tubes are respectively electrically connected to the cathodes of the first diodes (refer to Figure 4 U32, U33, U39 and U40 in) and a first transmission port, and the output ends of the switching tubes are electrically connected to the anodes of the first diodes and grounded. Among them, The switching tube is used to control the on / off of the input end and the output end of the switching tube according to the level of the enable signal output by the enable port connected to the input end.

[0046] When the input end and the output end of the switching tube are disconnected, the corresponding first transmission port is enabled. When the input end and the output end of the switching tube are connected, the corresponding first transmission port is disabled.

[0047] In this embodiment, it should be noted that the switching tubes in the embodiments of the present application include but are not limited to triodes, MOS tubes, and field effect transistors. And according to the content disclosed in the present application, those skilled in the art can easily think of modifying the switching tubes disclosed in the present application into an enable circuit adapted to the specific selection of the switching tubes according to the specific selection of the switching tubes. Therefore, whether the switching tube is an NPN-type or PNP-type triode, or an N-channel or P-channel switching MOS tube, or an N-type or P-type field effect transistor, the present application can be realized, and it is not limited in the embodiments of the present application; in some alternative embodiments, the two switching tubes are integrated into a dual-channel switching tube, and preferably a dual-channel NPN triode BCM847.

[0048] In some embodiments, each enable port (refer to Figure 2 the network labels VUART0 and VUART1 in) is also electrically connected to the first voltage output port (corresponding to VBAT) of the battery management system through a series-connected Schottky diode (refer to Figure 2 D11 and D12 in), where the Schottky diode is used to rectify the enable signal output along an enable port of the bridging conversion chip 200.

[0049] The embodiment of the present application also provides a bridge for communication connection between the host of the battery management system BSM and the battery acquisition chip AFE, including a bridge plug, and a bridge circuit is arranged in the bridge plug, and the bridge circuit includes the bridge circuit of the bridge in the above embodiment.

[0050] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered that the scope described in this specification is covered.

[0051] Those of ordinary skill in the art of this technology should recognize that the above embodiments are only used to illustrate the present invention and not to limit the present invention. As long as appropriate changes and variations made to the above embodiments fall within the scope of the spirit of the present invention, they fall within the scope of protection required by the present invention.

Claims

1. A bridge circuit of a bridge device, characterized in that: The invention comprises an SPI interface (100), a bridge conversion chip (200), an isolation circuit (300), an enabling circuit (400) and a UART interface (500), wherein the SPI interface (100) is coupled and electrically connected to the bridge conversion chip (200), the SPI interface (100) is also electrically connected to the SPI interface of a host of a battery management system, the data port of the bridge conversion chip (200) is coupled and electrically connected to the UART interface (500) through the isolation circuit (300), the bridge conversion chip (200) is also electrically connected to the data transmission port of the UART interface (500) through the corresponding enabling circuit (400), and the UART interface (500) is also electrically connected to the UART interface of an AFE, wherein: The host is used to configure configuration parameters for the UART interface (500) to communicate with a preset AFE; The SPI interface (100) is used to transmit an SPI signal sent by a host to the bridge conversion chip (200), or to transmit an SPI signal converted by the bridge conversion chip (200) to the host; The bridge conversion chip (200) is used to convert a received SPI signal into a UART signal, or to convert a received UART signal into a SPI signal; The isolation circuit (300) is used to isolate noise interference from the UART signal converted by the bridge conversion chip (200); The enabling circuit (400) is used to enable the data transmission port of the UART interface (500) so as to transmit the UART signal converted by the bridge conversion chip (200) to the AFE; The UART (500) is used to transmit UART signals between the AFE and the bridge conversion chip (200).

2. The bridge circuit of the bridge device according to claim 1, characterized in that: It also includes a power module, the power module including a linear voltage regulator chip, the input end of the linear voltage regulator chip is electrically connected to the battery port of the SPI interface (100), and the output end of the linear voltage regulator chip is electrically connected to the external power I / O port of the bridge conversion chip (200) via a first coupling resistor in series, wherein the linear voltage regulator chip is used to convert a first voltage output by the battery management system into a preset second voltage.

3. The bridge circuit of the bridge device according to claim 2, characterized in that: The linear voltage regulator chip includes a three-terminal voltage regulator chip of model LD1117AG-3.3V.

4. The bridge circuit of the bridge device according to claim 1, characterized in that: The bridge conversion chip (200) comprises a dual SPI / UART bridge chip of model PI22101.

5. The bridge circuit of the bridge device according to claim 1, characterized in that: The isolation circuit comprises a first isolation circuit and a second isolation circuit; the data port of the bridge conversion chip (200) comprises a plurality of groups of transceiver ports electrically connected to a plurality of the UART interfaces (500); each two groups of the transceiver ports are connected to one UART interface (500); each group of the transceiver ports comprises a first transmitting port and a first receiving port; two of the first transmitting ports in each two groups of the transceiver ports are electrically connected to the corresponding transmitting port of the UART interface (500) via a first isolation circuit; and two of the first receiving ports in each two groups of the transceiver ports are connected to the corresponding receiving port of the UART interface (500) via a second isolation circuit.

6. The bridge circuit of the bridge device according to claim 5, characterized in that: The first isolation circuit comprises a first isolation transformer, the first isolation transformer comprises a first input end, a second input end, a first output end and a second output end, the first input end is electrically connected to the cathode of a first ESD discharge protection diode and a first resistor respectively, the second input end is electrically connected to the cathode of a second ESD discharge protection diode and the second resistor respectively, the other ends of the first resistor and the second resistor are electrically connected to a corresponding first transmission port respectively, the anodes of the first ESD discharge protection diode and the second ESD discharge protection diode are connected to the ground, a first capacitor is connected in series between the first input end and the first output end, a second capacitor is connected in series between the second input end and the second output end, and the first output end and the second output end are also electrically connected to the corresponding transmission port of the corresponding UART interface (500); the second isolation circuit comprises an ESD electrostatic protection diode A diode and a second isolation transformer, the second isolation transformer comprising a third input end, a fourth input end, a third output end and a fourth output end, the third input end being electrically connected to the first anode of the ESD electrostatic protection diode, the output end of the first RC filter circuit and the third resistor respectively, the fourth input end being electrically connected to the second anode of the ESD electrostatic protection diode, the output end of the second RC filter circuit and the fourth resistor respectively, the other ends of the third resistor and the fourth resistor are both grounded, the input ends of the first RC filter circuit and the second RC filter circuit are electrically connected to a corresponding first receiving port respectively, a third capacitor is connected in series between the third input end and the third output end, a fourth capacitor is connected in series between the fourth input end and the fourth output end, and the third output end and the fourth output end are also electrically connected to the corresponding receiving port of the corresponding UART interface (500) respectively.

7. The bridge circuit of the bridge device according to claim 5, characterized in that: The first ESD discharge protection diode and the second ESD discharge protection diode both include a unidirectional electrostatic protection diode of the TPESD5V0U1UA model, the ESD electrostatic protection diode includes a bidirectional two-channel electrostatic protection diode of the PESD1CAN model, and / or the first isolation transformer and the second isolation transformer both include a common-mode inductor.

8. The bridge circuit of the bridge device according to claim 5, characterized in that: Two of the first transmission ports in each two groups of the transceiver ports are electrically connected to one enabling circuit (400), the enabling circuit (400) comprising two switch tubes, the controlled ends of the two switch tubes are electrically connected to an enabling port of the bridge conversion chip (200), the input ends of the switch tubes are electrically connected to the cathode of the first diode and one of the first transmission ports, respectively, and the output ends of the switch tubes are electrically connected to the anode of the first diode and to the ground, wherein: The switch tube is used to control the on / off of the input end and the output end of the switch tube according to the level of the enable signal output by the enable port received by the input end; When the input end and the output end of the switch tube are disconnected, the corresponding first sending port is enabled, and when the input end and the output end of the switch tube are connected, the corresponding first sending port is interrupted and enabled.

9. The bridge circuit of the bridge device according to claim 7, characterized in that: Each of the enable ports is also electrically connected to the first voltage output port of the battery management system via a series connection of a Schottky diode, wherein the Schottky diode is used to rectify an enable signal output along an enable port of the bridge conversion chip (200).

10. A bridge device for communication connection between a host of a battery management system and a battery acquisition chip AFE, comprising a bridge plug, wherein a bridge circuit is provided in the bridge plug, characterized in that: The bridge circuit includes the bridge circuit of any one of claims 1 to 9.

Images