Power processing circuit and power amplifier system

Abstract

The invention provides a power processing circuit and a power amplifier system, the power processing circuit comprises a first differential signal port, N second differential signal ports and a power processing unit connected between the first differential signal port and the N second differential signal ports, the power processing unit comprises N pairs of first differential coupling lines, and N is greater than or equal to 2; the positive coupling lines of the N pairs of first differential coupling lines are connected with the positive port of the first differential signal port, and the negative coupling lines of the N pairs of first differential coupling lines are connected with the negative port of the first differential signal port. According to the scheme, the positive coupling lines and the negative coupling lines of the different pairs of first differential coupling lines are connected in parallel, so that the whole circuit structure is simpler, the balance degree is better, the size and insertion loss of the power processing circuit are reduced, and when the circuit structure is applied to an amplifier system, the power processing circuit is more stable. The multi-way amplifier may be powered from a parallel connection point.

Description

Technical Field

[0001] This application relates to the field of radio frequency and microwave technologies, and particularly to a power processing circuit and a power amplifier system. Background Art

[0002] Power dividers / combiners are widely used in the field of wireless communication. A power divider can equally divide one signal into two or more signals with equal amplitude and in-phase, and a combiner can combine two or more signals with equal amplitude and in-phase into one signal. The bandwidth of the power divider / combiner affects the operating frequency of its system, the insertion loss within the band affects the transmission power of the wireless communication signal, and the isolation directly affects the interference between communication signals.

[0003] On the one hand, in modern communication systems, as one of the important radio frequency devices, power dividers / combiners are required to have characteristics such as wide bandwidth, low insertion loss, and high isolation. There are three common implementation methods for power dividers / combiners: The first is to use lumped elements in the form of capacitors and inductors to build. This type of power divider / combiner is difficult to implement at high frequencies (for example, frequencies higher than 5 GHz), and has a relatively narrow bandwidth, about 20% or so; the second is to use distributed transmission lines, that is, Wilkinson power dividers. It is difficult to reconcile the size and broadband performance of this type of power divider; the third is to use waveguides or dielectric integrated waveguides. This type of power divider has good performance, but it is difficult to make the size small and it is difficult to achieve high integration, lacking in practical applications.

[0004] On the other hand, with the development of technology, in the design of 5G multi-mode and multi-frequency power amplifier systems (PA), it is desired to be able to output 32 dBm LTE linear power (MPR = O) at a working voltage of 3.4V. Converted, the load impedance of the differential power amplifier system (PA) is 6 ohm. Since the design of a 1:9 transformer is difficult, and the GaAs chip has a large power, it poses challenges to both performance and cost. The existing implementation methods of power amplifier systems including power dividers / combiners cannot meet the above requirements for output power and efficiency. Summary of the Invention

[0005] This application aims to at least solve one of the technical problems existing in the prior art. For this reason, this application proposes a power processing circuit and a power amplifier system to solve the above one or more problems.

[0006] To solve the above one or more technical problems, the technical solution adopted in this application is:

[0007] In a first aspect, a power processing circuit is provided, including a first differential signal port, N second differential signal ports, and a power processing unit connected between the first differential signal port and the N second differential signal ports. Wherein, the power processing unit includes N pairs of first differential coupled lines, and N≥2;

[0008] The positive coupled lines of the N pairs of the first differential coupled lines are all connected to the positive port of the first differential signal port, and the negative coupled lines of the N pairs of the first differential coupled lines are all connected to the negative port of the first differential signal port.

[0009] In the solution of the present application, by setting that the positive coupled lines of all the first differential coupled lines in the power processing circuit are all connected to the positive port of the first differential signal port, and the negative coupled lines of all the first differential coupled lines are all connected to the negative port of the first differential signal port, that is, the positive coupled lines and the negative coupled lines between different pairs of the first differential coupled lines are all connected in parallel, the overall circuit structure is simpler, has better balance, is beneficial to reducing the size and insertion loss of the power processing circuit, and when this circuit structure is applied to an amplifier system, multiple amplifiers can be powered from the parallel connection point.

[0010] In a preferred embodiment, the positive port and the negative port in at least one second differential signal port are respectively connected to the positive coupled line and the negative coupled line of different pairs of the first differential coupled lines.

[0011] In the solution of the present application, by setting that the positive port and the negative port in at least one second differential signal port are respectively connected to the positive coupled line and the negative coupled line of different pairs of the first differential coupled lines, the isolation degree of the entire power processing circuit can be further improved.

[0012] In a preferred embodiment, the positive port and the negative port in each second differential signal port are respectively connected to the positive coupled line and the negative coupled line of different pairs of the first differential coupled lines.

[0013] In a preferred embodiment, the power processing circuit further includes a pair of second differential coupled lines. The positive coupled line of the second differential coupled line is connected between the positive port of the first differential signal port and the positive coupled lines of the N pairs of the first differential coupled lines, and the negative coupled line of the second differential coupled line is connected between the negative port of the first differential signal port and the negative coupled lines of the N pairs of the first differential coupled lines.

[0014] In a preferred embodiment, the input signal and the output signal of the power processing circuit are both single-ended signals, and the power processing circuit further includes a single-ended signal port and a balun;

[0015] The balun is connected between the single-ended signal port and the first differential signal port and / or the second differential signal port.

[0016] In a preferred embodiment, the power processing circuit further includes an isolation module disposed between the common ends of different second differential signal ports.

[0017] In a preferred embodiment, the isolation module includes an isolation resistor, or an isolation resistor and a capacitor connected in parallel.

[0018] In a preferred embodiment, the power processing circuit is a power splitter.

[0019] In a preferred embodiment, the first differential signal port serves as a differential signal input port, and the second differential signal port serves as a differential signal output port.

[0020] In a preferred embodiment, the power processing circuit is a combiner.

[0021] In a preferred embodiment, the first differential signal port serves as a differential signal output port, and the second differential signal port serves as a differential signal input port.

[0022] In a second aspect, a power amplifier system is further provided. The system includes an input port, an output port, and a plurality of power amplification paths disposed between the input port and the output port:

[0023] The plurality of power amplification paths are all connected to the input port, and include at least one main power amplification path and at least one auxiliary power amplification path, and are used for amplifying an input signal received from the input port respectively. When the at least one auxiliary power amplification path is in an operating state, load modulation is performed on the main power amplification path to reduce the load impedance of the main power amplification path;

[0024] A power splitter implemented by the power processing circuit according to any one of the first aspects is connected between the input port and the plurality of power amplification paths, and is used for distributing the power of an input signal input from the input port and outputting the input signal as multiple paths of signals; and / or,

[0025] A combiner implemented by the power processing circuit according to any one of the first aspects is connected between the plurality of power amplification paths and the output port, and is used for combining the amplified signals output by all the power amplification paths to obtain a combined output signal.

[0026] In the solution of this application, by adopting a parallel connection method between the positive coupling lines and the negative coupling lines of different pairs of the first differential coupling lines of the power processing circuit, the overall circuit structure is made simpler, has better balance, is beneficial to reducing the size and insertion loss of the power processing circuit, and when this circuit structure is applied to an amplifier system, on the one hand, it can supply power to multiple amplifiers from the parallel connection point, making the circuit structure simpler, and on the other hand, it can also improve the working efficiency during power back-off.

[0027] Additional aspects and advantages of this application will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of this application. Brief Description of the Drawings

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0029] Figure 1 is the architecture diagram of the power processing circuit provided in Embodiment 1 of this application;

[0030] Figure 2 is Figure 1 the schematic diagram of the working mode when the power processing circuit in

[0031] Figure 3 is Figure 1 the schematic diagram of the working mode when the power processing circuit in

[0032] Figure 4 is the architecture diagram of the power processing circuit provided in Embodiment 1 of this application when the original input signal is a single-ended signal;

[0033] Figure 5 is the architecture diagram of the power processing circuit provided in Embodiment 2 of this application;

[0034] Figure 6 is the architecture diagram of the power processing circuit provided in Embodiment 3 of this application;

[0035] Figure 7 is the architecture diagram of the power processing circuit provided in Embodiment 4 of this application;

[0036] Figure 8 is the schematic diagram of the simulation result of the performance of the power processing circuit provided in Embodiment 4 of this application;

[0037] Figure 9It is the architecture diagram of the power processing circuit provided in Embodiment 5 of the present application;

[0038] Figure 10 It is the schematic diagram of the simulation result of the performance of the power processing circuit provided in Embodiment 5 of the present application;

[0039] Figure 11 It is the architecture diagram of the power amplifier system provided in Embodiment 6 of the present application;

[0040] Figure 12 It is another architecture diagram of the power amplifier system provided in Embodiment 6 of the present application;

[0041] Figure 13 It is the schematic diagram of the simulation result of the performance of the power amplifier system provided in Embodiment 6 of the present application;

[0042] Figure 14 It is the schematic diagram of the simulation result of the performance of the power amplifier system provided in Comparative Example 1;

[0043] Figure 15 It is the schematic diagram of the simulation result when the port of the auxiliary power amplification unit of the power amplifier system provided in Embodiment 6 of the present application is open at the power divider;

[0044] Figure 16 It is the schematic diagram of the simulation result when the port of the auxiliary power amplification unit of the power amplifier system provided in Embodiment 6 of the present application is short - circuited at the power divider;

[0045] Figure 17 It is the schematic diagram of the simulation result when the port of the auxiliary power amplification unit of the power amplifier system provided in Comparative Example 1 is open at the power divider;

[0046] Figure 18 It is the schematic diagram of the simulation result when the port of the auxiliary power amplification unit of the power amplifier system provided in Comparative Example 1 is short - circuited at the power divider;

[0047] Figure 19 It is the architecture diagram of the power amplifier system provided in Embodiment 7 of the present application;

[0048] Figure 20 It is the schematic diagram of the simulation result of the performance of the power amplifier system provided in Embodiment 7 of the present application at 1, 3, 5 GHz;

[0049] Figure 21 It is the architecture diagram of the power amplifier system provided in Embodiment 8 of the present application;

[0050] Figure 22 It is the schematic diagram of the simulation result of the performance of the power amplifier system provided in Embodiment 8 of the present application;

[0051] Figure 23It is a schematic diagram of the simulation result when the ports of two auxiliary power amplification units of the power amplifier system provided in the eighth embodiment of the present application are short-circuited at the combiner;

[0052] Figure 24 It is a schematic diagram of the architecture of the power processing circuit provided in Comparative Example 1. Detailed implementation manners

[0053] To make the objectives, technical solutions, and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0054] The embodiment of the present application provides a power processing circuit, including a first differential signal port, N second differential signal ports, and a power processing unit connected between the first differential signal port and the N second differential signal ports. Wherein, the power processing unit includes N pairs of first differential coupled lines, and N≥2;

[0055] The positive coupled lines of the N pairs of first differential coupled lines are all connected to the positive port of the first differential signal port, and the negative coupled lines of the N pairs of first differential coupled lines are all connected to the negative port of the first differential signal port.

[0056] The applicant has found through a large number of experiments that through the above improvements, the isolation degree of the entire power processing circuit can be further improved.

[0057] The following will specifically elaborate on the present application through specific embodiments.

[0058] Embodiment 1

[0059] Figure 1 It shows a schematic diagram of the structure of the power processing circuit provided in Embodiment 1 of the present application. Referring to Figure 1 As shown, in the power processing circuit provided in the embodiment of the present application, the number N is selected as 2. The circuit includes a first differential signal terminal 101, two second differential signal terminals 1021 and 1022, and a power processing unit 103 connected between the first differential signal port 101 and the two second differential signal ports 1021 and 1022. Wherein, the power processing unit 103 includes two pairs of first differential coupled lines 1031 and 1032.

[0060] The first differential signal terminal 101 includes a positive terminal 101a and a negative terminal 101b. The second differential signal port 1021 includes a positive port 1021a and a negative port 1021b. The second differential signal port 1022 includes a positive port 1022a and a negative port 1022b.

[0061] The first pair of first differential coupling lines 1031 includes a positive coupling line 1031a and a negative coupling line 1031b. The second pair of first differential coupling lines 1032 includes a positive coupling line 1032a and a negative coupling line 1032b.

[0062] Further referring to Figure 1 As shown, the positive terminal 101a of the first differential signal port 101 is connected to the positive coupling line 1031a in the first pair of first differential coupling lines 1031 and the positive coupling line 1032a in the second pair of first differential coupling lines 1032. The negative terminal 101b of the first differential signal port 101 is connected to the negative coupling line 1031b in the first pair of first differential coupling lines 1031 and the negative coupling line 1032b in the second pair of first differential coupling lines 1032. The positive port 1021a in the second differential signal port 1021 is connected to the positive coupling line 1031a in the first pair of first differential coupling lines 1031. The negative port 1021b in the second differential signal port 1021 is connected to the negative coupling line 1032b in the second pair of first differential coupling lines 1032. The positive terminal 1022a in the second differential signal terminal 1022 is connected to the positive coupling line 1032a in the second pair of first differential coupling lines 1032. The negative port 1022b in the second differential signal port 1022 is connected to the negative coupling line 1031b in the first pair of first differential coupling lines 1031.

[0063] It can be seen that in the embodiment of the present application, the positive coupling lines of all the first differential coupling lines are connected to the positive terminal 101a of the first differential signal port 101, and the negative coupling lines of all the first differential coupling lines are connected to the negative terminal 101b of the first differential signal port 101. That is, the positive coupling lines and the negative coupling lines of different pairs of first differential coupling lines are connected in parallel, making the overall circuit structure simpler. And when this circuit structure is applied to an amplifier system, multiple amplifiers can be powered from the parallel connection point. The positive port 1021a and the negative port 1021b in the second differential signal port 1021 are connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines, and the positive port 1022a and the negative port 1022b in the second differential signal port 1022 are also connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines. Such a setting can further improve the isolation degree of the entire power processing circuit.

[0064] Further referring to Figure 1As shown, as a preferred embodiment, in the embodiment of the present application, the power processing circuit further includes a pair of second differential coupled lines 104. The second differential coupled lines 104 include a positive coupled line 104a and a negative coupled line 104b. One end of the positive coupled line 104a of the second differential coupled lines 104 is connected to the positive port 101a of the first differential signal port 101, and the other end is connected to the positive coupled lines of all the first differential coupled lines; one end of the negative coupled line 104b of the second differential coupled lines 104 is connected to the negative port 101b of the first differential signal port 101, and the other end is connected to the negative coupled lines of all the first differential coupled lines.

[0065] As a preferred embodiment, in the embodiment of the present application, the power processing circuit further includes an isolation module, and the isolation module is arranged between the same ports of different second differential signal ports. In some specific embodiments, the isolation module can adopt an isolation resistor; in other specific embodiments, the isolation module can adopt a parallel combination of an isolation resistor and a capacitor. It should be noted that in the embodiment of the present application, the specific implementation of the isolation module is not limited, and it can be selected according to the actual product requirements without departing from the inventive concept of the present application.

[0066] For example, in the power processing circuit shown Figure 1 the isolation resistor serving as the isolation module is arranged between the same ports of different second differential signal ports. Specifically, a total of 2 isolation resistors R105a and R105b are provided. Among them, the isolation resistor R105a is arranged between the positive port 1021a of the second differential signal port 1021 and the positive port 1022a of the second differential signal port 1022, and the isolation resistor R105b is arranged between the negative port 1021b of the second differential signal port 1021 and the negative port 1022b of the second differential signal port 1022.

[0067] It is proved by experiments that for the power processing circuit provided by the embodiment of the present application, through the setting of the isolation module, and the connection of the positive and negative ports of at least one second differential signal port to the positive and negative coupled lines of different pairs of first differential coupled lines, the isolation degree can be further improved.

[0068] It should be noted that the power processing circuit provided by the embodiment of the present application can be used to implement a power divider or a combiner. It can be understood that when the above power processing circuit is a power divider, the first differential signal port 101 is used as the differential signal input port, and the 2 second differential signal ports 1021 and 1022 are used as the differential signal output ports; when the above power processing circuit is a combiner, the first differential signal port 101 is used as the differential signal output port, and the 2 second differential signal ports 1021 and 1022 are used as the differential signal input ports.

[0069] Figure 2 shows Figure 1 a schematic diagram of the operating mode of the power handling circuit in when it is used as a power divider. At this time, the first differential signal port serves as the differential signal input port, and the two second differential signal ports serve as the differential signal output ports. The original Figure 1 positive terminal port 101a and negative terminal port 101b of the first differential signal port 101 in Figure 2 are replaced and represented by the positive input port I101a and negative input port I101b of the differential signal input port I101 in ; the original Figure 1 positive terminal port 1021a and negative terminal port 1021b of the second differential signal port 1021 in Figure 2 are represented by the positive output port 01021a and negative output port 01021b of the differential signal output port 01021 in ; the original Figure 1 positive terminal port 1022a and negative terminal port 1022b of the second differential signal port 1022 in Figure 2 are represented by the positive output port 01022a and negative output port 01022b of the differential signal output port 01022 in . Other circuit elements with the same reference numerals as those in Figure 1 are the same components and will not be elaborated here.

[0070] Figure 3 shows Figure 1 a schematic diagram of the operating mode of the power handling circuit in when it is used as a combiner. At this time, the first differential signal port serves as the differential signal output port for the combined signal, and the two second differential signal ports serve as the differential signal input ports. The original Figure 1 positive terminal port 101a and negative terminal port 101b of the first differential signal port 101 in Figure 3 are replaced and represented by the positive output port 0101a and negative output port 0101b of the differential signal output port 0101 in ; the original Figure 1 positive terminal port 1021a and negative terminal port 1021b of the second differential signal port 1021 in Figure 3 are represented by the positive input port l1021a and negative input port I1021b of the differential signal input port l1021 in ; the original Figure 1 positive terminal port 1022a and negative terminal port 1022b of the second differential signal port 1022 in Figure 3 are represented by the positive input port 11022a and negative input port 11022b of the differential signal output port 11022 in . Other circuit elements with the same reference numerals as those in Figure 1 are the same components and will not be elaborated here.

[0071] In some other specific embodiments, when the original input signal is a single-ended signal, the negative terminal of the differential signal input port of the power processing circuit can be grounded. Taking the power processing circuit as a power splitter as an example, refer to Figure 4 As shown, at this time, the first differential signal port 101 serves as the differential signal input port, and the two second differential signal ports 1021 and 1022 serve as the differential signal output ports. The single-ended original input signal can be input into the power processing circuit through the positive terminal 101a of the first differential signal port 101, and the negative terminal 101b of the first differential signal port 101 is grounded.

[0072] The power processing circuit provided in the first embodiment of the present application can optimize the in-band insertion loss, return loss, and isolation degree by changing one or several combinations of the electrical lengths, even-mode impedances Ze, odd-mode impedances Zo of the differential coupling lines (including the first differential coupling line and the second differential coupling line), and the isolation module. Without using traditional quarter-wavelength coupling lines, the length of the differential coupling lines in the embodiments of the present application can be less than a quarter wavelength of the operating center frequency, thereby reducing the size of the entire circuit, increasing the integration degree, and improving the insertion loss performance. In addition, the operating bandwidth can also be controlled by changing the electrical lengths, even-mode impedances Ze, odd-mode impedances Zo of the differential coupling lines (including the first differential coupling line and the second differential coupling line).

[0073] In addition, it should be noted that in this embodiment, "positive" and "negative" are relative concepts, which can only indicate "inverted phase" or "out-of-phase" between the signals of the corresponding ports. By interchanging "positive" and "negative" with each other, the circuit in this embodiment can still work normally, and this deformation method is still within the protection scope of the present application.

[0074] Embodiment 2

[0075] Figure 5 is the architecture diagram of the power processing circuit provided in the second embodiment of the present application. Refer to Figure 5 As shown, in the power processing circuit provided in the embodiment of the present application, the digital N is selected as 3. The circuit includes a first differential signal port 201, three second differential signal ports 2021, 2022, and 2023, and a power processing unit 203 connected between the first differential signal port 201 and the three second differential signal ports 2021, 2022, and 2023. Among them, the power processing unit 203 includes three pairs of first differential coupling lines 2031, 2032, and 2033.

[0076] The first differential signal port 201 includes a positive terminal port 201a and a negative terminal port 201b. The second differential signal port 2021 includes a positive terminal port 2021a and a negative terminal port 2021b. The second differential signal port 2022 includes a positive terminal port 2022a and a negative terminal port 2022b. The second differential signal port 2023 includes a positive terminal port 2023a and a negative terminal port 2023b.

[0077] The first pair of first differential coupling lines 2031 includes a positive coupling line 2031a and a negative coupling line 2031b. The second pair of first differential coupling lines 2032 includes a positive coupling line 2032a and a negative coupling line 2032b. The third pair of first differential coupling lines 2033 includes a positive coupling line 2033a and a negative coupling line 2033b.

[0078] Further referring to Figure 5 as shown, the positive terminal port 201a of the first differential signal port 201 is connected to the positive coupling line 2031a in the first pair of first differential coupling lines 2031, the positive coupling line 2032a in the second pair of first differential coupling lines 2032, and the positive coupling line 2033a in the third pair of first differential coupling lines 2033. The negative terminal port 201b of the first differential signal port 201 is connected to the negative coupling line 2031b in the first pair of first differential coupling lines 2031, the negative coupling line 2032b in the second pair of first differential coupling lines 2032, and the negative coupling line 2033b in the third pair of first differential coupling lines 2033. The positive terminal port 2021a in the second differential signal port 2021 is connected to the positive coupling line 2031a in the first pair of first differential coupling lines 2031. The negative terminal port 2021b in the second differential signal port 2021 is connected to the negative coupling line 2032b in the second pair of first differential coupling lines 2032. The positive terminal port 2022a in the second differential signal port 2022 is connected to the positive coupling line 2032a in the second pair of first differential coupling lines 2032. The negative terminal port 2022b in the second differential signal port 2022 is connected to the negative coupling line 2033b in the third pair of first differential coupling lines 2033. The positive terminal port 2023a in the second differential signal port 2023 is connected to the positive coupling line 2033a in the third pair of first differential coupling lines 2033. The negative terminal port 2023b in the second differential signal port 2023 is connected to the negative coupling line 2031b in the first pair of first differential coupling lines 2031.

[0079] It can be seen that in the embodiments of the present application, the positive coupling lines of all the first differential coupling lines are connected to the positive terminal port 201a of the first differential signal port 201, and the negative coupling lines of all the first differential coupling lines are connected to the negative terminal port 201b of the first differential signal port 201. That is, the positive coupling lines and the negative coupling lines of different pairs of the first differential coupling lines are connected in parallel, making the overall circuit structure simpler. And when this circuit structure is applied to an amplifier system, power can be supplied to multiple amplifiers from the parallel connection point. The positive terminal port and the negative terminal port in each second differential signal port are connected to the positive coupling lines and the negative coupling lines of different pairs of differential coupling lines. With such a setting, the isolation degree of the entire power processing circuit can be further improved.

[0080] Further referring to Figure 5 As shown, the power processing circuit further includes a pair of second differential coupling lines 204. The second differential coupling lines 204 include a positive coupling line 204a and a negative coupling line 204b. One end of the positive coupling line 204a of the second differential coupling lines 204 is connected to the positive terminal port 201a of the first differential signal port 201, and the other end is connected to the positive coupling lines of all the first differential coupling lines; one end of the negative coupling line 204b of the second differential coupling lines 204 is connected to the negative terminal port 201b of the first differential signal port 201, and the other end is connected to the negative coupling lines of all the first differential coupling lines.

[0081] As a preferred implementation manner, in the embodiments of the present application, the power processing circuit further includes an isolation module (not shown in the figure), and the isolation module is disposed between the same terminal ports of different second differential signal ports. In some specific embodiments, the isolation module can adopt an isolation resistor; in other specific embodiments, the isolation module can adopt a parallel combination of an isolation resistor and a capacitor. It should be noted that in the embodiments of the present application, the specific implementation of the isolation module is not limited, and it can be selected according to the actual product requirements without departing from the inventive concept of the present application.

[0082] In some specific embodiments, the isolation resistor serving as the isolation module is disposed between the common extreme ports of different second differential signal ports. Specifically, in the embodiments of the present application, 6 isolation resistors can be provided. Among them, between the positive extreme port 2021a of the second differential signal port 2021 and the positive extreme port 2022a of the second differential signal port 2022, between the negative extreme port 2021b of the second differential signal port 2021 and the negative extreme port 2022b of the second differential signal port 2022, between the positive extreme port 2022a of the second differential signal port 2022 and the positive extreme port 2023a of the second differential signal port 2023, between the negative extreme port 2022b of the second differential signal port 2022 and the negative extreme port 2023b of the second differential signal port 2023, between the positive extreme port 2021a of the second differential signal port 2021 and the positive extreme port 2023a of the second differential signal port 2023, and between the negative extreme port 2021b of the second differential signal port 2021 and the negative extreme port 2023b of the second differential signal port 2023, one isolation resistor is provided respectively. Details are not described herein one by one.

[0083] Experimental results demonstrate that for the power processing circuit provided in the embodiments of the present application, through the setting of the isolation module, and by connecting the positive and negative extreme ports of at least one second differential signal port to the positive and negative coupling lines of different pairs of first differential coupling lines, the isolation degree can be further improved.

[0084] It should be noted that the power processing circuit provided in the embodiments of the present application can be used to implement a power divider or a combiner. It can be understood that when the above power processing circuit is a power divider, the first differential signal port 201 is used as the differential signal input port, and the 3 second differential signal ports 2021, 2022, and 2023 are used as the differential signal output ports; when the above power processing circuit is a combiner, the first differential signal port 201 is used as the differential signal output port, and the 3 second differential signal ports 2021, 2022, and 2023 are used as the differential signal input ports. For specific details, reference can be made to the relevant content in Embodiment 1, and details are not described herein one by one.

[0085] The power processing circuit provided in the second embodiment of the present application can also optimize the in-band insertion loss, return loss, and isolation by changing one or a combination of the electrical lengths, even-mode impedances \(Z_e\), odd-mode impedances \(Z_o\), and isolation modules of the differential coupled lines (including the first differential coupled line and the second differential coupled line). Without using traditional quarter-wavelength coupled lines, the length of the differential coupled lines in the embodiments of the present application can be less than a quarter-wavelength of the center operating frequency, thereby reducing the size of the entire circuit, increasing the integration, and improving the insertion loss performance. In addition, the operating bandwidth can be controlled by changing the electrical lengths, even-mode impedances \(Z_e\), and odd-mode impedances \(Z_o\) of the differential coupled lines (including the first differential coupled line and the second differential coupled line).

[0086] Embodiment Three

[0087] Figure 6 is the architecture diagram of the power processing circuit provided in the third embodiment of the present application. Referring to Figure 6 as shown, in the power processing circuit provided in the embodiments of the present application, the number of second differential signal ports and the number of pairs of differential coupled lines in the power processing unit are set to be more, and are represented by the number \(N\), where \(N\geq2\) and \(N\) is a positive integer. Specifically, the embodiments of the present application include a first differential signal port 301, \(N\) second differential signal ports 3021 - 302N, and a power processing unit 303 connected between the first differential signal port 301 and the \(N\) second differential signal ports 3021 - 302N. Among them, the power processing unit 303 includes \(N\) pairs of first differential coupled lines 3031 - 303N.

[0088] The first differential signal port 301 includes a positive terminal port 301a and a negative terminal port 301b. Each second differential signal port includes a positive terminal port and a negative terminal port. For example, the second differential signal port 302i includes a positive terminal port 302ia and a negative terminal port 302ib, where \(1\leq i\leq N\) and \(i\) is a positive integer. That is, the second differential signal port 3021 includes a positive terminal port 3021a and a negative terminal port 3021b, the second differential signal port 3022 includes a positive terminal port 3022a and a negative terminal port 3022b, and so on. The second differential signal port 302N includes a positive terminal port 302Na and a negative terminal port 302Nb.

[0089] Each pair of first differential coupled lines includes a positive coupled line and a negative coupled line. For example, the i-th pair of first differential coupled lines 303i includes a positive coupled line 303ia and a negative coupled line 303ib, where 1 ≤ i ≤ N and i is a positive integer. That is, the first pair of first differential coupled lines 3031 includes a positive coupled line 3031a and a negative coupled line 3031b, the second pair of first differential coupled lines 3032 includes a positive coupled line 3032a and a negative coupled line 3032b, and so on. The N-th pair of first differential coupled lines 303N includes a positive coupled line 303Na and a negative coupled line 303Nb.

[0090] Further referring to Figure 6 As shown, the positive terminal port 301a of the first differential signal port 301 is connected to the positive coupled lines in all pairs of first differential coupled lines, and the negative terminal port 301b of the first differential signal port 301 is connected to the negative coupled lines in all pairs of first differential coupled lines.

[0091] Further referring to Figure 6 As shown, in the embodiment of the present application, the positive terminal port 302ja of the second differential signal port 302j is connected to the positive coupled line 303ja in the j-th pair of first differential coupled lines 303j, and the negative terminal port 302jb of the second differential signal port 302j is connected to the negative coupled line 303(j + 1)b in the (j + 1)-th pair of first differential coupled lines 303(j + 1), where 1 ≤ j < N and j is a positive integer. That is, the positive terminal port 3021a of the second differential signal port 3021 is connected to the positive coupled line 3031a in the first pair of first differential coupled lines 3031, and the negative terminal port 3021b of the second differential signal port 3021 is connected to the negative coupled line 3032b in the second pair of first differential coupled lines 3032; the positive terminal port 3022a of the second differential signal port 3022 is connected to the positive coupled line 3032a in the second pair of first differential coupled lines 3032, and the negative terminal port 3022b of the second differential signal port 3022 is connected to the negative coupled line 3033b in the third pair of first differential coupled lines 3033, and so on. The positive terminal port 302Na of the second differential signal port 302N is connected to the positive coupled line 303Na in the N-th pair of first differential coupled lines 303N, and the negative terminal port 302Nb of the second differential signal port 302N is connected to the negative coupled line 3031b in the first pair of first differential coupled lines 3031.

[0092] It can be seen that in the embodiment of the present application, the positive coupling lines of all the first differential coupling lines are connected to the positive terminal port 301a of the first differential signal port 301, and the negative coupling lines of all the first differential coupling lines are connected to the negative terminal port 301b of the first differential signal port 301. That is, the positive coupling lines and the negative coupling lines of different pairs of the first differential coupling lines are connected in parallel, making the overall circuit structure simpler. And when this circuit structure is applied to an amplifier system, power can be supplied to multiple amplifiers from the parallel connection point. The positive terminal port and the negative terminal port in each second differential signal port are connected to the positive coupling line and the negative coupling line of different pairs of differential coupling lines. With such a setting, the isolation degree of the entire power processing circuit can be further improved.

[0093] Further referring to Figure 6 As shown, the power processing circuit further includes a pair of second differential coupling lines 304. The second differential coupling lines 304 include a positive coupling line 304a and a negative coupling line 304b. One end of the positive coupling line 304a of the second differential coupling lines 304 is connected to the positive terminal port 301a of the first differential signal port 301, and the other end is connected to the positive coupling lines of all the first differential coupling lines; one end of the negative coupling line 304b of the second differential coupling lines 304 is connected to the negative terminal port 301b of the first differential signal port 301, and the other end is connected to the negative coupling lines of all the first differential coupling lines.

[0094] As a preferred embodiment, in the embodiment of the present application, the power processing circuit further includes an isolation module (not shown in the figure), and the isolation module is arranged between the same terminal ports of different second differential signal ports. In some specific embodiments, the isolation module can adopt an isolation resistor; in other specific embodiments, the isolation module can adopt a parallel combination of an isolation resistor and a capacitor. It should be noted that in the embodiment of the present application, the specific implementation of the isolation module is not limited, and it can be selected according to the actual product requirements without departing from the inventive concept of the present application.

[0095] In some specific embodiments, the isolation resistor serving as the isolation module is arranged between the same terminal ports of different second differential signal ports. Specifically, in the embodiment of the present application, an isolation resistor can be arranged between the positive terminal port 302ja of the second differential signal port 302j and the positive terminal port 302(j + 1)a of the second differential signal port 302(j + 1), and between the negative terminal port 302jb of the second differential signal port 302j and the negative terminal port 302(j + 1)b of the second differential signal port 302(j + 1), where 1 ≤ j < N and j is a positive integer, and details are not described one by one here.

[0096] Through experiments, it is proved that for the power processing circuit provided by the embodiments of the present application, through the setting of the isolation module, and the positive and negative terminals of at least one second differential signal port being connected to the positive and negative coupled lines of different pairs of first differential coupled lines, the isolation degree can be further improved.

[0097] It should be noted that the power processing circuit provided by the embodiments of the present application can equally be used to implement a power divider or a combiner. It can be understood that when the above power processing circuit is a power divider, the first differential signal port 301 is used as the differential signal input port, and the N second differential signal ports 3021 - 302N are used as the differential signal output ports; when the above power processing circuit is a combiner, the first differential signal port 301 is used as the differential signal output port, and the N second differential signal ports 3021 - 302N are used as the differential signal input ports. For specific details, reference can be made to the relevant content in Embodiment 1, which will not be elaborated here one by one.

[0098] For the power processing circuit provided by the third embodiment of the present application, the in-band insertion loss, return loss, and isolation degree can also be optimized by changing one or a combination of the electrical length, even-mode impedance Ze, odd-mode impedance Zo of the differential coupled lines (including the first differential coupled lines and the second differential coupled lines), and the isolation module. Without using traditional quarter-wavelength coupled lines, the length of the differential coupled lines in the embodiments of the present application can be less than a quarter wavelength of the operating center frequency, thereby reducing the size of the entire circuit, increasing the integration degree, and improving the insertion loss performance. In addition, the operating bandwidth can also be controlled by changing the electrical length, even-mode impedance Ze, odd-mode impedance Zo of the differential coupled lines (including the first differential coupled lines and the second differential coupled lines).

[0099] Embodiment 4

[0100] Figure 7 is the architecture diagram of the power processing circuit provided by the fourth embodiment of the present application. The overall structure of the power processing circuit in the embodiments of the present application is similar to that of the power processing circuit in Embodiment 1. However, the difference from Embodiment 1 is as follows: with reference to Figure 7 as shown, both the input signal and the output signal of the power processing circuit in the embodiments of the present application are single-ended signals.

[0101] In addition to including the circuit elements and circuit structures shown in Embodiment 1, the power processing circuit in the embodiments of the present application further includes a single-ended signal port and a balun. Among them, the balun is connected between the single-ended signal port and the first differential signal port, or the balun is connected between the single-ended signal port and the second differential signal port.

[0102] Further with reference to Figure 7As shown, in the embodiment of the present application, the power processing circuit includes a first differential signal port 401, two second differential signal ports 4021 and 4022, a power processing unit 403 connected between the first differential signal port 401 and the two second differential signal ports 4021 and 4022 (wherein, the power processing unit 403 includes two pairs of first differential coupled lines 4031 and 4032), a pair of second differential coupled lines 404, a first single-ended signal port 405, two second single-ended signal ports 4061 and 4062, two baluns 4071 and 4072, and two isolation resistors R405a and R405b.

[0103] Further referring to Figure 7 As shown, the first differential signal port 401 includes a positive port 401a and a negative port 401b, the second differential signal port 4021 includes a positive port 4021a and a negative port 4021b, and the second differential signal port 4022 includes a positive port 4022a and a negative port 4022b. The first pair of first differential coupled lines 4031 includes a positive coupled line 4031a and a negative coupled line 4031b, and the second pair of first differential coupled lines 4032 includes a positive coupled line 4032a and a negative coupled line 4032b. The second differential coupled line 404 includes a positive coupled line 404a and a negative coupled line 404b. Among them, the connection relationship between the first differential signal port 401, the second differential signal ports 4021 and 4022, the power processing unit 403, the second differential coupled line 404, and the two isolation resistors R405a and R405b can refer to the relevant content in Embodiment 1, which will not be elaborated here one by one.

[0104] Further referring to Figure 7As shown, the first single-ended signal port 405 is connected to the positive terminal port 401a of the first differential signal port 401, and a capacitor 408 is connected between the first single-ended signal port 405 and the positive terminal port 401a of the first differential signal port 401. The negative terminal port 401b of the first differential signal port 401 is grounded. Among them, the capacitor 408 serves as a coupling capacitor, which allows the AC signal to be transmitted from the single-ended signal port 405 to the differential signal port 401a, while blocking the DC component to ensure that the AC characteristics of the signal are maintained. The balun 4071 is connected between the second differential signal port 4021 and the second single-ended signal port 4061, and the balun 4072 is connected between the second differential signal port 4022 and the second single-ended signal port 4062. The baluns 4071 and 4072 play a role in transforming the differential signal to the single-ended signal or from the single-ended signal to the differential signal. For example, when the power processing circuit is used as a power divider, the first differential signal port 401 serves as the differential signal input port, and the two second differential signal ports 4021 and 4022 serve as the differential signal output ports. At this time, the baluns 4071 and 4072 play a role in transforming the differential signal to the single-ended signal, so as to transform the differential signals output from the two second differential signal ports 4021 and 4022 into single-ended signals and then transmit them to the two second single-ended signal ports 4061 and 4062 for output. When the power processing circuit is used as a combiner, the first differential signal port 401 serves as the differential signal output port, and the two second differential signal ports 4021 and 4022 serve as the differential signal input ports. At this time, the baluns 4071 and 4072 play a role in transforming the single-ended signal to the differential signal, so as to transform the single-ended signals input from the two second single-ended signal ports 4061 and 4062 into differential signals and then transmit them to the two second differential signal ports 4021 and 4022 respectively.

[0105] In some specific embodiments, the baluns 4071 and 4072 can be baluns with an impedance ratio of 1:1.

[0106] In some other specific embodiments, a balun (not shown in the figure) can also be connected between the first single-ended signal port 405 and the first differential signal port 401 to transform the single-ended signal into a differential signal or transform the differential signal into a single-ended signal, which will not be elaborated here one by one.

[0107] Figure 8 is a schematic diagram of the simulation result of the performance of the power processing circuit provided in the fourth embodiment of the present application. Refer to Figure 8As shown, the power processing circuit provided by the embodiment of the present application has the best impedance matching and the maximum gain near 5 GHz. The group delay is small at low frequencies and increases with the increase of frequency, which may affect the transmission of high-speed signals. The phase changes little within the concerned frequency range, which helps to maintain the phase consistency of the signal. The circuit exhibits multiple resonance points within the frequency range of 1 GHz to 10 GHz, which may affect the stability and bandwidth of the circuit.

[0108] Embodiment Five

[0109] Figure 9 is the architecture diagram of the power processing circuit provided by Embodiment Five of the present application. The overall structure of the power processing circuit in the embodiment of the present application is similar to that of the power processing circuit in Embodiment Four. However, the difference from Embodiment Four is that, referring to Figure 9 As shown, the balun 4072 in the embodiment of the present application is a balun with isolation. Further referring to Figure 9 As shown, in the embodiment of the present application, a capacitor 408 is connected between the negative terminal port 401b of the first differential signal port 401 and the ground. The other structures of the power processing circuit provided by the embodiment of the present application are the same as those of the power processing circuit provided by Embodiment Four, and will not be elaborated here one by one.

[0110] Figure 10 is the schematic diagram of the simulation results of the performance of the power processing circuit provided by Embodiment Five of the present application. Referring to Figure 10 As shown, the power processing circuit provided by the embodiment of the present application has good performance between 1 GHz and 2 GHz, including high gain, low reflection and stable phase; near 3 GHz, the performance of the circuit deteriorates, which may be due to poor impedance matching or limitations in circuit design; the circuit shows good performance again between 4 GHz and 5 GHz.

[0111] Embodiment Six

[0112] Corresponding to the above power processing circuit, an embodiment of the present application further provides a power amplifier system, which generally includes an input port, an output port, and a plurality of power amplification paths, a power splitter, and / or a combiner disposed between the input port and the output port. Among them, the plurality of power amplification paths are all connected to the input port. The plurality of power amplification paths include at least one main power amplification path and at least one auxiliary power amplification path, and are used to amplify an input signal received from the input port respectively. When at least one auxiliary power amplification path is in an operating state, load modulation is performed on the main power amplification path to reduce the load impedance of the main power amplification path. The power splitter and the combiner are implemented by the power processing circuit described in any one of the above Embodiments 1 to 5. The power splitter is connected between the input port and the plurality of power amplification paths, and is used to distribute the power of an input signal input from the input port and output it as multiple signals; the combiner is connected between the plurality of power amplification paths and the output port, and is used to synthesize the powers of the amplified signals output by all the power amplification paths to obtain a synthesized output signal.

[0113] Figure 11 FIG. shows the architecture diagram of the power amplifier system provided in Embodiment 6 of the present application. The system includes an input port RFlnput, an output port RFOutput, a plurality of power amplification paths, and a power splitter 100. Among them, the power splitter 100 and the plurality of power amplification paths are sequentially connected between the input port RFlnput and the output port RFOutput. The power splitter is implemented by the power processing circuit described in Embodiment 1, and details are not described herein one by one. Specifically, the power splitter 100 is connected between the input port RFlnput and the plurality of power amplification paths, and is used to distribute the power of an input signal input from the input port and output it as multiple signals to the plurality of power amplification paths respectively. Each power amplification path receives an input signal from the power splitter 100. In some specific embodiments, the input signals received by each power amplification path have the same phase. The plurality of power amplification paths amplify the input signal with the same phase received from the power splitter 100 respectively to obtain each amplified signal.

[0114] In some specific embodiments, the power amplification path includes at least one main power amplification path 510 and at least one auxiliary power amplification path 520, and is used to amplify an input signal received from the input port RFlnput respectively. When at least one auxiliary power amplification path is in an operating state, load modulation is performed on the main power amplification path to reduce the load impedance of the main power amplification path, that is, the power amplification path adopts two or more power amplifiers, and by performing phase compensation between different branches, power synthesis of the signals output by the plurality of power amplification paths in the same phase can be achieved.

[0115] In some specific embodiments, each of the power amplification paths includes a power amplification unit and an impedance conversion network. Among them, the power amplification unit is used to amplify an input signal with the same phase received from the input port RFlnput in the power amplification path where it is located; the impedance conversion network is connected to the power amplification unit and is used to perform load modulation on the power amplification unit in the power amplification path where it is located.

[0116] In the embodiments of the present application, the positional relationship between the impedance conversion network and the power amplification unit is not specifically limited, and can be set according to actual requirements during specific implementation. For example, in some specific embodiments, along the signal transmission direction, the impedance conversion network is arranged in front of the power amplification unit, that is, the impedance conversion network is arranged between the input port RFlnput and the power amplification unit; in some other specific embodiments, along the signal transmission direction, the impedance conversion network is arranged behind the power amplification unit, that is, the impedance conversion network is arranged between the power amplification unit and the output port RFOutput.

[0117] Further referring to Figure 11 As shown, in the embodiments of the present application, the power amplification path includes a main power amplification path 510 and an auxiliary power amplification path 520. The main power amplification path 510 includes a main power amplification unit 530a and a first impedance conversion network 540a, and the auxiliary power amplification path 520 includes an auxiliary power amplification unit 530b and a second impedance conversion network 540b. Among them, the first impedance conversion network 540a is connected between the input port RFlnput and the main power amplification unit 530a, and the second impedance conversion network 540b is connected between the auxiliary power amplification unit 530b and the output port RFOutput.

[0118] In some specific embodiments, the types of the power amplification units of the main power amplification path 510 and the auxiliary power amplification path 520 are different, that is, the types of the main power amplification unit 530a and the auxiliary power amplification unit 530b are different. The power amplification unit of the main power amplification path 510 remains in an on state at low input power; while the power amplification unit of the auxiliary power amplification path 520 is in an off state at low input power and is pushed by the input power into class C or class B state at high input power, which is also called Peaking PA.

[0119] The in-phase power combination of the power amplifier system provided in the embodiments of the present application can be designed with power amplification units in structures such as in-phase (Wilkinson power divider, 180° transformer combination), or 90° (coupled line combination, 90° hybrid coupler combination, etc.).

[0120] In some specific embodiments, the impedance conversion network of the main power amplification path 510 and the impedance conversion network of the auxiliary power amplification path 520 may be the same or different, that is, the first impedance conversion network 540a and the second impedance conversion network 540b may be the same or different, and no specific limitation is made here. During specific implementation, it can be set according to the actual product requirements. As a relatively optimal example, the main power amplification path 510 and the auxiliary power amplification path 520 adopt impedance conversion networks with the same phase shift, that is, the first impedance conversion network 540a and the second impedance conversion network 540b have the same phase shift. In this way, it is ensured that the phases of the amplified signals output by the main power amplification path 510 and the auxiliary power amplification path 520 are consistent when the signals are combined by the combiner.

[0121] In some specific embodiments, both the main power amplification path 510 and the auxiliary power amplification path 520 amplify the same-phase input signal received from the input port RFlnput respectively. When the auxiliary power amplification path 520 is in the working state, it performs load modulation on the main power amplification path 510 to reduce the load impedance of the main power amplification path 510.

[0122] Through experiments by the applicant, when the output power of the system is less than the first threshold, the main power amplification path 510 is in the working state and the auxiliary power amplification path 520 is in the off state. At this time, only the main power amplification unit 530a is turned on and the auxiliary power amplification unit 530b is in the off state, presenting a low impedance state at the port of the power splitter 100. When the output power of the system is not less than the first threshold, the auxiliary power amplification path 520 is in the working state. When the auxiliary power amplification path 520 is in the working state, it performs load modulation on the main power amplification path 510 to reduce the load impedance of the main power amplification path 510 until the difference between the load impedance of the main power amplification path 510 and the load impedance of the auxiliary power amplification path 520 is less than the second threshold. During this process, both the main power amplification unit 530a and the auxiliary power amplification unit 530b are turned on. However, at the beginning, the output powers of the main power amplification unit 530a and the auxiliary power amplification unit 530b are different. The output power of the auxiliary power amplification unit 530b forms a load modulation effect on the main power amplification unit 530a until both the main power amplification unit 530a and the auxiliary power amplification unit 530b maintain the same working state and the difference between the load impedance of the main power amplification path 510 and the load impedance of the auxiliary power amplification path 520 is less than the second threshold (including but not limited to the main power amplification unit 530a and the auxiliary power amplification unit 530b entering the saturation state and outputting the same power).

[0123] It should be noted here that in the embodiments of the present application, the specific values of the first threshold and the second threshold are not limited, and can be set according to the actual product requirements on the premise of not violating the inventive concept of the present application. For example, the first threshold can be 0 or any non-zero number.

[0124] In some specific embodiments, the initial load impedance of at least one main power amplification path is ZC, the number of auxiliary power amplification paths is M, and when the load impedance of at least one main power amplification path decreases to be equal to the load impedance of at least one auxiliary power amplification path, the load impedance of the at least one main power amplification path becomes ZC / (M + 1).

[0125] In some specific embodiments, the power amplifier system further includes a combiner (not shown in the figure), and the combiner (not shown in the figure) is connected between multiple power amplification paths and the output port RFOutput, and is used to perform power combination on the amplified signals output by all power amplification paths to obtain a combined output signal. Among them, in the embodiments of the present application, the combiner (not shown in the figure) is also implemented by using the power processing circuit described in Embodiment 1, and will not be elaborated here one by one.

[0126] In some specific embodiments, in order to optimize the impedance matching in the power amplification path, in a preferred embodiment, at least one power amplification path further includes an impedance matching circuit unit, where the impedance matching circuit unit is used to implement the impedance matching of the power amplification unit, and the impedance matching here may include input impedance matching on the signal input side of the power amplification unit, and output impedance matching on the signal output side of the power amplification unit or either one of them. Therefore, the impedance matching circuit may include at least one or a combination of an input impedance matching circuit unit and an output impedance matching circuit unit.

[0127] Refer to Figure 12As shown, specifically, taking the example where each power amplification path includes an impedance matching circuit unit, and each impedance matching circuit unit includes an input impedance matching circuit unit and an output impedance matching circuit unit. For example, the main power amplification path 510 includes an input impedance matching circuit unit 5501, a first impedance conversion network 540a, an input impedance matching circuit unit 5502, a main power amplification unit 530a, and an output impedance matching circuit unit 5601 that are sequentially connected between the power splitter 100 and the output port RFOutput. Among them, the input impedance matching circuit units 5501, 5502, and the output impedance matching circuit unit 5601 are respectively used to match the input impedance and the output impedance of the main power amplification unit 530a. The auxiliary power amplification path 520 includes an input impedance matching circuit unit 5503, an auxiliary power amplification unit 530b, an output impedance matching circuit unit 5602, and a second impedance conversion network 540a that are sequentially connected between the power splitter 100 and the output port RFOutput. Among them, the input impedance matching circuit unit 5503 and the output impedance matching circuit unit 5602 are respectively used to match the input impedance and the output impedance of the auxiliary power amplification unit 530b.

[0128] Figure 13 is a schematic diagram of the simulation results of the performance of the power amplifier system provided in Embodiment Six of the present application. Referring to Figure 13 shown, when the isolation resistors R105a and R105b are 100 ohm, power splitter port isolation can be achieved. Figure 14 is a schematic diagram of the simulation results of the performance of the power amplifier system provided in Comparative Example One of the present application. Referring to Figure 14 shown, when the two isolation resistors are 25 ohm, combiner port isolation can be achieved. Further referring to Figure 13 and Figure 14 shown, the power amplifier system provided in Embodiment Six of the present application has better balance at the two power splitter ports compared to the power amplifier system provided in Comparative Example One, and the 50 ohm CLIN (choke balun) can be cancelled, which is beneficial to reducing the size and insertion loss of the power combiner. And the feeding structure of the power amplifier system provided in Embodiment Five of the present application is simpler than that of the power amplifier system provided in Comparative Example One, that is, multiple amplifiers can be powered from the parallel connection point.

[0129] Figure 15 is a schematic diagram of the simulation results when the port of the auxiliary power amplification unit of the power amplifier system provided in Embodiment Six of the present application is open at the power splitter. Referring to Figure 15 shown, in this case, it cannot achieve 2 times impedance, but it can achieve a higher multiple impedance in the high frequency band. Figure 16 is a schematic diagram of the simulation results when the port of the auxiliary power amplification unit of the power amplifier system provided in Embodiment Six of the present application is short - circuited at the power splitter. Referring toFigure 16 As shown, in this case, it can achieve a 2-fold impedance over a wide frequency band. Figure 17 It is a schematic diagram of the simulation result when the port of the auxiliary power amplification unit of the power amplifier system provided in Comparative Example 1 is open at the power splitter. Refer to Figure 17 As shown, in this case, it can only achieve a 2-fold impedance in the low frequency band. Figure 18 It is a schematic diagram of the simulation result when the port of the auxiliary power amplification unit of the power amplifier system provided in Comparative Example 1 is short-circuited at the power splitter. Refer to Figure 18 As shown, in this case, it can achieve a 2-fold impedance over a wide frequency band.

[0130] Embodiment Seven

[0131] Figure 19 FIG. shows the architecture diagram of the power amplifier system provided in Embodiment Seven of the present application. The difference from Embodiment Six is that in the embodiment of the present application, the power amplifier system includes an input port RFlnput, an output port RFOutput, a plurality of power amplification paths, and a combiner 200. The combiner 200 and the plurality of power amplification paths are sequentially connected between the input port RFlnput and the output port RFOutput. Among them, the combiner 200 is implemented by using the power processing circuit described in Embodiment One. The other structures of the power amplifier system provided in the embodiment of the present application are the same as those in Embodiment Six, and will not be described in detail here.

[0132] Specifically, the combiner 200 is connected between the plurality of power amplification paths and the output port RFOutput, and is used to perform power combination on the amplified signals output by all the power amplification paths to obtain a combined output signal. Each power amplification path receives an input signal from the input port RFlnput. In some specific embodiments, the input signals received by each power amplification path have the same phase. The plurality of power amplification paths perform amplification processing on the same-phase input signal received from the input port RFlnput respectively to obtain each amplified signal.

[0133] In some specific embodiments, the load impedance of the main power amplification path 510 and the auxiliary power amplification path 520 is set to 100 ohm. At this time, the simulation results of the performance of the power amplifier system at 1, 3, and 5 GHz are as shown in Figure 20As shown, near 1 GHz, the gain begins to increase significantly. Near 2 GHz, the gain reaches its peak, approaching 0 dB. At a fundamental output power of 20 dBm, the efficiency is approximately 40%. As the output power increases to 35 dBm, the efficiency increases to nearly 70%. The phase varies within the range of fundamental output power from 0 dBm to 35 dBm, changing from approximately -100 degrees to nearly 0 degrees. At a fundamental output power of 5 dBm, the current is approximately 0.1 A. As the output power increases to 35 dBm, the current increases to above 0.4 A. The gain decreases as the output power increases. At a fundamental output power of 0 dBm, the gain is approximately 17 dB. As the output power increases to 35 dBm, the gain decreases to approximately 14 dB. At an available source power of 0 dBm, the fundamental power is approximately -10 dBm, and the third harmonic power is close to -20 dBm. As the power increases to 16 dBm, the fundamental power increases to nearly 40 dBm, and the third harmonic power increases to nearly 30 dBm. The output power of the amplifier increases as the input power increases. At an available source power of 0 dBm, the output power is close to 0 dBm. As the source power increases to 16 dBm, the output power increases to nearly 35 dBm.

[0134] Embodiment VIII

[0135] Figure 21 FIG. shows the architecture diagram of the power amplifier system provided in Embodiment VIII of the present application. The difference from Embodiment VII is that in the embodiment of the present application, the power amplifier system includes an input port RFlnput, an output port RFOutput, a plurality of power amplification paths, and a combiner 200. The combiner 200 and the plurality of power amplification paths are sequentially connected between the input port RFlnput and the output port RFOutput. Among them, the power amplification path includes one main power amplification path 510 and two auxiliary power amplification paths 520. The specific structure of the main power amplification path 510 is the same as that of the main power amplification path 510 in Embodiment VI, and the specific structures of the two auxiliary power amplification paths 520 are the same as those of the auxiliary power amplification paths 520 in Embodiment VI. The combiner is implemented by using the power processing circuit described in Embodiment II. The other structures of the power amplifier system provided in the embodiment of the present application are the same as those in Embodiment VII, and will not be elaborated here one by one.

[0136] Specifically, the combiner 200 is connected between multiple power amplification paths and the output port RFOutput, and is used to perform power combination on the amplified signals output by all power amplification paths to obtain a combined output signal. Each power amplification path receives an input signal from the input port RFlnput. In some specific embodiments, the input signals received by each power amplification path have the same phase. The multiple power amplification paths amplify the same-phase input signal received from the input port RFlnput respectively to obtain each amplified signal.

[0137] Similarly, in the embodiment of the present application, the power amplification unit of the main power amplification path 510 remains in the on state at low input power; while the power amplification units of the two auxiliary power amplification paths 520 are in the off state at low input power and are pushed by the input power to enter the class C or class B state at high input power, which is also called Peaking PA.

[0138] Through experiments by the applicant, when the system output power is less than the first threshold, the main power amplification path 510 is in the working state and the two auxiliary power amplification paths 520 are in the off state. At this time, only the main power amplification unit 530a is turned on and the two auxiliary power amplification units 530b are in the off state, presenting a low impedance state at the port of the combiner 200. When the system output power is not less than the first threshold, the two auxiliary power amplification paths 520 are in the working state. When the two auxiliary power amplification paths 520 are in the working state, they perform load modulation on the main power amplification path 510 to reduce the load impedance of the main power amplification path 510 until the difference between the load impedance of the main power amplification path 510 and the load impedance of the two auxiliary power amplification paths 520 is less than the second threshold. During this process, both the main power amplification unit 530a and the two auxiliary power amplification units 530b are turned on. However, at the beginning, the output powers of the main power amplification unit 530a and the two auxiliary power amplification units 530b are different, and the output power of the two auxiliary power amplification units 530b forms a load modulation effect on the main power amplification unit 530a until both the main power amplification unit 530a and the two auxiliary power amplification units 530b maintain the same working state and the difference between the load impedance of the main power amplification path 510 and the load impedance of the two auxiliary power amplification paths 520 is less than the second threshold (including but not limited to the main power amplification unit 530a and the two auxiliary power amplification units 530b entering the saturation state and outputting the same power).

[0139] It should be noted here that in the embodiment of the present application, the specific values of the first threshold and the second threshold are not limited, and can be set according to the actual product requirements on the premise of not violating the inventive concept of the present application. For example, the first threshold can be 0 or any non-zero number.

[0140] Figure 22 It is a schematic diagram of the simulation result of the performance of the power amplifier system provided in the eighth embodiment of the present application. Referring to Figure 22 as shown, the input port passes through a one-to-three power divider to achieve three-way signal output. The amplitudes of the three-way output signals are equal, the impedance of each output port is 3 times that of the input port, and the phases of the two signals entering the auxiliary amplifier are the same. Figure 23 It is a schematic diagram of the simulation result when the ports of the two auxiliary power amplification units of the power amplifier system provided in the eighth embodiment of the present application are short-circuited at the combiner. Referring to Figure 23 as shown, in this case, it can achieve 3 times impedance in a wide frequency band.

[0141] Comparative Example 1

[0142] Figure 24 shows a schematic diagram of the structure of the power processing circuit provided in Comparative Example 1. Referring to Figure 24 as shown, the circuit includes a first differential signal port 101′, two second differential signal ports 1021′ and 1022′, and a power processing unit 103′ connected between the first differential signal port 101′ and the two second differential signal ports 1021′ and 1022′. Among them, the power processing unit 103′ includes two pairs of differential coupled lines 1031′ and 1032′.

[0143] The first differential signal port 101′ includes a positive port 101a′ and a negative port 101b′. The second differential signal port 1021′ includes a positive port 1021a′ and a negative port 1021b′. The second differential signal port 1022′ includes a positive port 1022a′ and a negative port 1022b′.

[0144] The first pair of differential coupled lines 1031′ includes a positive coupled line 1031a′ and a negative coupled line 1031b′. The second pair of differential coupled lines 1032′ includes a positive coupled line 1032a′ and a negative coupled line 1032b′.

[0145] Further referring to Figure 24As shown, the positive terminal port 101a' of the first differential signal port 101' is connected to the positive coupling line 1031a' of the first pair of differential coupling lines 1031', and the negative terminal port 101b' of the first differential signal port 101' is connected to the negative coupling line 1032b' of the second pair of differential coupling lines 1032'. The difference from the first embodiment is that the negative coupling line 1031b' of the first pair of differential coupling lines 1031' is in series with the positive coupling line 1032a' of the second pair of differential coupling lines 1032'. The positive terminal port 1021a' of the second differential signal port 1021' is connected to the positive coupling line 1032a' of the second pair of differential coupling lines 1032', the negative terminal port 1021b' of the second differential signal port 1021' is connected to the negative coupling line 1031b' of the first pair of differential coupling lines 1031', the positive terminal port 1022a' of the second differential signal port 1022' is connected to the positive coupling line 1031a' of the first pair of differential coupling lines 1031', and the negative terminal port 1022b' of the second differential signal port 1022' is connected to the negative coupling line 1032b' of the second pair of differential coupling lines 1032'.

[0146] As a preferred implementation, in this comparative example, the power processing circuit further includes an isolation module, and the isolation module is arranged between the same terminal ports of different second differential signal ports. Taking the isolation resistor that can be used as the isolation module as an example, in specific implementation, the isolation resistor as the isolation module is arranged between the same terminal ports of different second differential signal ports. Specifically, a total of 2 isolation resistors (not marked in the figure) are provided. One isolation resistor is arranged between the positive terminal port 1021a' of the second differential signal port 1021' and the positive terminal port 1022a' of the second differential signal port 1022', and the other isolation resistor is arranged between the negative terminal port 1021b' of the second differential signal port 1021' and the negative terminal port 1022b' of the second differential signal port 1022'.

[0147] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other, and the differences between each embodiment and other embodiments are emphasized. In particular, for a system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and reference can be made to the corresponding part of the method embodiment for relevant details. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative efforts.

[0148] In the description of this specification, the descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0149] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of this application, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0150] Although the embodiments of this application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting this application. A person of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A power processing circuit, characterized in that: The device comprises a first differential signal port, N second differential signal ports, and a power processing unit connected between the first differential signal port and the N second differential signal ports, wherein the power processing unit comprises N pairs of first differential coupling lines, wherein N≥2; The positive coupling lines of the N pairs of the first differential coupling lines are all connected to the positive port of the first differential signal port, and the negative coupling lines of the N pairs of the first differential coupling lines are all connected to the negative port of the first differential signal port.

2. The power processing circuit according to claim 1, characterized in that: The positive port and the negative port of at least one second differential signal port are respectively connected to the positive coupling line and the negative coupling line of different pairs of first differential coupling lines.

3. The power processing circuit according to claim 1, characterized in that: The positive port and the negative port in each second differential signal port are respectively connected to the positive coupling line and the negative coupling line of different pairs of first differential coupling lines.

4. The power processing circuit according to claim 1, characterized in that: The power processing circuit also includes a pair of second differential coupling lines, wherein the positive coupling lines of the second differential coupling lines are connected between the positive port of the first differential signal port and the positive coupling lines of N pairs of the first differential coupling lines, and the negative coupling lines of the second differential coupling lines are connected between the negative port of the first differential signal port and the negative coupling lines of N pairs of the first differential coupling lines.

5. The power processing circuit according to claim 1, wherein: The input signal and the output signal of the power processing circuit are both single-ended signals, and the power processing circuit further includes a single-ended signal port and a balun; The balun is connected between the single-ended signal port and the first differential signal port and / or the second differential signal port.

6. The power processing circuit according to claim 1, wherein: The power processing circuit further includes an isolation module, which is arranged between the same-polarity ports of different second differential signal ports.

7. The power processing circuit according to claim 6, characterized in that: The isolation module includes an isolation resistor, or an isolation resistor and a capacitor connected in parallel.

8. The power processing circuit according to any one of claims 1 to 7, characterized in that: The power processing circuit is a power divider.

9. The power processing circuit according to claim 8, characterized in that: The first differential signal port serves as a differential signal input port, and the second differential signal port serves as a differential signal output port.

10. The power processing circuit according to any one of claims 1 to 7, characterized in that: The power processing circuit is a combiner.

11. The power processing circuit according to claim 10, characterized in that: The first differential signal port is used as a differential signal output port, and the second differential signal port is used as a differential signal input port.

12. A power amplifier system, characterized in that: The system includes an input port, an output port, and: A plurality of power amplification paths, all connected to the input port, including at least one main power amplification path and at least one auxiliary power amplification path, for amplifying one input signal received from the input port, wherein when the at least one auxiliary power amplification path is in a working state, load modulation is performed on the main power amplification path to reduce the load impedance of the main power amplification path; A power divider implemented by the power processing circuit according to any one of claims 1 to 11, connected between the input port and the plurality of power amplification paths, for distributing the power of an input signal input from the input port and dividing it into multiple signals for output; and / or, The combiner implemented by the power processing circuit according to any one of claims 1 to 11 is connected between the plurality of power amplification paths and the output port, and is used to perform power synthesis on the amplified signals output by all the power amplification paths to obtain a synthesized output signal.

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