Adaptive low density parity check decoder

Abstract

The present disclosure describes apparatuses and methods for implementing an adaptive low density parity check (LDPC) decoder that performs iterations on bit flipping or symbol flipping operations. In various aspects, an adaptive LDPC decoder (130) processes (704) a first portion of data using a first parameter, e.g., a flipping threshold, effective to change a state of the LDPC decoder, e.g., a comprehensive weight. The LDPC decoder selects (706) a second parameter of the LDPC decoder, such as an adaptive change flip threshold, based on the state of the LDPC decoder. The LDPC decoder then processes (708) the second portion of the data with the LDPC decoder using the second parameter, and provides (712) decoded data for the channel based at least on the processing of the first portion of the data using the first parameter and the processing of the second portion of the data using the second parameter. By adaptively changing decoding parameters based on the state of the decoder, the adaptive LDPC decoder can decode channel data with less decoding iterations or a higher success rate, thereby improving LDPC decoding performance.

Description

BACKGROUND OF THE INVENTION

[0001] Many computing and electronic devices transfer data to provide various functions of the devices. Data transfer systems, such as data transmission systems and data storage systems, typically feature data channels. For example, in a data transmission system, data can be transferred via channels such as printed circuit board (PCB) traces, cables, optical fibers, wireless protocols, etc. In a data storage system, the storage medium to which data is written and from which data is read can be considered a data channel of the data storage system. Thus, data storage data channels can include magnetic storage media, optical storage media, holographic storage media, solid-state storage media, etc.

[0002] The efficiency and reliability of a data channel can depend on many factors, such as the signal-to-noise ratio (SNR) of the channel. For example, a storage medium with a high SNR can generally store and retrieve data more accurately. On the other hand, a storage medium with a low SNR may result in a high data error rate, such as misreads or irrecoverable data. Similarly, the quality of a digital data communication channel depends on the SNR of the channel, where a high SNR communication channel can transfer data quickly and accurately, while a low SNR communication channel may have difficulty transferring data through the channel (e.g., dropped data packets).

[0003] Error correction codes (ECCs) can provide a way to reduce errors in data storage and transmission by introducing data redundancy into the communication channel, where the data redundancy is typically in the form of additional bits that can check the validity of the original data. ECCs use codewords, which are specific patterns of bits or symbols in the storage medium or transmission signal, to group data into chunks to be checked for errors. However, most ECCs are implemented with a static configuration, which may be suboptimal or not account for any changes in the data or the channel over which the data is transferred. This can lead to excessive ECC-related processing of the data or decoding failures of the data. Thus, a communication system or storage system with a static ECC configuration may be inefficient, reduce data throughput, suffer from data loss, or consume excessive power. SUMMARY OF THE INVENTION

[0004] This summary is provided to introduce a subject matter that is also described in the detailed description and the drawings. Therefore, this summary should not be considered as describing essential features or as limiting the scope of the claimed subject matter.

[0005] In some aspects, a method for adaptive low density parity check (LDPC) decoding includes processing a first portion of data of a channel using an LDPC decoder with a first parameter that effectively changes the state of the LDPC decoder. The method selects a second parameter of the LDPC decoder based on the state of the LDPC decoder, and processes a second portion of the data (e.g., during the same or a single iteration) using the second parameter with the LDPC decoder. Decoded data for the channel is provided based at least on the processing of the first portion of the data using the first parameter and the processing of the second portion of the data using the second parameter. In various aspects, an adaptive decoder may determine multiple portions or subsets of the data from the received data, and process each of the multiple portions using adaptively selected or determined decoding parameters. By adaptively changing the decoding parameters based on the state of the decoder, the adaptive LDPC decoder may decode the channel data with fewer decoding iterations or with a higher success rate, thereby improving LDPC decoding performance.

[0006] In other aspects, an apparatus includes a data interface configured to communicate via channel data, an LDPC decoder, and an adaptive controller for the LDPC decoder. The adaptive controller is configured to use the LDPC decoder and a first parameter to process a first block of data received from the channel to effectively change a metric of the LDPC decoder. The controller selects a second parameter for the LDPC decoder based on the metric of the LDPC decoder, and uses the LDPC decoder and the second parameter to process a second block of data. The adaptive controller provides decoded data for the channel from the LDPC decoder based at least on processing the first block using the first parameter and processing the second block using the second parameter.

[0007] In yet other aspects, a system on chip (SoC) is described that includes a media interface for accessing a storage medium of a storage system, a host interface for communicating with a host system, an LDPC decoder, and an adaptive controller for the LDPC decoder. The adaptive controller is configured to use the LDPC decoder and a first parameter to process a first block of data received from the channel to effectively change the state of the LDPC decoder. The controller selects a second parameter for the LDPC decoder based on the state of the LDPC decoder, and uses the LDPC decoder and the second parameter to process a second block of data. The adaptive controller then provides decoded data for the channel from the LDPC decoder based at least on processing the first block of data using the first parameter and processing the second block of data using the second parameter.

[0008] Details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Details of one or more implementations of an adaptive low - density parity - check (LDPC) decoder are set forth in the accompanying drawings and the following detailed description. In the drawings, the left - most digit of the reference numeral identifies the drawing in which the reference numeral first appears. The same reference numerals are used in different instances in the specification and drawings to indicate the same elements:

[0010] Figure 1 Shows an example operating environment of a system having an adaptive LDPC decoder implemented therein according to one or more aspects of the present disclosure;

[0011] Figure 2 Shows an example data channel in which aspects of adaptive LDPC decoding can be implemented by a decoder;

[0012] Figure 3 Shows an example configuration of a storage system including an adaptive LDPC decoder implemented according to one or more aspects;

[0013] Figure 4 Shows an example Tanner graph of LDPC data that can be processed by an adaptive LDPC decoder;

[0014] Figure 5 Shows an example algorithm that can be implemented by an adaptive LDPC decoder according to various aspects;

[0015] Figure 6 Shows an example algorithm of adaptive LDPC decoding using a threshold based on comprehensive adjustment of the LDPC decoder;

[0016] Figure 7 Depicts an example method for adaptive LDPC decoding according to one or more aspects;

[0017] Figure 8 Depicts an example method for implementing adaptive LDPC decoding based on the comprehensive of the decoder;

[0018] Figure 9A and Figure 9B Depicts an example method for selecting decoding parameters of an adaptive LDPC decoder based on the state of the decoder;

[0019] Figure 10 Depicts an example method for selecting parameters of an adaptive LDPC decoder based on the result of processing data using a parameter combination;

[0020] Figure 11 Shows an example system - on - chip (SoC) environment in which aspects of adaptive LDPC decoding can be implemented; and

[0021] Figure 12An example storage system controller of an adaptive LDPC decoder implemented in accordance with one or more aspects is shown; DETAILED DESCRIPTION

[0022] Many computing and electronic devices transfer data to provide various functions of the devices. Data transmission systems, such as data transfer systems and data storage systems, are typically characterized by data channels. Generally, error correction codes (ECCs) can provide a way to reduce errors in data storage and transmission by introducing data redundancy into a communication channel, which is typically in the form of extra bits that can check the validity of the original data. ECCs use codewords, which are specific patterns of bits or symbols in a storage medium or a transmitted signal, to group data into chunks to be checked for errors. However, most ECCs are implemented with a static configuration (e.g., preset static rules), which may be suboptimal or unable to account for any changes in the data or the channel over which the data is transmitted. Thus, a communication system or a storage system with a static ECC configuration may be inefficient, reduce data throughput, suffer from data loss, or consume excessive power.

[0023] This disclosure describes apparatus and techniques for adaptive low-density parity-check (LDPC) decoding. Compared with prior ECC techniques, the described apparatus and techniques can implement an adaptive LDPC decoder that dynamically changes or selects decoding rules (e.g., thresholds) based on the state of the decoder, enabling the decoder to adapt dynamically during the decoding process. By doing so, the adaptive LDPC decoder can achieve faster convergence in a bit-flipping decoder, increase decoder throughput, reduce decoder latency, or reduce the average number of processing iterations required to decode data. Generally, the described aspects can implement an adaptive decoding process in which a bit-flipping or symbol-flipping decoder can employ dynamic flipping rules within an iteration of the decoding process. In some implementations of adaptive decoding, the decoding rules (e.g., flipping thresholds) are adaptively changed based on the state (e.g., metric) of the decoder at each point in the decoding (e.g., real-time state within each decoding iteration), rather than using a fixed rule value for all bits in the LDPC code of the data being decoded throughout a given iteration.

[0024] In various aspects, the state of the decoder can include one or more of the following: a combined weight, a column weight, the LDPC code being decoded, an iteration index, a block index, whether a bit (or symbol) is flipped or not (e.g., a flip state), etc. Thus, in addition to the number of iterations or the flip state of the bits, the adaptive controller of the LDPC decoder can set or select a decoding rule (e.g., a flip threshold) based on the real-time state of the decoder. In some aspects, the adaptive controller uses the sum of the combined values (the current combined weight) in the LDPC decoder as the state of the decoder for adaptively selecting or setting the decoding rule. In other words, when the current combined weight of the decoder changes in real time, the adaptive controller of the LDPC decoder changes the decoding rule (e.g., the flip threshold) in the decoder in real time or dynamically during the decoding iterations. Alternatively or additionally, the adaptive LDPC decoder can use the state to select or set different decoding rules for decoding different blocks in the LDPC decoder. For example, the blocks in the decoder can include multiple bits of bit nodes in the LDPC having the same or different types or degrees. In one implementation, the adaptive controller can divide the data to be decoded or the entire LDPC code into multiple M blocks. The adaptive controller can determine any suitable number of data blocks (e.g., a portion or subset of the data), which can range from at least two blocks to several blocks or dozens of blocks, depending on the complexity of the LDPC decoder. One block can include or correspond to one type of bit, while another block can include or correspond to another type of bit. Generally, the number of bit types in the data being decoded can be the same as or different from the number of blocks. Thus, the adaptive LDPC decoder can be configured to divide or form the bits of the data into two types (T = 2), but having three different blocks (M = 3). As an example, multiple blocks can cover the same type, such that two blocks cover the first type and one block covers the second type. These are just several examples of the adaptive LDPC decoder, which are described in detail along with other examples throughout this disclosure.

[0025] In various aspects of adaptive LDPC decoding, an adaptive LDPC decoder processes a first portion of data using a first parameter that effectively changes the state of the LDPC decoder. The LDPC decoder selects a second parameter of the LDPC decoder based on the state of the LDPC decoder. The LDPC decoder then processes a second portion of the data using the second parameter with the LDPC decoder and provides decoded data of the channel based at least on the processing of the first portion of the data using the first parameter and the processing of the second portion of the data using the second parameter. In various aspects, the adaptive decoder can determine multiple portions or subsets of the data from the received data and process each of the multiple portions using adaptively selected or determined decoding parameters. By adaptively changing the decoding parameters based on the state of the decoder, the adaptive LDPC decoder can decode channel data with fewer decoding iterations or with a higher success rate, thereby improving LDPC decoding performance.

[0026] The following discussion describes an operating environment and a system-on-chip (SoC) in which components of the operating environment can be implemented. In the context of the present disclosure, the operating environment or various components are referenced only by way of example.

[0027] Operating Environment

[0028] Figure 1 An example operating environment 100 is shown with a host system 102 capable of storing, accessing, or transmitting various forms of data or information. Examples of the host system 102 can include a laptop computer 104, a desktop computer 106, and a server 108, any of which can be configured as a user device, a computing device, or part of a storage network, a data storage center, cloud storage, etc. Further examples of the host system 102 (not shown) can include a tablet computer, a set-top box, a data storage appliance, a wearable smart device, a television, a content streaming device, a high-definition multimedia interface (HDMI) media stick, a smart device, a home automation controller, a smart thermostat, an Internet of Things (IoT) device, a mobile Internet device (MID), a network-attached storage (NAS) drive, an aggregated storage system, a game console, an automotive entertainment device, an automotive computing system, an automotive control module (e.g., an engine or powertrain control module), etc. Generally, the host system 102 can transmit or store data for any suitable purpose, such as enabling the functionality of a particular type of device, providing a user interface, enabling network access, implementing a game application, playing back media, providing navigation, editing content, providing data storage, etc.

[0029] The host system 102 includes a processor 110 and a computer-readable medium 112. The processor 110 can be implemented as any suitable type or number of processors (single-core or multi-core) for executing instructions or commands of an operating system or other applications of the host system 102. In various aspects, the processor 110 of the host system can execute tenants, services, or workloads of a data storage system or a data storage center. The computer-readable medium 112 (CRM 112) includes a memory (not shown) and a storage system 114 of the host system 102. The memory of the host system 102 can include any suitable type or combination of volatile memory or non-volatile memory. For example, the volatile memory of the host system 102 can include various types of random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), etc. The non-volatile memory can include read-only memory (ROM), electrically erasable programmable ROM (EEPROM), solid-state storage media, or flash memory.

[0030] The storage system 114 of the host system 102 can be configured as any suitable type of data storage system, such as a data storage center, a storage device, a storage drive, a storage array, a storage volume, etc. Although described with reference to the host system 102, the storage system 114 can also be implemented separately as an independent device or as part of a larger storage collection, such as a network-attached storage device, an external storage drive, a data storage center, a server farm, or a virtualized storage system (e.g., for cloud-based storage or services). Examples of the storage system 114 include a magnetic storage media drive 116, a fast non-volatile memory (NVMe) solid-state drive (not shown), a fast peripheral component interconnect (PCIe) solid-state drive 118, a solid-state drive 120 (SSD 120), and a storage array 122, which can be implemented using any combination of storage devices or storage drives.

[0031] The storage system 114 includes a storage medium 124 and a storage medium controller 126 (storage controller 126) for managing various operations or functions of the storage system 114. The storage medium 124 may include or be formed of a non-volatile memory device on which data 128 or information of the host system 102 is stored. The storage medium 124 may be implemented using any type or combination of storage media, which may include optical storage media, magnetic storage media, holographic storage media, solid-state storage media, etc. In various aspects, the solid-state memory medium may include one of the following: flash memory, NAND flash memory, RAM, DRAM (e.g., for caching), SRAM, etc. For example, the storage medium 124 of the storage system 114 may include NAND flash memory, single-level cell (SLC) flash memory, multi-level cell (MLC) flash memory, triple-level cell (TLC) flash memory, quad-level cell flash memory (QLC), NOR cell flash memory, or any combination thereof. These memories may store, individually or in combination, data associated with users, applications, tenants, workloads, services, and / or operating systems of the host system 102.

[0032] Generally, the storage controller 126 manages the operations of the storage system 114 and enables the host system 102 to access the storage medium 124 for data storage. The storage controller 126 may be implemented by any suitable combination of hardware, firmware, or software to provide various functions of the storage system 114. The storage controller 126 may also conduct or manage internal tasks or operations associated with the storage medium 124, which may include data placement, data-to-block mapping, wear leveling, data caching, data migration, garbage collection, thermal management (e.g., throttling), power management, etc. Thus, the storage controller 126 may receive read requests (e.g., host I / O) for data access from the host system 102 and queue (or generate) internal commands (e.g., I / O) associated with the internal operations of the storage medium 124. Generally, the storage controller 126 may perform media I / O for accessing the storage medium 124, which corresponds to scheduling host I / O for data access (e.g., host write requests or read requests) and / or internal I / O for internal operations or tasks associated with the storage medium 124.

[0033] In this example, the storage controller 126 also includes an adaptive LDPC decoder 130 (LDPC decoder 130), decoding parameters 132, decoding metrics 134, and an adaptive decoder controller 136 (adaptive controller 136). Although not shown, the LDPC decoder 130 may include one or more processing blocks for implementing the decoding of LDPC-encoded data, such as data received through a channel (e.g., a storage channel or a communication channel from a transmitter). In other configurations, the LDPC decoder 130 and the adaptive controller 136 may be implemented combinatorially as an adaptive LDPC decoder. Thus, the adaptive LDPC decoder 130 may include a controller or control circuitry configured to implement various aspects of adaptive LDPC decoding. In some implementations, the decoding parameters 132 may include a set of decoding rules or thresholds stored in a lookup table, which may be implemented in hardware or in a memory associated with the LDPC decoder 130.

[0034] In various aspects, the LDPC decoder 130 and / or the adaptive controller 136 use the parameters 132 and the metrics 134, which can be used to dynamically configure the parameters 132 for decoding data read from the storage medium 124 of the storage system 114. Generally, the LDPC decoder 130 and the adaptive controller 136 may implement adaptive decoding of ECC data read from the storage medium 124 of the storage system 114. In some cases, the LDPC decoder 130 processes a first portion of the data, and the adaptive controller 136 obtains a state or metric from the LDPC decoder 130 that has changed or been updated in response to processing the first portion of the data. The adaptive controller 136 then selects or changes the parameters 132 based on the state or metric of the LDPC decoder for use in decoding a second portion of the data. The selected decoding parameters provided by the adaptive controller 136 may enable the LDPC decoder 130 to decode the data with fewer decoding iterations or with a higher success rate, thereby improving LDPC decoding performance.

[0035] For example, the LDPC decoder 130 processes a first portion of data received from the channel using a first parameter that effectively changes the state of the LDPC decoder (e.g., the overall weight). The adaptive controller 136 selects a second parameter of the LDPC decoder, such as a bit flip threshold or a symbol flip threshold, based on the state of the LDPC decoder. Then, the LDPC decoder 130 processes a second portion of the data using the second parameter with the LDPC decoder and provides decoded data of the channel based at least on the processing of the first portion of the data using the first parameter and the processing of the second portion of the data using the second parameter. By adaptively changing the decoding parameters based on the state of the decoder, the LDPC decoder can decode the channel data with fewer decoding iterations or with a higher success rate, thereby improving the LDPC decoding performance. This is just one example of adaptive LDPC decoding, and other examples of adaptive LDPC decoding are described throughout the disclosure.

[0036] Return to Figure 1 , the host system 102 may further include an I / O port 138, a graphics processing unit 140 (GPU 140), and a data interface 142. Generally, the I / O port 138 allows the host system 102 to interact with other devices, peripherals, or users. For example, the I / O port 138 may include a universal serial bus, a human interface device, an audio input, an audio output, etc. or be coupled to a universal serial bus, a human interface device, an audio input, an audio output, etc. The GPU 140 processes and renders graphics-related data for the host system 102, such as user interface elements of the operating system, applications, etc. In some cases, the GPU 140 accesses a portion of the local memory to render graphics or includes dedicated memory (e.g., video RAM) of the host system 102 for rendering graphics.

[0037] The data interface 142 of the host system 102 provides connectivity to one or more networks and other devices connected to these networks. The data interface 142 can include a wired interface, such as an Ethernet or fiber optic interface for communicating over a local network, intranet, or the Internet. Alternatively or additionally, the data interface 142 can include a wireless interface facilitating communication over a wireless network (such as, wireless LAN, wide area wireless network (e.g., cellular network), and / or wireless personal area network (WPAN)). Aspects described herein can be used to decode any data transmitted through the I / O port 138 or the data interface 142. For example, the decoder of the data interface can be configured as an adaptive LDPC decoder and implement one or more of the techniques described for decoding data received over a communication channel. Alternatively or additionally, data read from the storage system 114 of the host system 102 can be decoded and / or re-encoded according to one or more aspects of adaptive LDPC decoding for communication through the data interface 142.

[0038] Figure 2 An example of a data channel is shown at 200 where aspects of adaptive LDPC decoding can be implemented by the decoder; generally, the shown data channel can represent a medium through which data is sent to a receiver, or to which data is stored and read from. In some cases, Figure 2 the data channel represents a medium in which the encoded data is exposed to noise or interference, such as a wired medium, wireless medium, optical medium, storage medium, etc. Thus, the noise or interference of the data channel can alter (e.g., introduce coding errors) any encoded and / or modulated data sent through an electronic device or stored to the data channel. As described herein, aspects of adaptive LDPC decoding can improve decoder performance to correct such errors in fewer decoding iterations, reduced decoder latency, or with a higher error correction success rate.

[0039] At Figure 2In the context of the data channel, user information 202 is encoded by an encoding mechanism, which is shown as LDPC encoder 204 in this example. User information 202 can include any suitable type of information or data (e.g., message information, message vector), which can be grouped into units of k symbols, where each symbol can be binary, ternary, quaternary, or any other suitable type of data. For simplicity, the implementation of the present disclosure will be described in terms of binary bits or symbols (e.g., LDPC codes over a Galois field). For example, the described aspects can be applied to symbol flipping decoders for non-binary LDPC codes (e.g., LDPC codes over Galois field GF(q)), where the field size q is greater than 2. Note that LDPC codes over GF(2) include the binary LDPC codes described throughout the present disclosure. During the process of encoding user information 202, the encoding block can use any suitable code to achieve different results. In this example, LDPC encoder 204 encodes user information 202 using an LDPC code to generate one or more codewords of the encoded information (not shown). LDPC encoder 204 can be configured to implement various LDPC encoding schemes or generate one or more codewords of a predetermined length. In various aspects, LDPC encoder 204 provides or sends the codewords to modulator 206, which prepares the codewords for transmission over channel 208. As an example, modulator 206 can modulate the codewords using phase shift keying, frequency shift keying, quadrature amplitude modulation, or any suitable modulation technique to convert the codewords into one or more information-bearing signals. Then the encoded data or modulated data can be written or stored to channel 208, which represents the medium through which the information-bearing signal propagates (e.g., optical or electrical signal) or to which the information-bearing signal is stored. For example, channel 208 can represent a wired or wireless medium of a communication system, an optical communication system (e.g., optical fiber or free space), a solid-state medium (e.g., RAM, ROM), a magnetic medium (e.g., hard disk, tape drive), or an optical medium (e.g., DVD, holographic) storage medium, where the information-bearing signal can be stored.

[0040] Due to interference signals and other types of noise and phenomena, channel 208 may affect or corrupt the information-bearing signal generated by modulator 206. Accordingly, the waveform of the information-bearing signal received by demodulator 210 may be different from the original waveform of the information-bearing signal entering channel 208. Demodulator 210 demodulates the information-bearing signal passing through or received from channel 208 and may implement filtering, multiplication by a periodic function, or any suitable demodulation technique corresponding to the type of modulation implemented by modulator 206. Due to the non-ideal nature of channel 208 (e.g., noise), the result of demodulation may include demodulated bits or a bit stream (e.g., received vector) that may include errors due to channel corruption.

[0041] To recover data from the demodulated signal (e.g., received vector), decoding block 212 may decode the bit stream or vector to detect and / or remove errors generated by channel 208. In this example, decoding block 212 includes adaptive LDPC decoder 130, processing block 214, decoding parameter 132 (parameter 132), decoding metric 134 (metric 134), and adaptive controller 136. Generally, LDPC decoder 130 may detect and / or correct errors in data received from a channel, such as encoded information read from a storage medium. LDPC decoder 130 may implement an iterative decoding algorithm (e.g., flood decoding, layered decoding, bit flip decoding, symbol flip decoding) to detect and / or correct errors in the demodulated data or vector provided by demodulator 210. In aspects, LDPC decoder 130 is configured as a bit flip decoder to iteratively decode noisy data received from channel 208. LDPC decoder 130 may provide information, such as an LDPC vector or a bit flip vector, to processing block 214. Generally, processing block 214 may receive any relevant information from LDPC decoder 130. In some cases, processing block 214 receives information from LDPC decoder 130 for computations to be performed by the decoder during iteration. In some implementations, LDPC information is received in vector form (e.g., LDPC vector) that may include or correspond to the number of unsatisfied check vectors (NUC vectors) for each bit node or group of bit nodes (e.g., bits of a codeword) in the LDPC decoder. In aspects, processing block 214 may convert LDPC vector 508 (or NUC vector) and bit flip vector 510 to decoding metric 134 (e.g., decoder state) of LDPC decoder 130, which may include NUC state, where the NUC state may indicate the number of unsatisfied checks for a bit node or block of bit nodes.

[0042] When utilizing such an iterative algorithm, the LDPC decoder 130 may perform several iterations of bit - flipping operations until the output of the adaptive LDPC decoder 130 converges to a valid codeword. As described herein, during the decoding process, the adaptive controller 136 may select or change the decoding parameters 132 based on the decoding metric 134 (e.g., state, state information) of the LDPC decoder 130 during the decoding iterations. For example, the adaptive controller 136 may obtain the metric 134 (e.g., LDPC state information, combined weights) from the LDPC decoder 130 during the decoding iterations and select one or more different bit - flipping thresholds for decoding the remaining bits in the iterations of the decoding process. When the LDPC decoder 130 converges to a valid codeword or reaches the maximum iteration limit, the adaptive LDPC decoder 130 provides decoding information 216, which may correspond to the original user information 202 transmitted through the channel 208 if the error correction of the adaptive LDPC decoder is successful.

[0043] Figure 3 An example configuration of a storage system including an adaptive LDPC decoder implemented according to one or more aspects is shown at 300; in this example, the storage controller 126 of the storage system 114 includes an instance of the LDPC decoder 130, the processing block 214, and the adaptive controller 136, which may be implemented as a decoding block of the storage controller 126 or as part of a decoding block of the storage controller 126. The storage controller 126 may be configured to manage or implement access by the host system 102 to any suitable type of storage medium 124 and may include or implement corresponding functions, such as a flash translation layer (not shown), etc. The adaptive decoder 130 and / or the adaptive controller 136 may interact with the storage controller 126 or its components to implement aspects of adaptive LDPC decoding.

[0044] In this example, the LDPC decoder 130 and the adaptive controller 136 are shown in the context of a storage system 114 implemented as an instance of a solid - state storage drive (SSD) 120. The SSD 120 may be coupled to any suitable host system 102 and implemented using a storage medium 124 including a plurality of NAND flash chips (not shown). Alternatively, the example storage system may be implemented with magnetic storage media, optical storage media, etc. Although illustrated as components of the SSD 120, the adaptive LDPC decoder 130, the processing block 214, and / or the adaptive controller 136 may be implemented separately from or external to the storage system 114. In some cases, the adaptive LDPC decoder 130 or the adaptive controller 136 is implemented as part of a storage medium accelerator or an aggregated storage controller coupled between the host system 102 and one or more storage systems 114.

[0045] Typically, the operation of SSD 120 is enabled or managed by an instance of storage controller 126, which in this example includes a host interface 302 for enabling communication with host system 102 and a media interface 304 for enabling access to storage medium 124. The host interface 302 may be configured to implement any suitable type of storage interface or protocol, such as Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), PCIe, Advanced Host Controller Interface (AHCI), NVMe, NVM-over Fabric (NVM-OF), NVM Host Controller Interface Specification (NVMHCIS), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Secure Digital I / O (SDIO), Fibre Channel, any combination of these protocols (e.g., M.2 or Next Generation Form Factor (NGFF) combination interface), etc. Alternatively or additionally, the media interface 304 may implement any suitable type of storage media interface, such as a flash interface, a flash bus channel interface, a NAND channel interface, a Physical Page Addressing (PPA) interface, a read / write channel interface (e.g., for magnetic media), etc.

[0046] In various aspects, the components of storage controller 126 provide a data path through the controller between the host interface 302 to host system 102 and the media interface 304 to storage medium 124. In this example, storage controller 126 includes a processor core 306 for executing a kernel, firmware, or driver to implement the functions of storage controller 126. In some cases, the processor core 306 may also execute processor-executable instructions to implement the adaptive LDPC decoder 130 or the adaptive controller 136 of storage controller 126. Alternatively or additionally, the adaptive LDPC decoder 130 or the adaptive controller 136 may execute or run on ML dedicated hardware, an AI engine, or the processor core.

[0047] As Figure 3As shown, the structure 308 of the storage controller 126 (which may include control and data buses) operably couples the components of the storage controller 126 and enables communication between the components of the storage controller 126. For example, the adaptive LDPC decoder 130 or the processing block 214 may communicate with the host interface 302, the processor core 306 (e.g., firmware), or the media interface 304 to exchange data, decode information, commands, or I / O within the storage controller 126. In various aspects, the adaptive LDPC decoder 130 may implement adaptive decoding of information (e.g., codewords) read from the storage medium 124, which may be performed in response to a read request from the host system 102. Generally, the adaptive LDPC decoder 130 and the processing block 214 may use the adaptive controller 136 to implement aspects of adaptive decoding, where the decoding rules or thresholds of the LDPC decoder are dynamically adjusted or selected based on the state, state information, or metrics of the LDPC decoder during decoding iterations to provide error detection and / or error correction for data read from the storage medium 124. The static random access memory 310 (SRAM 310) of the storage controller 126 may store processor-executable instructions or code for the firmware or drivers of the storage controller, which may be executed by the processor core 306. The storage controller 126 may also include a dynamic random access memory (DRAM) controller 312 and an associated DRAM 314 for storing or caching various data when the storage controller 126 moves data between the host system 102, the storage medium 124, and other components of the storage controller.

[0048] Figure 4 An example Tanner graph of LDPC data that may be processed by an adaptive LDPC decoder is shown at 400; in the context of a storage or communication system, data received from a channel may include encoded data or codewords that the LDPC decoder 130 (not shown) attempts to decode to provide or reproduce the original data written or transmitted to the channel. In the context of a storage system, when data is read from a storage medium such as NAND flash, the data may include bit errors (e.g., a 0 is flipped to a 1, a 1 is flipped to a 0). Generally, an encoder may apply an LDPC code to data before transmitting the data over a communication channel (e.g., before writing to a storage medium), and the adaptive LDPC decoder 130 may decode the LDPC-encoded data after receiving the encoded data from the communication channel (e.g., after reading from a storage medium). In various aspects, the adaptive LDPC decoder is implemented as a bit-flipping LDPC decoder, which may flip bits when decoding the encoded data to potentially flip incorrect bits to the original values transmitted or written to the channel.

[0049] As an example and as Figure 4As shown, an LDPC code is typically defined by a parity-check matrix H402, such as a codeword for encoding bits and the like. An LDPC code can also be represented by a bipartite Tanner graph 404 of encoded bits 406, where each bit "1" in the parity-check matrix H402 is represented by an edge between a corresponding variable node 408 (column) and a corresponding check node 410 (row). In some cases, the variable node 408 can also be referred to as a bit node. During the decoding process, the adaptive LDPC decoder 130 can compute a syndrome vector 412 (e.g., "syndrome"), as shown in Equation 1.

[0050] Syndrome = H·z, where z represents the received bit vector Formula 1: LDPC Syndrome

[0051] For example, the received bit vector z can represent a noisy version of the encoded data written or stored to a channel, such as a solid-state or magnetic storage medium. The weight of the syndrome vector can be referred to as the syndrome weight, which can be computed as the sum of the syndrome vector entries, and the syndrome vector entries are 0 and 1. As Figure 4 shown, each circular node corresponds to an encoded bit or variable node 408. The number of lines between a variable node 408 (or bit node) and a square check node 410 can be referred to as the "type of bit", which can also be referred to as the degree of the bit node (or the degree of the variable node). The degree of this type of bit or bit node is equal to the number of 1s in each column of the parity-check matrix H402 corresponding to the Tanner graph 404. For example, as Figure 4As shown, the variable node 408 (the leftmost one) is connected to the corresponding check node 410 by two lines, which means that this variable node is a type-2 (degree-2) node, and the number of 1s in the first column of the parity-check matrix H is 2. The next variable node is connected to the corresponding check node 410 by three lines, which means that it is a type-3 (degree-3) node, and the number of 1s in the second column of the parity-check matrix H is 3. Generally, aspects of adaptive LDPC coding can be related to or of interest in LDPC codes that can have one, two, three, or more different bit types, such that the methods described herein can be applied to all such LDPC code configurations. Thus, the described aspects of adaptive decoding can be applied to symbol-flipping decoders, such as Galois-field-based symbols that can have four states, eight states, etc. As shown at 414, when the received or read bit is noisy, generally the syndrome vector of the bit is a non-zero vector, and the syndrome weight is greater than 0. Alternatively, when the received or read bit has no noise, the syndrome vector is a zero vector (e.g., the entries are zero) and the syndrome weight is 0. In aspects, the LDPC decoder 130 and the adaptive controller 136 can interactively process (e.g., flip bits) the noisy bits of the data or the codeword until the syndrome 412 or the syndrome weight of the codeword approaches zero, which means that the errors in the received or read bits have been corrected.

[0052] In aspects of adaptive decoding, the LDPC decoder 130 and the adaptive controller 136 implement an adaptive decoding process, where the bit-flipping or symbol-flipping parameters (e.g., rules, thresholds) of the decoder are dynamically updated during the iterations of the decoding process. In some implementations of adaptive decoding, the decoding parameters (e.g., flip threshold) are adaptively changed based on the state of the decoder (e.g., metric) per block (e.g., the real-time state within each decoding iteration) during decoding, rather than the decoder using a fixed rule value for all bits in the LDPC code of the data being decoded throughout a given iteration.

[0053] The state of the decoder can include one or more of the following: synthesis weights, column weights of the parity check matrix, the LDPC code being decoded, the bit positions of the bits or variable nodes, iteration indices, block indices, whether a bit (or symbol) is flipped or not (e.g., flip state), etc. Thus, in addition to the number of iterations or flip state of the bits, the adaptive controller 136 can set or select decoding parameters (e.g., flip threshold) based on the real-time state of the decoder. In some aspects, the adaptive controller uses the sum of the synthesis values in the LDPC decoder (current synthesis weights, parity check constraints) as the state of the decoder 130 for adaptively selecting or setting decoding rules. In other words, when the current synthesis weights of the decoder change in real time, the adaptive controller 136 changes the decoding parameters (e.g., flip threshold) in the decoder in real time or dynamically during decoding iterations.

[0054] In the context of a block of variable nodes 408 or bit nodes, the LDPC decoder 130 or the adaptive controller 136 can divide the matrix or graph of variable bits 408 or data bits into blocks of variable bits or other suitable subsets. For example, a block in the decoder can include multiple bits of bit nodes in the LDPC graph (e.g., the data set being decoded) having the same or different types or degrees. In one implementation, the adaptive controller 136 can divide the data to be decoded or the entire LDPC code into multiple M blocks. One block can include or correspond to one type of bit, while another block can include or correspond to another type of bit. Generally, the number of bit types “T” in the data being decoded can be the same as or different from the number of blocks “M” into which the data is divided. Thus, the adaptive LDPC decoder can be configured to divide or form the bits of the data into two types (T = 2), but have 3 different blocks (M = 3). As an example, multiple blocks can cover the same type, such that two blocks cover the first bit type and one block covers the second bit type. As an example, consider Figure 4 the variable nodes shown in 418, which are divided into three block types. In this example, box 1 420 includes a first subset of type-2 variable nodes 408, box 2 422 includes a second subset of type-2 variable nodes 408 at different bit positions (or ranges of bit positions, e.g., bits 1 to 3, 4 to 6, etc.), and box 3 424 includes a subset of type-3 variable nodes 408, and so on.

[0055] Figure 5An example algorithm that can be implemented by an adaptive LDPC decoder according to various aspects is shown at 500; although described with reference to a bit - flip decoder, aspects of algorithm 500 can also be applied to other types of decoders, including symbol - flip decoders, etc. Generally, a bit - flip decoder can implement a hard - decision decoding algorithm for LDPC codes. For example, at the decoding iteration number i, the decoder or processing block calculates the number j of unsatisfied check nodes connected to a variable node (e.g., variable node 408), which can be represented as U j (for variable node j). Then, the decoder or processing block compares this number with a bit - flip threshold (t i ), and if the number of unsatisfied check nodes U j exceeds the threshold, the decoder flips the variable node j (flips the bit value j), otherwise retains the bit value for the variable node (does not flip the bit value j). During the iteration, the adaptive decoder can perform this bit - flip comparison for corresponding bits of a bit subset or bit block using different decoding parameters 132 (e.g., the threshold).

[0056] In various aspects, the adaptive controller 136 can change, select, or modify decoding parameters based on the state of the decoder, and the state of the decoder can include one or more various metrics 134. For example, the adaptive controller 136 can be configured to select decoding parameters 132 based on the combined weight of variable nodes and the bit - flip state. In some implementations, the adaptive controller includes or has access to a table of decoding parameters (e.g., bit - flip threshold), and the decoding parameters are accessed or selected based on the combined weight of variable nodes and the bit - flip state. Thus, the table can include ranges of combined weights and threshold pairs (t 1(i) ,t 2(i) ) selected based on the current combined weight of the decoder and whether the variable node j is equal to the received bit j of the channel. In the context of this example, the adaptive controller selects a threshold pair based on the current combined weight of the decoder, and then based on whether the variable node j received by the decoder has been flipped (t 1(i) , the flipped threshold) or has not been flipped (t 2(i) , the non - flipped threshold), compares the number (Uj) of unsatisfied check nodes connected to variable node j with one of the values in the threshold pair. Based on the comparison, if the number of unsatisfied check nodes U jIf the selected threshold is exceeded, the decoder or processing block flips the value j of the bit node; otherwise, the bit value of the variable node is retained (the bit value j is not flipped). The LDPC decoder 130 can continue this process throughout the decoding iterations, selecting different bit flip thresholds for the variable nodes based on the combined weights of the decoder and the bit flip status of the variable nodes. Alternatively or additionally, the adaptive controller 136 can use any combination of decoding metrics, such as two or more of the following: combined weights, the bits of the data or the bit positions of the variable nodes, the LDPC code implemented by the LDPC decoder, the degree of one or more bits of the data (e.g., the type of bit), the block index of the LDPC decoder, the iteration index of the LDPC decoder, etc. At the end of the iteration, the LDPC decoder or the adaptive controller calculates the combined updated sum and stores the decoded output (e.g., decoded_word). These decoding iterations can be repeated for several iterations (i = 1, 2, 3, …, K) until the combined sum (combined weight) reaches 0 or the maximum allowed number of iterations K is reached.

[0057] Return to Figure 5 Referring to the algorithm shown, the adaptive LDPC decoder can implement the operations of the algorithm to decode data received from a channel such as a storage channel or a communication channel. At 502, the adaptive LDPC decoder receives the bits to be decoded from the channel, and in some implementations, divides the graph or matrix of bits into bit blocks for processing during the decoding iterations. The adaptive decoder can determine or divide the received data into multiple subsets or portions for decoding. For example, the adaptive decoder can divide the data into two portions, three portions, four portions, etc. At 504, the adaptive LDPC decoder or the adaptive controller determines the current decoding metric, which can include combined weights, the column weights of the parity check matrix, the LDPC code being decoded, the block index, whether the bit (or symbol) has been flipped (e.g., the flip status), etc. At 506, the adaptive LDPC decoder can also determine the iteration index of the current iteration of the decoding performed by the decoder, and if the iteration is exceeded at 508, it can indicate that the decoding of the bits has not been completed after several iterations. Otherwise, the adaptive LDPC decoder or the adaptive controller determines the flip threshold for the current portion (e.g., subset or block) of the bit nodes being decoded at 510.

[0058] At 512, the adaptive LDPC decoder flips the bits of the current portion of bits with a number of unsatisfied checks greater than a threshold, and then at 514 updates the syndrome of the decoder. Note that the syndrome of the decoder may change or be updated after each bit flip, and the decoder may track syndrome updates or syndrome weights on a per-bit-flip basis, which may allow for dynamic adjustment of the decoding rules or thresholds. Thus, the adaptive decoder may use multiple corresponding sets of decoding parameters (e.g., three to six adaptively selected sets of decoding parameters) to process multiple portions of the received data or bits (e.g., three to six data subsets). At 516, the adaptive LDPC decoder sums the syndrome updates at the end of the decoding iteration, and if the syndrome sum equals zero, the adaptive LDPC decoder provides the decoded data as a decoding success at 518. Otherwise, the adaptive LDPC decoder feeds back the current iteration of decoded bits including the flipped bits for another iterative decoding by the adaptive LDPC decoder. This algorithm may be repeated until the syndrome sum reaches zero or the adaptive LDPC decoder encounters the maximum allowed number of decoding iterations.

[0059] As another example, consider Figure 6 , which shows an example algorithm for adaptive LDPC decoding with a threshold based on the syndrome adjustment of an LDPC decoder at 600; although described with reference to a bit-flip decoder, aspects of algorithm 600 may also apply to other types of decoders, including symbol-flip decoders and the like. At 602, the adaptive LDPC decoder receives the bits to be decoded from the channel, and in some implementations, divides the graph or matrix of bits into bit blocks for processing during the decoding iteration. At 604, the adaptive LDPC decoder or adaptive controller determines whether the bit is equal to the received bit, or whether the bit has flipped from its original value at the time of reception (e.g., the bit flip state). At 606, the adaptive decoder determines at 608 the block index of the current bit being decoded and the current sum of the syndrome values. Alternatively or additionally, the adaptive decoder may determine the block index based on the corresponding bit positions of the bit nodes or variable nodes of the graph. At 610, the adaptive LDPC decoder may also determine the iteration index of the current iteration of decoding performed by the decoder, which if exceeded at 612 may indicate a failure to complete the decoding of the bits after a number of iterations. Otherwise, at 614, the adaptive LDPC decoder or adaptive controller reads or accesses the flip threshold for the current bit block at the current decoding iteration. Thus, the adaptive LDPC decoder may obtain the bit flip (or symbol flip) threshold based on the syndrome weight, bit flip state, and block index of the current subset of bits being decoded.

[0060] At 616, the adaptive LDPC decoder flips the bits of the current block of bits with the number of unsatisfied checks greater than a threshold, and then at 618 updates the metric of the decoder. Note that the metric of the decoder can change or be updated after each bit flip, and the decoder can track the metric update or metric weight on a per-bit flip basis, which can allow for dynamic adjustment of the decoding rule or threshold. At 620, the adaptive LDPC decoder sums the metric updates at the end of the decoding iteration, and if the metric sum is equal to zero, the adaptive LDPC decoder provides the decoded data as a decoding success at 618. Otherwise, the adaptive LDPC decoder feeds back the current iteration of the decoded bits including the flipped bits for another iterative decoding of the adaptive LDPC decoder. This algorithm can be repeated until the metric sum reaches zero or the adaptive LDPC decoder encounters the maximum allowed number of decoding iterations.

[0061] As an example, consider a decoding process that includes two iterations of decoding an LDPC code with aspects of adaptive decoding. In this example, assume that the adaptive LDPC decoder decodes an LDPC code of length N, and the bits of the LDPC code are partitioned into two types (type A (e.g., degree-3) and type B (e.g., degree-2)) that are divided into three blocks (M = 3). For this example, assume that type A bits are covered by the first block and type B bits are covered by the second and third blocks. When the adaptive LDPC decoder performs bit flip decoding, in iteration i of the decoding iteration, for each block in this decoding iteration, the adaptive LDPC decoder compares the number of unsatisfied check nodes (Uj) connected to variable node j with a threshold selected based on the current metric weight. In some implementations, the adaptive LDPC decoder selects the threshold from a threshold table stored in or accessible to the decoder based on the metric weight. In the context of the current example, in the first iteration (iteration index = 1), assume that the adaptive LDPC decoder decodes type A bits. Since type A bits are covered by one block (block 1), the adaptive LDPC decoder processes this one block by accessing the threshold associated with block index 1. As an example, consider Table 1, where the thresholds (t1 or t2) for block index 1 can be accessed based on the range of the metric weight and the bit flip state.

[0062]

[0063] Table 1: Bit Flip Thresholds for Block Index 1

[0064] When processing this bit node block, the adaptive LDPC decoder accesses and uses the bit flip threshold based on the current state or metric of the decoder. For example, if the metric weight of the decoder is between 175 and 200, the adaptive LDPC decoder uses the threshold pair (a 1,k-1 , b1,k-1 ) For the bit nodes of block 1, if the combined weight of the decoder is between 200 and 225, the adaptive LDPC decoder uses the threshold pair (a 1,k , b 1,k ) For the bit nodes of block 1, if the combined weight of the decoder is between 225 and 250, the adaptive LDPC decoder uses the threshold pair (a 1,k+1 , b 1,k+1 ) For the bit nodes of block 1 and so on. Based on the threshold entries selected from the table, the adaptive LDPC decoder performs bit flips using the thresholds, where if U j is greater than the selected threshold, the decoder flips the bit; otherwise, the decoder retains the bit value. In all aspects, this continues when the adaptive LDPC decoder updates the combined weight and dynamically selects or changes the thresholds.

[0065] After the first iteration is completed, the adaptive LDPC decoder advances to the second iteration (iteration index = 2). During the second iteration, the type B bits are decoded into the block 2 bits and block 3 bits of the LDPC code. Since the type B bits are covered by two different blocks, the adaptive LDPC decoder can access two different tables with different block indices, examples of which are illustrated as Table 2 for block index 2 and Table 3 for block index 3.

[0066]

[0067] Table 2: Bit - flip thresholds for block index 2

[0068] In the context of the second iteration and for block index 2, the adaptive LDPC decoder will access and use the bit - flip thresholds based on the current state or metric of the decoder. For example, if the combined weight of the decoder is between 175 and 200, the adaptive LDPC decoder uses the threshold pair (a 2,k-1 , b 2,k-1 ) for the bit nodes of block 2. If the combined weight of the decoder is between 200 and 225, the adaptive LDPC decoder uses the threshold pair (a 2,k , b 2,k ) for the bit nodes of block 2. If the combined weight of the decoder is between 225 and 250, the adaptive LDPC decoder uses the threshold pair (a 2,k+1 , b 2,k+1 ) for the bit nodes of block 2 and so on.

[0069]

[0070] Table 3: Bit - flip thresholds for block index 3

[0071] For bits of block index 3 that can be processed before, after, or in parallel with the bits of block index 2, the adaptive LDPC decoder accesses Table 3 and uses a bit flip threshold based on the current state or metric of the decoder. For example, if the combined weight of the decoder is between 175 and 200, the adaptive LDPC decoder uses the threshold pair (a 3,k-1 , b 3,k-1 ) for the bit nodes of block 3. If the combined weight of the decoder is between 200 and 225, the adaptive LDPC decoder uses the threshold pair (a 3,k , b 3,k ) for the bit nodes of block 3. If the combined weight of the decoder is between 225 and 250, the adaptive LDPC decoder uses the threshold pair (a 3,k+1 , b 3,k+1 ) for the bit nodes of block 3, and so on. Continuing with this example, and for each block of a given iteration, when the adaptive LDPC decoder implements the bit flip algorithm to decode the LDPC code, the adaptive LDPC decoder can use different tables based on the state and / or metric of the decoder. Thus, for iterations after the second iteration, the adaptive LDPC decoder proceeds in the same manner by accessing the threshold table corresponding to a particular iteration and the particular block (or blocks) being decoded during that iteration. As described herein, adaptive LDPC decoding can continue until the combined weight reaches zero or the adaptive LDPC decoder reaches the maximum iteration limit (K).

[0072] Techniques for Adaptive LDPC Decoding

[0073] The following discussion describes techniques for adaptive LDPC decoding that can enable an LDPC decoder to decode channel data with fewer decoding iterations or with a higher success rate, thereby improving LDPC decoding performance. These techniques can be implemented using any of the environments and entities described herein, such as the LDPC decoder 130 and the adaptive decoder controller 136. These techniques include Figures 7 to 10 the various methods shown. Each of the figures is shown as a set of operations that can be performed by one or more entities.

[0074] These methods need not be limited to the order of operations shown in the associated figures. Instead, any operation can be repeated, skipped, replaced, or reordered to achieve any aspect described herein. Additionally, these methods can be used in combination with each other, either in whole or in part, whether performed by the same entity, separate entities, or any combination thereof. For example, these methods can be combined to implement adaptive LDPC decoding, where the parameters of the LDPC decoder (e.g., the bit flip threshold) are adaptively set based on the decoder state to decode channel data with fewer decoding iterations or with a higher success rate, thereby improving LDPC decoding performance. In the following discussion sections, reference will be made by way of example to Figure 1 the operating environment 100 and Figures 2 to 6 the various entities or configurations of Figure 11 the system-on-chip and / or Figure 12 the storage system controller of

[0075] Figure 7 depicts an example method 700 for adaptive LDPC decoding according to various aspects, including operations performed by or in conjunction with an LDPC decoder 130, decoding parameters 132, decoding metrics 134, or an adaptive controller 136 associated with the adaptive LDPC decoder.

[0076] At 702, data is provided to the LDPC decoder, which can be configured as an adaptive LDPC decoder or include an adaptive controller. The data can be received from a channel such as a storage channel or a communication channel. For example, the data can be received from a storage channel via a storage medium interface or from a communication channel via a transceiver. Due to noise in the channel, one or more bits of the data (e.g., one or more bits of the data codeword) may be flipped or incorrect. Thus, the received data or the bits read from the data can include flipped bits or bit errors in the ECC encoding of the data. In various aspects, the adaptive LDPC decoder divides or allocates the data of a graph or matrix into multiple parts or subsets (e.g., blocks) for processing during the decoding iterations.

[0077] At 704, the LDPC decoder processes a first portion of data using a first parameter that effectively changes the state of the decoder. To process the first portion of data, the adaptive LDPC decoder flips bits or symbols of a first portion of bit nodes or variable nodes based on the first parameter. The first parameter can include a decoding rule or a decoding threshold by which to process bits of the first portion of data. The LDPC decoder can select the first parameter for decoding the first portion of data based on one or more metrics of the decoder, where the one or more metrics can include a combined weight, a bit flip status, a column weight, a block index, etc. The change in the state of the decoder can include an update to the combined weight of the decoder, which can change or be updated each time a bit or symbol of the LDPC code flips from a current value to a different value.

[0078] At 706, the LDPC decoder selects a second parameter of the LDPC decoder based on the state of the decoder. The second parameter can include a decoding rule or a decoding threshold by which to process bits of the first portion of data. The LDPC decoder can select the second parameter for decoding a second portion of data based on one or more metrics of the decoder, where the one or more metrics can include a combined weight, a bit flip status, a column weight, a bit position, a block index, etc. In various aspects, the adaptive LDPC decoder selects or updates a parameter or threshold for decoding a portion of bits at least once during a decoding iteration such that bits to be decoded are not decoded using only one bit flip threshold.

[0079] At 708, the LDPC decoder processes a second portion of data using the second parameter. To process the second portion of data, the adaptive LDPC decoder flips bits or symbols of a second portion of bit nodes or variable nodes based on the second parameter (e.g., a bit flip threshold). The second parameter can include a decoding rule or a decoding threshold by which to process bits of the second portion of data. Processing the second portion of data can also effectively change the state of the decoder, including another update to the combined weight of the decoder, which can change or be updated each time a bit or symbol of the LDPC code flips from a current value to a different value. From operation 708, method 700 can return to operation 706 to process another portion of data during the current iteration, or can proceed to operation 710 to determine whether bits of the data have been decoded. Operations 706 and 708 can be iteratively repeated until all portions of the data are processed to complete one decoding iteration.

[0080] At 710, a controller of the LDPC decoder determines whether the data has been decoded. In some cases, the LDPC decoder calculates a sum of syndromes updates to determine whether the decoder's syndrome weight has reached zero, indicating successful decoding of the data bits. If the syndrome weight of the LDPC decoder is not zero, method 700 can return to operation 702 to feed the partially decoded bits back to the decoder for another decoding iteration. Alternatively, the LDPC decoder can compare the iteration index with a maximum iteration threshold, and if the maximum iteration threshold is exceeded, the LDPC decoder can stop the decoding operation and provide the currently decoded bits as the output of the LDPC decoder at operation 712.

[0081] Figure 8 An example method 800 for implementing adaptive LDPC decoding based on the decoder's syndrome is depicted, including operations performed by or with an LDPC decoder 130, decoding parameters 132, decoding metrics 134, or an adaptive controller 136 associated with the adaptive LDPC decoder.

[0082] At 802, data is provided to the LDPC decoder, which can be configured as an adaptive LDPC decoder or include an adaptive controller. The data can be received from a channel such as a storage channel or a communication channel. Due to noise in the channel, one or more bits of the data (e.g., one or more bits of the data codeword) may be flipped or incorrect. Thus, the received data or the bits of the read data can include flipped bits or bit errors in the ECC encoding of the data. In various aspects, the adaptive LDPC decoder partitions or assigns the data of a graph or matrix into multiple bit blocks or bit subsets for processing during decoding iterations. For example, the adaptive LDPC decoder can divide the data into at least two portions of bits for decoding, and in some implementations, can divide the data into three portions, four portions, or any suitable number of portions (e.g., based on the received data quality (bit error rate) and / or decoder complexity).

[0083] At 804, the LDPC decoder processes a first data block using a first threshold setting to update the LDPC decoder's syndrome. To process the first block of data, the adaptive LDPC decoder flips the bits or symbols of a first block of bit nodes or variable nodes based on the first threshold setting, such as with reference Figure 5 or Figure 6Those described. The LDPC decoder can select a first threshold setting for decoding the first data block based on one or more metrics of the decoder, and the one or more metrics can include aggregate weight, bit flip status, column weight, bit position, block index, etc. The aggregate or aggregate weight of the decoder can change or be updated each time a bit or symbol of the LDPC code flips from its current value to a different value.

[0084] At 806, the adaptive controller of the LDPC decoder changes the first threshold setting based on the aggregate of the LDPC decoder to provide a second threshold setting. Additionally, the LDPC decoder can change the first threshold setting based on another metric of the decoder or the data being decoded, and the another metric can include the column weight of the parity check matrix, the bit position of the bit nodes or variable nodes, bit flip status, block index, etc. In various aspects, the adaptive LDPC decoder accesses a threshold table to select the second threshold setting, such as that referenced Figure 5 or Figure 6 described. Thus, the adaptive LDPC decoder can process or decode each of multiple portions of data bits using a corresponding set of decoding parameters dynamically selected based on the state of the LDPC decoder.

[0085] At 808, the LDPC decoder uses the second threshold setting to process the second data block to update the aggregate of the LDPC decoder. To process the second block of data, the adaptive LDPC decoder flips the bits or symbols of the second block of bit nodes or variable nodes based on the second threshold setting (e.g., bit flip threshold). Processing the bits of the second block of data updates the aggregate of the decoder, which can change or be updated each time a bit or symbol of the LDPC code flips from its current value to a different value. From operation 808, the LDPC decoder can return to operation 806 to change the current threshold setting of the LDPC decoder based on the updated aggregate resulting from processing the second data block or subsequent data blocks (e.g., on another block iteration), and process the next block of data. Operations 806 and 808 can be iteratively repeated until all blocks or bit types of the data are processed to complete one decoding iteration. Alternatively, the LDPC decoder can proceed to operation 810, where it determines whether the data is decoded based on the sum of the updated aggregate of the LDPC decoder.

[0086] At 810, the LDPC decoder determines whether the data is decoded based on the updated aggregate sum of the decoder. In some cases, the LDPC decoder determines whether the aggregate weight of the decoder reaches zero, indicating successful decoding of the data bits. If the aggregate weight of the LDPC decoder is not zero, method 800 may, at 812, return to operation 804 to feed the partially decoded bits back to the decoder for another decoding iteration. Alternatively, the LDPC decoder may compare the iteration index with a maximum iteration threshold, and if the maximum iteration threshold is exceeded, the LDPC decoder may stop the decoding operation. When the data is successfully decoded or the maximum number of iterations is reached, the LDPC decoder may provide the decoded bits as the output of the decoder at operation 814.

[0087] Figure 9A and Figure 9B Illustrated is an example method 900 for selecting decoding parameters of an adaptive LDPC decoder based on the state of the decoder, including operations performed by or with the LDPC decoder 130, the decoding parameters 132, the decoding metric 134, or the adaptive controller 136 associated with the adaptive LDPC decoder.

[0088] At 902, the LDPC decoder receives or is provided with the bits to be decoded. The data may be received from a channel such as a storage channel or a communication channel. Due to noise in the channel, one or more bits of the data (e.g., one or more bits of the data codeword) may be flipped or incorrect. In various aspects, the adaptive decoder may determine multiple portions or subsets of the data from the received data, and may then process the multiple portions or subsets of the data using decoding parameters (e.g., bits) adaptively selected or determined for each of the multiple portions or subsets of the data.

[0089] At 904, the state of the LDPC decoder is determined based on one or more metrics of the LDPC decoder. Generally, determining the state of the decoder may include determining the state information of the decoder and / or the metrics of the bit nodes or variable nodes of the data graph being decoded. As Figure 9A shown, the LDPC decoder may determine whether a bit is equal in value to the received bit (e.g., bit flip status) at 906, determine the block index of the LDPC decoder at 908, determine the sum of the aggregate value or vector of the LDPC decoder at 910, or determine the iteration index of the LDPC decoder at 912.

[0090] At 914, an adaptive controller of the LDPC decoder selects decoding parameters based on the state of the LDPC decoder; for example, based on the state and / or metrics of the decoder, the adaptive controller can access a table of bit flip threshold settings and select the bit flip threshold setting corresponding to the current state or states of the decoder, such as those described in reference Figure 5 or Figure 6 From operation 914, the method proceeds to operation 916, as shown at 901 of Figure 9B .

[0091] At 916, the LDPC decoder flips at least some bits based on the decoding parameters. Generally, the adaptive LDPC decoder flips the bits of the current block with a number of unsatisfied checks greater than the threshold, and then updates the syndrome of the decoder at 918. Note that the syndrome of the decoder can change or be updated after each bit flip, and the decoder can track the syndrome update or syndrome weight on a per-bit flip basis, which can allow for dynamic adjustment of the decoding rules or thresholds.

[0092] At 920, the sum of the syndromes is calculated. In various aspects, the adaptive LDPC decoder sums the syndrome updates at the end of the decoding iteration, and if the syndrome sum equals zero, the adaptive LDPC decoder provides the decoded data as a decoding success at 922. Otherwise, the adaptive LDPC decoder returns to operation 902, feeding back the current iteration of the decoded bits including the flipped bits for another iterative decoding by the adaptive LDPC decoder. The operations of method 900 can be repeated until the syndrome sum reaches zero or the adaptive LDPC decoder encounters the maximum allowed number of decoding iterations.

[0093] Figure 10 An example method 1000 for selecting parameters of an adaptive LDPC decoder based on the results of processing data with a combination of parameters is depicted, including operations performed by or with an LDPC decoder 130, decoding parameters 132, decoding metrics 134, or an adaptive controller 136 associated with the adaptive LDPC decoder. In various aspects, method 1000 can be implemented as an optimization of threshold setting based on "greedy search", where the cost function in the optimization can be configured to maximize the number of corrected bits per block of the decoded bit nodes. For example, method 1000 can be used to optimize the threshold table described in reference Figure 6 for any suitable number of iteration indices and / or block indices.

[0094] At 1002, data is loaded for the iteration index of the LDPC decoder. The data can be training data, randomized data, or real-time data of an LDPC code obtained from a channel. Optionally, at 1004, the current parameters of the LDPC decoder are accessed, which can include previously optimized parameters or parameters currently configured for the threshold settings of the decoder.

[0095] At 1006, data for the block index of the LDPC decoder is selected for decoding. In some embodiments, method 1000 is iteratively performed by advancing each block index from 1 to m - 1 for m blocks. At 1008, the parameters of the LDPC decoder are initialized for the currently selected data or the block index of the bit nodes. This can include setting a bit flip threshold for the data of the block index to be processed. At 1010, the data of the block index is processed using the LDPC decoder with the parameters, and the performance of the decoder can be monitored during the processing. In some cases, the data is processed by running a performance simulation using the currently optimized threshold, which is saved in a threshold table from all previous iterations from 1 to i - 1 and is used for blocks 1 to m - 1 in iteration i. At 1012, one or more of the decoding parameters are changed such that the performance simulation can evaluate multiple combinations of the decoding parameters or thresholds. In some cases, the performance simulation can be run simultaneously for all possible threshold combinations of the current block index m in the iteration i being evaluated or simulated.

[0096] At 1014, the results of processing the data of the block index with different parameters are compared, and at 1016, parameters are selected for the block index based on the comparison of the results. For example, after processing the results generated from the performance simulation, the best threshold that produces the largest number of corrected bits in the block can be selected. Starting from operation 1016, the method can proceed to the next block and process the next block with different combinations of parameters, such as until all blocks in the iteration are exhausted. After all blocks of the iteration have been processed, the method can proceed to operation 1018, where parameters (e.g., the best parameters or thresholds) are selected for the iteration index based on the processing results of each block or the thresholds selected for the block index based on the decoding results.

[0097] From operation 1018, after selecting parameters for an iteration index, the method may return to operation 1002 to load data for another iteration index for the LDPC decoder and iteratively process the data for that index on a block-by-block basis to determine parameters for another iteration index for the decoder. Thus, the operations of method 1000 may be iteratively performed to process multiple blocks for each iteration index, which may provide an optimal decoding threshold for multiple iteration indexes. After determining decoding parameters or thresholds for one or more iteration indexes of the LDPC decoder, method 1000 may proceed to operation 1020 to store the parameters into the LDPC decoder. In various aspects, the LDPC decoder or the adaptive controller stores the optimal decoding parameters or thresholds into a table based on the iteration number index, block index, and combined weight range, such as to provide tables similar to those described herein.

[0098] System-on-chip and controller

[0099] Figure 11 An example system-on-chip (SoC) 1100 environment is shown in which aspects of adaptive LDPC decoding may be implemented. The SoC 1100 may be implemented in any suitable system or device, such as a smart phone, netbook, tablet computer, access point, network-attached storage device, camera, smart appliance, printer, set-top box, server, data storage center, solid state drive (SSD), hard disk drive (HDD), optical storage drive, holographic storage system, storage drive array, memory module, automotive computing system, or aggregation storage controller, or any other suitable type of device (e.g., other devices described herein). Although described with reference to an SoC, Figure 11 entities may also be implemented as other types of integrated circuits or embedded systems, such as application specific integrated circuits (ASICs), memory controllers, storage controllers, communication controllers, application specific standard products (ASSPs), digital signal processors (DSPs), programmable SoCs (PSoCs), system-in-packages (SiPs), or field programmable gate arrays (FPGAs).

[0100] The SoC 1100 can be integrated with electronic circuits, microprocessors, memories, input / output (I / O) control logic, communication interfaces, firmware, and / or software for providing the functionality of a computing device, a host system, or a storage system (such as any device or component herein (e.g., a storage drive or a storage array)). The SoC 1100 can also include an integrated data bus or an interconnect structure (not shown) that couples the various components of the SoC for control signals, data communication, and / or routing between the components. The integrated data bus, interconnect structure, or other components of the SoC 1100 can be exposed or accessed through an external port, a parallel data interface, a serial data interface, a fabric-based interface, a peripheral component interface, or any other suitable data interface. For example, the components of the SoC 1100 can access or control an external storage medium, a processing block, a neural network, a dataset, or an AI model through an external interface or an off-chip data interface.

[0101] In this example, the SoC 1100 includes various components, such as input / output (I / O) control logic 1102 and a hardware-based processor 1104 (processor 1104), such as a microprocessor, a processor core, an application processor, a DSP, etc. The SoC 1100 also includes a memory 1106, which can include any type and / or combination of RAM, SRAM, DRAM, non-volatile memory, ROM, one-time programmable (OTP) memory, multiple-time programmable (MTP) memory, flash memory, and / or other suitable electronic data storage devices. In some aspects, the processor 1104 and the code stored in the memory 1106 are implemented as a storage system controller or a storage aggregator to provide various functions associated with adaptive LDPC decoding. In the context of the present disclosure, the memory 1106 stores data, code, instructions, or other information via a non-transitory signal and does not include a carrier wave or a transient signal. Alternatively or additionally, the SoC 1100 can include a data interface (not shown) for accessing additional or expandable off-chip storage media, such as solid-state memory (e.g., flash memory or NAND memory), magnetic-based storage media, or optical-based storage media.

[0102] SoC 1100 may also include firmware 1108, applications, programs, software, and / or an operating system, which may be embodied as processor-executable instructions maintained on memory 1106 for execution by processor 1104 to implement the functions of SoC 1100. SoC 1100 may also include other communication interfaces, such as components for controlling or communicating with a local on-chip (not shown) or off-chip communication transceiver. Thus, in some aspects, SoC 1100 may be implemented or configured to be a communication transceiver capable of implementing aspects of adaptive LDPC decoding to process data received over a communication channel. Alternatively or additionally, the transceiver interface may also include or implement a signal interface to transmit radio frequency (RF), intermediate frequency (IF), or baseband frequency signals outside the chip to facilitate wired or wireless communication through a transceiver, physical layer transceiver (PHY), or media access controller (MAC) coupled to SoC 1100. For example, SoC 1100 may include a transceiver interface configured to enable storage over a wired or wireless network, such as providing adaptive LDPC decoding for data transmitted and / or stored for a network-attached storage (NAS) volume.

[0103] SoC 1100 also includes an LDPC decoder 130, a processing block 214, and an adaptive controller 136, which may be implemented separately as shown or in combination with storage components, host controllers, data interfaces, data transceivers. In accordance with aspects of adaptive LDPC decoding, the LDPC decoder 130 and the adaptive controller 136 use a first parameter that effectively changes the state (e.g., synthesis weights) of the decoder to process a first portion (e.g., a block of data) of the channel data and select a second parameter based on the state of the decoder. The LDPC decoder 130 is then configured with the second parameter and processes a second portion (e.g., another data block) of the data using the second parameter, which may also update the state of the LDPC decoder 130. The LDPC decoder 130 provides decoded data for the channel based at least on the processing of the first portion of the data using the first parameter and the processing of the second portion of the data using the second parameter. Any of these entities may be embodied as separate or combined components, as described with reference to the various aspects presented herein. For example, the adaptive controller may be implemented as part of the LDPC decoder 130 or the processing block 214 of a storage controller or a communication transceiver. Refer to Figure 1 the corresponding components or entities of environment 100 or Figures 2 to 6 the corresponding configurations and / or as shown in Figures 7 to 10Examples of these components and / or entities or corresponding functions are described by methods 700 to 1000. The LDPC decoder 130 or the adaptive controller 136 may be implemented in whole or in part as processor-executable instructions maintained by the memory 1106 and executed by the processor 1104 to implement various aspects and / or features of adaptive LDPC decoding.

[0104] The adaptive LDPC decoder 130 and / or the processing block 214 may be implemented independently or in combination with any suitable components or circuits to implement the aspects described herein. For example, the adaptive LDPC decoder 130 or the processing block 214 may be implemented as part of a DSP, a processor / memory bridge, an I / O bridge, a graphics processing unit, a memory controller, a storage controller, an arithmetic logic unit (ALU), etc. The adaptive LDPC decoder 130 may also be provided integrally with other entities of the SoC 1100, such as integrated with the processor 1104, the memory 1106, the storage media interface, or the firmware 1108 of the SoC 1100. Alternatively or additionally, the adaptive LDPC decoder 130, the processing block 214, and / or other components of the SoC 1100 may be implemented as hardware, firmware, fixed logic circuitry, or any combination thereof.

[0105] As another example, consider Figure 12 , which shows an example storage system controller 1200 according to one or more aspects of adaptive LDPC decoding. In various aspects, the storage system controller 1200 or any combination of its components may be implemented as a storage drive controller, a distributed storage center controller (e.g., between a host and an SSD), a storage media controller, a NAS controller, a fabric interface, an NVMe target, or a storage integration controller for storage media. In some cases, the storage system controller 1200 is implemented similarly to or utilizes components of the SoC 1100 as described in reference to Figure 11 . In other words, an instance of the SoC 1100 may be configured as a storage system controller, such as the storage system controller 1200, to manage storage media (e.g., NAND flash-based or magnetic media) using aspects of adaptive LDPC decoding.

[0106] As Figure 12As shown, the storage system controller 1200 includes input / output (I / O) control logic 1202 and a processor 1204, such as a microprocessor, a processor core, an application processor, a DSP, etc. In some aspects, the processor 1204 and the firmware of the storage system controller 1200 can be implemented to provide various functions associated with adaptive LDPC decoding, such as those described with reference to any of methods 700 to 1000. The storage system controller 1200 also includes a host interface 1206 (e.g., SATA, PCIe, NVMe, or a fabric interface) and a storage medium interface 1208 (e.g., a NAND interface, a read / write channel), which enable access to the host system and the storage medium, respectively. The storage system controller 1200 may also include a flash translation layer 1210 (FTL 1210), SRAM (not shown), and / or a DRAM controller (not shown). In some aspects of adaptive LDPC decoding, the FTL 1210 interacts with the LDPC decoder 130 and / or the adaptive controller 136 to decode data read from a storage medium operably coupled to the storage medium interface 1208.

[0107] In this example, the storage controller 1200 also includes an instance of a processing block 214, an LDPC decoder 130, decoding parameters 132, decoding metrics 134, and an adaptive controller 136. Any or all of these components may be implemented separately as shown, or in combination with the processor 1204, the host interface 1206, the storage medium interface 1208, the flash translation layer 1210, and / or as an adaptive LDPC decoder of the storage system controller 1200. Refer to Figure 1 the corresponding components or entities of the environment 100 or Figures 2 to 6 the corresponding configurations shown in to describe examples of these components and / or entities or corresponding functions. According to various aspects of adaptive LDPC decoding, the LDPC decoder 130 and the adaptive controller 136 use a first parameter that effectively changes the state of the decoder (e.g., the synthesis weights) to process a first portion (e.g., a block of data) of the data of the channel, and select a second parameter based on the state of the decoder. The LDPC decoder 130 is then configured with the second parameter and processes a second portion (e.g., another data block) of the data using the second parameter, which may also update the state of the LDPC decoder. The LDPC decoder 130 provides decoded data of the channel based at least on the processing of the first portion of the data using the first parameter and the processing of the second portion of the data using the second parameter. By adaptively selecting or changing decoding parameters (e.g., bit flip or symbol flip thresholds) based on the decoder state, the adaptive LDPC decoder 130 can decode channel data with fewer decoding iterations or with a higher success rate, improving LDPC decoding performance.

[0108] In the following, some examples of adaptive LDPC decoding are described according to one or more aspects:

[0109] Example 1: A method for adaptive low-density parity-check decoding, comprising: using a first parameter that effectively changes the state of an LDPC decoder, processing a first portion of data of a channel by means of a low-density parity-check (LDPC) decoder; selecting a second parameter of the LDPC decoder based on the state of the LDPC decoder; processing a second portion of the data by means of the LDPC decoder using the second parameter; and providing decoded data of the channel based at least on the processing of the first portion of the data using the first parameter and the processing of the second portion of the data using the second parameter.

[0110] Example 2: The method according to any example, further comprising: receiving data from the channel and providing the data of the channel to the LDPC decoder.

[0111] Example 3: The method according to any example, wherein receiving data of the channel comprises: receiving data from a storage channel via a storage medium interface; or receiving data from a communication channel via a transceiver.

[0112] Example 4: The method according to any example, further comprising: after at least a portion of processing the second portion of the data, selecting a third parameter of the LDPC decoder based on the state of the LDPC decoder; processing a third portion of the data by means of the LDPC decoder using the third parameter; and providing decoded data of the channel based at least on the processing of the first portion of the data using the first parameter, the processing of the second portion of the data using the second parameter, and the processing of the third portion of the data using the third parameter.

[0113] Example 5: The method according to any example, wherein the state of the LDPC decoder comprises one of the following: the overall weight of the LDPC decoder; the column weight of the parity-check matrix; the bit position of the bits of the data; the LDPC code implemented by the LDPC decoder to decode the data; the degree of one or more bits of the data; the block index of the LDPC decoder; or the iteration index of the LDPC decoder.

[0114] Example 6: The method according to any example, wherein the first parameter or the second parameter comprises one of the following: an LDPC decoding rule; the value of an LDPC decision threshold; a bit flip threshold for bits that have been flipped; a bit flip threshold for bits that have not been flipped; a symbol flip threshold for symbols that have been flipped; or a symbol flip threshold for symbols that have not been flipped.

[0115] Example 7: The method according to any example, wherein: processing the first portion of the data using an LDPC decoder includes flipping the bit value of a variable node representing a corresponding bit in the first portion of the data; or processing the second portion of the data using an LDPC decoder includes flipping the bit value of a variable node representing a corresponding bit in the second portion of the data.

[0116] Example 8: The method according to any example, wherein: the first portion of the data corresponds to the first block of the data; the second portion of the data corresponds to the second block of the data; and the method further includes determining from the data a plurality of data blocks including at least the first data block and the second data block, wherein the state of the decoder based on which the second parameter is selected includes an index of the second block of the data.

[0117] Example 9: The method according to any example, wherein: each data block of the plurality of data blocks includes a bit node type corresponding to the degree of a bit node in the parity check matrix of the LDPC decoder; and determining the plurality of blocks includes forming each block of the plurality of blocks with bit node types of data from at least two types of bit nodes defined for the LDPC decoder.

[0118] Example 10: The method according to any example, wherein: the first portion of the data and the second portion of the data are processed during a single iteration of the LDPC decoder; and the state of the LDPC decoder includes an intermediate state of the LDPC decoder obtained during a single iteration of processing the data of the channel.

[0119] Example 11: The method according to any example, wherein: the data includes data read from a storage medium; and the storage medium includes one of the following: an optical storage medium, a magnetic storage medium, a holographic storage medium, a solid-state storage medium, a NAND flash memory, a single-level cell (SLC) flash memory, a multi-level cell (MLC) flash memory, a three-level cell (TLC) flash memory, a four-level cell flash memory (QLC), or a NOR cell flash memory.

[0120] Example 12: An apparatus, comprising: a data interface configured to communicate data over a channel; a low-density parity-check (LDPC) decoder; and an adaptive controller for the LDPC decoder, the adaptive controller being configured to implement any method of the examples.

[0121] Example 13: A system-on-chip (SoC), comprising: a media interface for accessing a storage medium of a storage medium system; a host interface for communicating with a host system; a low-density parity-check (LDPC) decoder; and an adaptive controller for the LDPC decoder, configured to implement any method of the examples.

[0122] Although the subject matter of the adaptive LDPC decoder has been described in language specific to structural features and / or method operations, it should be understood that the subject matter defined in the appended claims need not be limited to the specific examples, features, or operations described herein, including the order in which they are performed.

Claims

1. A method for adaptive low-density parity-check decoding, comprising: Process (704) a first portion of data of a channel having the LDPC decoder using a first parameter that effectively changes a state of the low density parity check (LDPC) decoder; Select (706) a second parameter of the LDPC decoder based on the state of the LDPC decoder; Process (708) a second portion of the data using the second parameter with the LDPC decoder; And Provide (712) decoded data of the channel based at least on processing of the first portion of the data using the first parameter and processing of the second portion of the data using the second parameter.

2. The method according to claim 1, further comprising: Receive the data from the channel and provide the data of the channel to the LDPC decoder.

3. The method according to claim 1 or 2, wherein receiving the data from the channel comprises: Receive the data from a storage channel via a storage medium interface; Or Receive the data from a communication channel via a transceiver.

4. The method according to any one of claims 1 to 3, wherein the state of the LDPC decoder comprises one of the following items: The combined weight of the LDPC decoder; The column weight of the parity-check matrix; The bit position of the bits of the data; An LDPC code implemented by the LDPC decoder to decode the data; A degree of one or more bits of the data; A block index of the LDPC decoder; or An iteration index of the LDPC decoder.

5. The method according to any one of claims 1 to 4, wherein the first parameter or the second parameter comprises one of the following items: LDPC decoding rules; A value of an LDPC decision threshold; A bit flip threshold for bits that have been flipped; A bit flip threshold for bits that have not been flipped; A symbol flip threshold for symbols that have been flipped; or A symbol flip threshold for symbols that have not been flipped.

6. The method according to any one of claims 1 to 5, wherein: The processing of the first portion of the data using the LDPC decoder includes: flipping a bit value of a variable node representing a corresponding bit in the first portion of the data; or The processing of the second portion of the data using the LDPC decoder includes: flipping a bit value of a variable node representing a corresponding bit in the second portion of the data.

7. The method according to claim 6, wherein: The first portion of the data corresponds to a first block of the data; The second portion of the data corresponds to a second block of the data; And The method further includes: determining a plurality of blocks of the data from the data, the plurality of blocks of the data including at least the first block of the data and the second block of the data, Wherein the state of the decoder based on which the second parameter is selected includes an index of the second block of the data.

8. The method according to claim 7, wherein: Each block of the plurality of blocks of the data includes a type of bit node corresponding to a degree of a bit node in a parity check matrix of the LDPC decoder; And The determining of the plurality of blocks includes: forming each block of the plurality of blocks using one type of bit node of the data from at least two types of bit nodes defined for the LDPC decoder.

9. The method according to any one of claims 1 to 8, wherein: The first portion of the data and the second portion of the data are processed during a single iteration of the LDPC decoder; and The state of the LDPC decoder includes an intermediate state of the LDPC decoder obtained during the single iteration of the processing of the data of the channel.

10. An apparatus, comprising: A data interface (142), configured for communication of data of a channel; A low density parity check (LDPC) decoder (130); And An adaptive controller (136) for the LDPC decoder, the adaptive controller being configured to: Process (704) a first block of data received from the channel using the LDPC decoder and a first parameter to effectively change a metric of the LDPC decoder; Select (706) a second parameter for the LDPC decoder based on the metric of the LDPC decoder; Process (708) a second block of the data using the LDPC decoder and the second parameter; And Provide (712) decoded data of the channel based at least on the processing of the first block using the first parameter and the processing of the second block using the second parameter.

11. The apparatus according to claim 10, wherein: The data interface includes a storage medium interface, and the apparatus is further configured to read the data from a storage medium operably coupled to the apparatus via the storage medium interface; or The data interface includes a data transceiver, and the apparatus is further configured to receive the data from a transmitter via the data transceiver over the channel.

12. The apparatus according to claim 10 or 11, wherein: The metric of the LDPC decoder is an intermediate metric of an iteration of decoding the data from the channel; and The metric of the LDPC decoder includes one or more of the following: The combined weight of the LDPC decoder; The column weight of the parity check matrix; The bit position of a bit of the data; The LDPC code implemented by the LDPC decoder for decoding the data; The degree of one or more bits of the data; The block index of the LDPC decoder; or The iteration index of the LDPC decoder.

13. The apparatus according to claim 12, wherein the first parameter or the second parameter of the LDPC decoder comprises one of the following items: LDPC decoding rules; The value of the LDPC decision threshold; A bit flip threshold for a flipped bit; A bit flip threshold for an unflipped bit; A symbol flip threshold for a flipped symbol; or A symbol flip threshold for an unflipped symbol.

14. The apparatus according to claim 13, wherein: The adaptive controller is further configured to: determine a plurality of blocks of the data from the data, the plurality of blocks of the data including at least the first block of the data and the second block of the data; And wherein the metric of the decoder based on which the second parameter is selected includes an index of the second block of the data.

15. The apparatus according to claim 14, wherein: Each block of the plurality of blocks of the data includes a type of bit node corresponding to the degree of a bit node in a parity check matrix of the LDPC decoder; And To determine the plurality of blocks, the adaptive controller is configured to: form each block of the plurality of blocks using one type of bit node of the data from at least two types of bit nodes defined for the LDPC decoder.

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