Power loop dynamic VI calibration method, system and device and storage medium

Abstract

The embodiment of the invention provides a power loop dynamic VI calibration method, system and device and a storage medium, and the method comprises the steps: carrying out the real-time detection of a half-bridge circuit, obtaining a detection value, and obtaining first detection time and second detection time through combining with a second preset condition and a third preset condition; the switching state is identified by comparing the first detection time and the second detection time, and dynamic voltage-current (VI) calibration is achieved with a first time offset by capturing a first turn-off transient waveform and a second turn-off transient waveform and calculating the first time offset in a fast switching transient. According to the embodiment of the invention, by accurately analyzing the relation between the current and the voltage in the switching transient process, the measurement error caused by high-frequency noise and time deviation in the traditional voltage-current (VI) calibration is effectively avoided.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of power electronics technology, and particularly to a power loop dynamic VI calibration method, system, device and storage medium. Background Art

[0002] With the wide application of wide bandgap semiconductor materials such as GaN and SiC in the field of power electronics, the switching performance of power devices plays a crucial role in the efficiency, stability and reliability of power systems. Especially in high-speed switching applications, wide bandgap power devices have advantages such as high switching frequency, high efficiency and low switching losses.

[0003] During high-speed switching, voltage, current and the rate of change of current (di / dt) change rapidly. Currently, common voltage-current (VI) calibrations, such as the automatic calibration of oscilloscopes, square wave signal source calibration, post-processing calibration, calibration based on fixed-value resistors, etc., although they solve the calibration problem to a certain extent, all have limitations. Especially when facing high-speed switching and complex circuits, it is difficult to effectively handle problems such as measurement delay, waveform mismatch and parasitic inductance. The automatic calibration function of the oscilloscope is applicable to voltage probes, but it cannot effectively solve the delay in current measurement. The square wave signal source calibration can align waveforms, but its adaptability to complex circuits is poor, and it can only perform simple compensation for delay. The post-processing calibration can align according to the known voltage-current relationship, but it requires accurate voltage waveforms and is easily affected by parasitic inductance, resulting in measurement errors. The calibration based on fixed-value resistors can eliminate the influence of parasitic inductance, but it is not applicable to complex transient waveforms and still faces problems of accuracy and noise interference.

[0004] Traditional voltage-current (VI) calibration methods face many challenges. Especially when dealing with wide bandgap semiconductor (such as GaN and SiC) power devices, under the influence of high-frequency noise interference and time deviation, measurement errors are inevitable and it is impossible to effectively adapt to the challenges brought by high-speed switching. During high-speed switching, the changes in current and voltage are very rapid. Especially in the transient stage of switching devices, the changes in voltage, current and the rate of change of current (di / dt) are extremely violent. Conventional steady-state calibration methods cannot capture these transient characteristics, resulting in an increase in the error of calibration results. Especially for GaN HEMT (High Electron Mobility Transistors) devices, the rise time of voltage and current during high-speed switching is only a few nanoseconds, and the delay and waveform mismatch of traditional calibration methods lead to a significant reduction in measurement accuracy. Summary of the Invention

[0005] To this end, an embodiment of the present invention provides a power loop dynamic VI calibration method, system, device, and storage medium to solve the technical problem that traditional voltage-current (VI) calibration is often affected by high-frequency noise interference and time deviation when dealing with high-speed switches, resulting in inaccurate measurement results.

[0006] To achieve the above object, the embodiments of the present invention provide the following technical solutions:

[0007] According to the first aspect of the embodiments of the present invention, an embodiment of the present application provides a power loop dynamic VI calibration method, the method includes:

[0008] Perform real-time detection on the half-bridge circuit according to a first preset condition to obtain a first detection value, a second detection value, a third detection value, and a fourth detection value;

[0009] Judge whether the first detection value meets a second preset condition;

[0010] If the first detection value meets the second preset condition, obtain the corresponding first detection time t 11 , and judge whether the second detection value meets a third preset condition;

[0011] If the second detection value meets the third preset condition, obtain the corresponding second detection time t 12 ;

[0012] Judge whether the first detection time t 11 is less than or equal to the second detection time t 12 ;

[0013] If the first detection time t 11 is greater than the second detection time t 12 , then based on a fourth preset condition, respectively capture a first turn-off transient waveform and a second turn-off transient waveform corresponding to the third detection value and the fourth detection value;

[0014] Based on the first turn-off transient waveform, obtain a third detection time t 13 when the third detection value drops to 0;

[0015] Based on the second turn-off transient waveform, obtain a fourth detection time t r when the fourth detection value drops to the reverse conduction voltage V 14 ;

[0016] Calculate the difference between the third detection time t 13 minus the fourth detection time t 14 to obtain a first time offset Δt1;

[0017] Adjust the first turn-off transient waveform by using the first time offset Δt1, so that the third detection time t of the first turn-off transient waveform 13 is aligned with the fourth detection time t of the second turn-off transient waveform 14 , and continue to perform real-time detection on the half-bridge circuit according to the first preset condition.

[0018] Further, the first detection value, the second detection value, the third detection value, and the fourth detection value are respectively the gate-source voltage V of the active transistor SW2 in the half-bridge circuit gs , drain-source voltage V ds and drain current i d , and the drain-source voltage V of the passive transistor SW1 in the half-bridge circuit ds1 .

[0019] Further, a power loop dynamic VI calibration method provided by an embodiment of the present application further includes:

[0020] Based on the fifth preset condition, respectively capture the first turn-on transient waveform and the second turn-on transient waveform corresponding to the third detection value and the fourth detection value;

[0021] Based on the first turn-on transient waveform, obtain the fifth detection time t corresponding to the third detection value rising to the load inductor current I L ; 15 ;

[0022] Based on the second turn-on transient waveform, obtain the sixth detection time t corresponding to the fourth detection value starting to transition and rise from the reverse conduction voltage V r ; 16 ;

[0023] Calculate the difference between the fifth detection time t 15 minus the sixth detection time t 16 to obtain the second time offset Δt2;

[0024] Adjust the first turn-on transient waveform by using the second time offset Δt2, so that the third detection time t of the first turn-on transient waveform 15 is aligned with the fourth detection time t of the second turn-on transient waveform 16 , and continue to perform real-time detection on the half-bridge circuit according to the first preset condition.

[0025] Further, a power loop dynamic VI calibration method provided by an embodiment of the present application further includes:

[0026] If the first detection time t 11 is less than or equal to the second detection time t 12, then the drain current i is obtained based on each third detection value d The change rate di d / dt, as the fifth detection value;

[0027] During the turn-off process of the active transistor SW2, monitor the changes of the second detection value and the fifth detection value with the real-time detection time t, and respectively obtain the first waveform and the second waveform;

[0028] Based on the first waveform, obtain the seventh detection time t dsmax corresponding to when the second detection value reaches the first maximum value V 17 ;

[0029] Based on the second waveform, obtain the absolute value of the fifth detection value reaching the second maximum value corresponding to the eighth detection time t 18 ;

[0030] Calculate the difference between the eighth detection time t 18 minus the seventh detection time t 17 to obtain the third time offset Δt3;

[0031] Use the third time offset Δt3 to adjust the second waveform so that the eighth detection time t of the second waveform 18 is aligned with the seventh detection time t of the first waveform 17 , and continue to perform real-time detection on the half-bridge circuit according to the first preset condition.

[0032] Further, the first preset condition includes:

[0033] Set the first gate drive voltage V g1 of the passive transistor SW1 to zero;

[0034] Apply a double-pulse signal voltage to the gate-source of the active transistor SW2 using the second gate drive voltage V g ; and

[0035] Apply a DC bus voltage V DC to the bus terminal of the half-bridge circuit.

[0036] Further, a power loop dynamic VI calibration method provided by an embodiment of the present application further includes: if the first detection value does not meet the second preset condition, or the second detection value does not meet the third preset condition, then continue to perform real-time detection on the half-bridge circuit according to the first preset condition.

[0037] Further, the second preset condition is:

[0038]

[0039] Among them, I L is the load inductor current, and g m is the transconductance of the active transistor SW2, and V th is the threshold voltage of the active transistor SW2;

[0040] The third preset condition is:

[0041] V ds = V gs - V th

[0042] Among them, V th is the threshold voltage of the active transistor SW2;

[0043] The fourth preset condition is: the dual-pulse signal voltage reaches the falling edge of the first pulse; and

[0044] The fifth preset condition is: the dual-pulse signal voltage reaches the rising edge of the second pulse.

[0045] According to the second aspect of the embodiments of the present invention, an embodiment of the present application provides a power loop dynamic VI calibration system, and the system includes:

[0046] A detection module, configured to perform real-time detection on the half-bridge circuit according to the first preset condition, and obtain a first detection value, a second detection value, a third detection value, and a fourth detection value;

[0047] An identification module, configured to perform the following steps:

[0048] Judge whether the first detection value meets the second preset condition;

[0049] If the first detection value meets the second preset condition, obtain the corresponding first detection time t 11 , and judge whether the second detection value meets the third preset condition;

[0050] If the second detection value meets the third preset condition, obtain the corresponding second detection time t 12 ;

[0051] Judge whether the first detection time t 11 is less than or equal to the second detection time t 12 ; and

[0052] A calibration module, configured to perform the following steps:

[0053] If the first detection time t 11 is greater than the second detection time t 12, then based on the fourth preset condition, the first turn-off transient waveform and the second turn-off transient waveform corresponding to the third detection value and the fourth detection value are respectively captured;

[0054] Based on the first turn-off transient waveform, obtain the third detection time t when the third detection value drops to 0 13 ;

[0055] Based on the second turn-off transient waveform, obtain the fourth detection time t when the fourth detection value drops to the reverse conduction voltage V r corresponding to 14 ;

[0056] Calculate the difference between the third detection time t 13 subtracted by the fourth detection time t 14 to obtain the first time offset Δt1;

[0057] Use the first time offset Δt1 to adjust the first turn-off transient waveform so that the third detection time t of the first turn-off transient waveform 13 is aligned with the fourth detection time t of the second turn-off transient waveform 14 , and continue to perform real-time detection on the half-bridge circuit by the detection module according to the first preset condition.

[0058] According to the third aspect of the embodiments of the present invention, a power loop dynamic VI calibration device is provided, and the device includes: a processor and a memory;

[0059] The memory is used to store one or more program instructions;

[0060] The processor is used to run one or more program instructions to execute the steps of a power loop dynamic VI calibration method as described in any one of the above.

[0061] According to the fourth aspect of the embodiments of the present invention, a computer-readable storage medium is provided, and a computer program is stored on the computer-readable storage medium. When the computer program is executed by a processor, the steps of a power loop dynamic VI calibration method as described in any one of the above are implemented.

[0062] Compared with the prior art, a power loop dynamic VI calibration method, system, device and storage medium provided by an embodiment of the present application obtain detection values by performing real-time detection on a half-bridge circuit, and obtain a first detection time and a second detection time in combination with a second preset condition and a third preset condition. The switch state is identified by comparing the first detection time and the second detection time. When a fast switch transient occurs, a first turn-off transient waveform and a second turn-off transient waveform are captured and a first time offset is calculated, and the first time offset is used to achieve dynamic voltage-current (VI) calibration. The embodiment of the present invention effectively avoids measurement errors caused by high-frequency noise and time deviation in traditional voltage-current (VI) calibration by accurately analyzing the relationship between current and voltage during the switch transient process. Description of the Drawings

[0063] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only exemplary, and for those of ordinary skill in the art, without creative efforts, other implementation drawings can be obtained according to the provided drawings.

[0064] The structures, ratios, sizes, etc. illustrated in this specification are only used to cooperate with the content disclosed in the specification for those who are familiar with this technology to understand and read, and are not used to limit the limited conditions under which the present invention can be implemented. Therefore, they do not have technical substantive significance. Any modification of the structure, change of the proportional relationship or adjustment of the size should still fall within the scope that can be covered by the technical content disclosed in the present invention without affecting the effects that the present invention can produce and the purposes that can be achieved.

[0065] Figure 1 It is a topological structure diagram of a GaN HEMT dual-pulse test half-bridge circuit considering parasitic parameters provided by an embodiment of the present invention;

[0066] Figure 2 It is a schematic logical structure diagram of a power loop dynamic VI calibration system provided by an embodiment of the present invention;

[0067] Figure 3 It is a schematic flow diagram of a power loop dynamic VI calibration method in a fast switch transient state provided by an embodiment of the present invention;

[0068] Figure 4 It is a schematic flow diagram of a power loop dynamic VI calibration method in a normal working state provided by an embodiment of the present invention;

[0069] Figure 5aSchematic diagram of the principle for capturing the first turn-off transient waveform, the second turn-off transient waveform, the first turn-on transient waveform, and the second turn-on transient waveform provided by the embodiments of the present invention;

[0070] Figure 5b Drain-source voltage V of the active transistor SW2 under switch transient provided by an embodiment of the present invention ds Waveform diagram, drain current i d Waveform diagram, and drain-source voltage V of the passive transistor SW1 ds1 Waveform diagram;

[0071] Figure 6a Drain current i of the active transistor SW2 before and after VI calibration during the turn-on process in the fast switch transient state provided by an embodiment of the present invention d Waveform diagram, and drain-source voltage V of the passive transistor SW1 ds1 Waveform diagram;

[0072] Figure 6b Drain current i of the active transistor SW2 before and after VI calibration during the turn-off process in the fast switch transient state provided by an embodiment of the present invention d Waveform diagram, and drain-source voltage V of the passive transistor SW1 ds1 Waveform diagram;

[0073] Figure 7 Rate of change di of the drain current i of the active transistor SW2 before and after calibration in the normal working state provided by an embodiment of the present invention d / dt waveform diagram, and drain-source voltage V d Waveform diagram; ds Waveform diagram;

[0074] Figure 8a Schematic diagram of the double-pulse test results in a simulation condition during the turn-on process in the fast switch transient state for a power loop dynamic VI calibration method provided by the embodiments of the present invention;

[0075] Figure 8b Schematic diagram of the double-pulse test results in a simulation condition during the turn-off process in the fast switch transient state for a power loop dynamic VI calibration method provided by the embodiments of the present invention;

[0076] Figure 9a Schematic diagram of the double-pulse test results in another simulation condition during the turn-on process in the fast switch transient state for a power loop dynamic VI calibration method provided by the embodiments of the present invention;

[0077] Figure 9b Schematic diagram of the double-pulse test results in another simulation condition during the turn-off process in the fast switch transient state for a power loop dynamic VI calibration method provided by the embodiments of the present invention;

[0078] Figure 10 Schematic diagram of double-pulse test results under a simulation condition in the normal operating state of a power loop dynamic VI calibration method provided by an embodiment of the present invention;

[0079] Figure 11 Schematic diagram of double-pulse test results under another simulation condition in the normal operating state of a power loop dynamic VI calibration method provided by an embodiment of the present invention. Detailed implementation manners

[0080] The following specific embodiments illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0081] The purpose in the embodiments of the present invention is to: by analyzing the current and voltage characteristics of the active transistor and the passive transistor, and combining the key electrical characteristic points during the switching process, realize dynamic voltage-current (VI) calibration of the power loop, be able to adapt to the calibration requirements of different switching speeds at the same time, ensure efficient and accurate calibration under both normal and high-speed switching conditions, and significantly improve the accuracy of power device performance testing.

[0082] To solve the above technical problems, an embodiment of the present application provides a power loop dynamic VI calibration system, which is applied to a half-bridge circuit including parasitic parameters.

[0083] As Figure 1 shown, in the embodiment of the present application, all key high-frequency components are considered, and it is particularly applicable to the GaN HEMT half-bridge test equivalent circuit with parasitic parameters. The half-bridge circuit is formed by the passive transistor SW1 and the active transistor SW2. The embodiments of the present invention are applicable to wide-bandgap semiconductor devices such as GaN and SiC, such as GaN HEMT (High Electron Mobility Transistors), SiC MOSFET, etc. The passive transistor SW1 and the active transistor SW2 are wide-bandgap semiconductor power devices.

[0084] Taking the double-pulse test circuit as an example, the embodiment of the present application analyzes the high-speed switching transient behavior mechanism of the GaN HEMT power device, and then proposes the construction idea of the analysis model. This modeling method can also be applied to other half-bridge-based circuits, such as synchronous buck converters. Figure 1 The circuit parameters used in DC are defined as follows: VDC : Decoupling capacitor, I L : Load inductor current, L loop : Loop parasitic inductance, R loop : Total resistance of the double-pulse circuit power loop, C ds1 , C ds : Drain-source parasitic capacitance of the passive transistor SW1 and the active transistor SW2, C gd1 , C gd : Gate-drain parasitic capacitance of the passive transistor SW1 and the active transistor SW2, C gs1 , C gs : Gate-source parasitic capacitance of the passive transistor SW1 and the active transistor SW2, R g1_ext , R g_ext : Equivalent resistance of the drive loop of the passive transistor SW1 and the active transistor SW2, R g1_int , R g_int : Equivalent resistance inside the devices of the passive transistor SW1 and the active transistor SW2, L g1—ext , L g_ext : Equivalent inductance of the drive loop of the passive transistor SW1 and the active transistor SW2, L g1—int , L g_int : Equivalent inductance of the gate inside the devices of the passive transistor SW1 and the active transistor SW2, L s1—ext , L s_ext : Common-source parasitic inductance of the passive transistor SW1 and the active transistor SW2, L s1—int , L s_int : Parasitic inductance of the source inside the devices of the passive transistor SW1 and the active transistor SW2, L d1—ext , L d_ext : Equivalent inductance of the external drain of the passive transistor SW1 and the active transistor SW2, L d1—int , L d_int : Equivalent inductance of the drain inside the devices of the passive transistor SW1 and the active transistor SW2, V g1 : First gate drive voltage of the passive transistor SW1, V g : Second gate drive voltage of the active transistor SW2.

[0085] Furthermore, for subsequent analysis, the following parameters are defined in the embodiments of the present application: R g : Equivalent drive resistance, L g : Gate parasitic inductance, L s : Source parasitic inductance, L loop : Loop equivalent parasitic inductance, C oss : Output capacitance of the active transistor SW2, C iss : Input capacitance of the active transistor SW2, C oss1 : Output capacitance of the passive transistor SW1, where,

[0086] Rg = R g_ext + R g_int

[0087] L g = L g_ext + L g_int

[0088] L s = L s_ext + L s_int

[0089] C oss = C ds + C gd

[0090] C iss = C gs + C gd

[0091] C oss1 = C ds1 + C gd1

[0092] When analyzing the switching transient process of GaN HEMT, traditional models usually divide the switching process into four main stages. These stages are classified based on the mode of the channel current of the switching device. The following is a brief description of the turn-on process:

[0093] (1) Turn-on delay stage: When the driving power supply of the active transistor SW2, that is, the second gate driving voltage V g switches from low level to high level, the gate-source parasitic capacitance C gs of the active transistor SW2 starts to charge, and the active transistor SW2 remains in the off state. As the gate-source voltage V gs of the active transistor SW2 increases until the gate-source voltage V gs of the active transistor SW2 reaches the threshold voltage V th of the active transistor SW2, the working region of the active transistor SW2 starts to enter the saturation region, and the switching process enters the next stage.

[0094] (2) Current rising stage: When the gate-source voltage V gs of the active transistor SW2 reaches the threshold voltage V th of the active transistor SW2, the channel of the active transistor SW2 starts to conduct, and the drain current i d of the active transistor SW2 rises rapidly. Due to the effect of the parasitic inductance in the power loop, the drain-source voltage V ds of the active transistor SW2 starts to decrease. In this stage, the drain current i d of the active transistor SW2 increases relatively rapidly, the passive transistor SW1 transitions from reverse conduction to cut-off state, and the drain current id Gradually reach the load inductor current I L , and the current rising stage ends.

[0095] (3) Voltage drop stage (Miller stage): At this time, the output capacitance C of the active transistor SW2 oss causes the drain-source voltage V of the active transistor SW2 to drop rapidly through fast discharge ds , while the drain-source voltage V of the passive transistor SW1 ds1 begins to rise. During this process, the passive transistor SW1 transitions from reverse conduction to the cut-off region, and the operating region of the active transistor SW2 remains in the saturation region. When the drain-source voltage V of the active transistor SW2 ds drops to the difference between the gate-source voltage V of the active transistor SW2 gs minus the threshold voltage V of the active transistor SW2 th , the voltage drop stage ends.

[0096] (4) Oscillation stage: In this stage, the operating region of the active transistor SW2 enters the ohmic region, while the operating region of the passive transistor SW1 enters the cut-off region. The channel of the active transistor SW2 is fully conducting, approximated as the drain-source on-resistance R DS(on) , and the operating region of the passive transistor SW1 is in the cut-off state, which can be approximated as the output capacitance C of the active transistor SW2 oss . The loop inductor and the output capacitance interact with each other to form a second-order oscillation circuit, resulting in high-frequency oscillations of the drain-source voltage and current of the device until the system stabilizes.

[0097] For the analysis of the turn-off process, the traditional model can also be divided into the following four stages:

[0098] (1) Turn-off delay stage: When the drive power supply of the active transistor SW2, that is, the second gate drive voltage V g changes from high level to zero, the gate-source voltage V of the active transistor SW2 gs begins to drop, the input capacitance C of the active transistor SW2 iss begins to discharge, and at this time the drain-source voltage V of the active transistor SW2 ds and the drain current i d remain unchanged. When the operating region of the active transistor SW2 returns from the ohmic region to the saturation region, the turn-off delay stage ends.

[0099] (2) Voltage rising stage: As the gate-source voltage V of the active transistor SW2 gs drops, the channel current i of the active transistor SW2 ch rapidly decreases, the output capacitance C of the active transistor SW2 oss begins to charge, and the drain-source voltage V of the active transistor SW2 ds gradually rises. Due to the Miller effect of GaN HEMT, the drain current i of the active transistor SW2d At the same time, the drain-source voltage V ds1 The voltage starts to decrease, and when it reaches the reverse conduction voltage, the voltage rising phase ends.

[0100] (3) Current drop phase: In this phase, the passive transistor SW1 starts to conduct in the reverse direction and guides the reverse current to flow. At the same time, the channel current of the active transistor SW2 is affected by the gate-source voltage V gs Control, the drain current i of active tube SW2 d Decreases and gradually transfers to the passive tube SW1. When the gate-source voltage V gs The threshold voltage V of active transistor SW2 is reduced to th When , the working area of ​​the active tube SW2 returns from the saturation area to the cut-off area, and the current decrease stage ends.

[0101] (4) Shutdown oscillation stage: At this time, the working area of ​​the active tube SW2 completely enters the cut-off area, and the passive tube SW1 enters the reverse conduction state. The output capacitor C of the active tube SW2 oss The equivalent parasitic inductance L loop A second-order oscillation circuit is formed, and the system gradually stabilizes after the oscillation decays.

[0102] However, under high voltage fast switching transient conditions, due to the equivalent drive resistance R g Small, while the equivalent parasitic inductance L loop Large, resulting in the drain current i of the active tube SW2 during the switching process d The rate of change of d / dt is too large. Under the set working conditions, when the DC bus voltage V DC Small load inductor current I L When the value is large, the active transistor SW2 may enter the variable resistance region before the second-stage commutation is fully completed, that is, the active transistor SW2 may enter the cut-off region in advance before the passive transistor SW1 enters the reverse conduction state, which is beyond the prediction range of the traditional switch analysis model. This phenomenon is particularly significant in GaN HEMT devices and SiC MOSFET devices with fast response time and high electron mobility characteristics.

[0103] Based on the above analysis, the embodiment of the present application is designed specifically for the calibration phase of GaN HEMT switching transient testing, and is designed for two different working conditions: a normal working state and a fast switching transient state.

[0104] Specifically, Figure 2 As shown, a power circuit dynamic VI calibration system provided in an embodiment of the present application includes: a detection module 1, an identification module 2 and a calibration module 3.

[0105] The detection module 1 is used to perform real-time detection on the half-bridge circuit according to the first preset condition, and obtain the first detection value, the second detection value, the third detection value, and the fourth detection value.

[0106] The recognition module 2 is used to perform the following steps: determine whether the first detection value meets the second preset condition; if the first detection value meets the second preset condition, obtain the corresponding first detection time t 11 , and determine whether the second detection value meets the third preset condition; if the second detection value meets the third preset condition, obtain the corresponding second detection time t 12 ; determine whether the first detection time t 11 is less than or equal to the second detection time t 12 .

[0107] The calibration module 3 is used to perform the following steps: if the first detection time t 11 is greater than the second detection time t 12 , then based on the fourth preset condition, respectively capture the first turn-off transient waveform and the second turn-off transient waveform corresponding to the third detection value and the fourth detection value; based on the first turn-off transient waveform, obtain the third detection time t when the third detection value drops to 0 13 ; based on the second turn-off transient waveform, obtain the fourth detection time t corresponding to the fourth detection value dropping to the reverse conduction voltage V r ; calculate the difference between the third detection time t 14 and the fourth detection time t 13 to obtain the first time offset Δt1; use the first time offset Δt1 to adjust the first turn-off transient waveform so that the third detection time t of the first turn-off transient waveform 14 is aligned with the fourth detection time t of the second turn-off transient waveform 13 , and continue to perform real-time detection on the half-bridge circuit by the detection module 1 according to the first preset condition. 14

[0108] The calibration module 3 is further used to perform the following steps: based on the fifth preset condition, respectively capture the first turn-on transient waveform and the second turn-on transient waveform corresponding to the third detection value and the fourth detection value; based on the first turn-on transient waveform, obtain the fifth detection time t corresponding to the third detection value rising to the load inductance current I L ; based on the second turn-on transient waveform, obtain the sixth detection time t corresponding to the fourth detection value starting to transition and rise from the reverse conduction voltage V 15 ; based on the second turn-on transient waveform, obtain the sixth detection time t corresponding to the fourth detection value starting to transition and rise from the reverse conduction voltage V r ; calculate the difference between the fifth detection time t 16 and the sixth detection time t 15 ; calculate the difference between the fifth detection time t 16to obtain a second time offset Δt2; use the second time offset Δt2 to adjust the first turn-on transient waveform so that the third detection time t of the first turn-on transient waveform 15 is aligned with the fourth detection time t of the second turn-on transient waveform 16 , and continue to perform real-time detection on the half-bridge circuit by the detection module 1 according to the first preset condition.

[0109] The calibration module 3 is further configured to perform the following steps: If the first detection time t 11 is less than or equal to the second detection time t 12 , then obtain the change rate di d / dt of the drain current i d based on each third detection value as the fifth detection value; monitor the changes of the second detection value and the fifth detection value with the real-time detection time t during the turn-off process of the active transistor SW2, and respectively obtain a first waveform and a second waveform; based on the first waveform, obtain the seventh detection time t dsmax corresponding to the second detection value reaching a first maximum value V 17 ; based on the second waveform, obtain the absolute value of the fifth detection value reaching a second maximum value corresponding to the eighth detection time t 18 ; calculate the difference between the eighth detection time t 18 minus the seventh detection time t 17 to obtain a third time offset Δt3; use the third time offset Δt3 to adjust the second waveform so that the eighth detection time t of the second waveform 18 is aligned with the seventh detection time t of the first waveform 17 , and continue to perform real-time detection on the half-bridge circuit by the detection module 1 according to the first preset condition.

[0110] Compared with the prior art, a power loop dynamic VI calibration system provided by an embodiment of the present application obtains detection values by performing real-time detection on a half-bridge circuit, and obtains a first detection time and a second detection time in combination with a second preset condition and a third preset condition, and identifies a switch state through comparison of the first detection time and the second detection time; when there is a fast switch transient, by capturing a first turn-off transient waveform and a second turn-off transient waveform and calculating a first time offset, and by capturing a first turn-on transient waveform and a second turn-on transient waveform and calculating a second time offset, a dynamic voltage-current (VI) calibration is achieved by using the first time offset and the second time offset; when in a normal operating state, by monitoring the first waveform and the second waveform and calculating a third time offset, a dynamic voltage-current (VI) calibration is achieved by using the third time offset. An embodiment of the present invention effectively avoids measurement errors caused by high-frequency noise and time deviation in traditional voltage-current (VI) calibration by accurately analyzing the relationship between current and voltage during the switch transient process.

[0111] Corresponding to the power loop dynamic VI calibration system disclosed above, an embodiment of the present invention also discloses a power loop dynamic VI calibration method. The following describes in detail the power loop dynamic VI calibration method disclosed in the embodiment of the present invention in combination with the above-described power loop dynamic VI calibration system.

[0112] As Figure 3 shown, the following details the specific steps of a power loop dynamic VI calibration method provided by an embodiment of the present application.

[0113] A power loop dynamic VI calibration method provided by an embodiment of the present application, similarly, this method is applied to a half-bridge circuit including parasitic parameters.

[0114] The detection module 1 performs real-time detection on the half-bridge circuit according to a first preset condition to obtain a first detection value, a second detection value, a third detection value, and a fourth detection value.

[0115] In the embodiment of the present application, the first preset condition includes: setting the first gate drive voltage V of the passive transistor SW1 to zero. Applying a double-pulse signal voltage to the gate-source of the active transistor SW2 using the second gate drive voltage V. And applying a DC bus voltage V to the bus terminal of the half-bridge circuit. g1 And g . DC .

[0116] In the embodiment of the present invention, the first detection value, the second detection value, the third detection value, and the fourth detection value are respectively the gate-source voltage V of the active transistor SW2 in the half-bridge circuit, the drain-source voltage V, and the drain current i, and the drain-source voltage V of the passive transistor SW1 in the half-bridge circuit. In order to obtain the corresponding gate-source voltage V and drain-source voltage V of the active transistor SW2 and the drain-source voltage V of the passive transistor SW1, an oscilloscope and a passive probe can be used for measurement. At the same time, by using a coaxial shunt to measure the drain current i of the active transistor SW2 and directly calculating using the oscilloscope, the waveform of the change rate di / dt of the drain current i can be obtained. As shown in and, where t0 is defined as the moment when the drain current i of the active transistor SW2 starts to rise. gs , the drain-source voltage V ds and the drain current i d as well as the drain-source voltage V ds1 of the passive transistor SW1 in the half-bridge circuit. In order to obtain the corresponding gate-source voltage V gs and drain-source voltage V ds of the active transistor SW2 and the drain-source voltage V ds1 of the passive transistor SW1, an oscilloscope and a passive probe can be used for measurement. At the same time, by using a coaxial shunt to measure the drain current i d of the active transistor SW2 and directly calculating using the oscilloscope, the waveform of the change rate di d / dt of the drain current i d can be obtained. As Figure 5a and Figure 5b shown, where, t0 is defined as the moment when the drain current i d of the active transistor SW2 starts to rise.

[0117] First, it is necessary to determine whether the actual switching process is in the normal working state or the fast-switching transient state. In the normal working state, the equivalent drive resistance R g is relatively large, and the equivalent parasitic inductance L of the loop loop does not reach an extreme level; while in the fast-switching transient state, the equivalent drive resistance R g significantly decreases, and the equivalent parasitic inductance L of the loop loop increases correspondingly.

[0118] In the normal working state, when the operating region of the active transistor SW2 of the GaN HEMT is in the saturation region, the drain current i d of the active transistor SW2 is equal to the channel current i ch , and can be expressed by the gate-source voltage V gs as shown in the following first formula:

[0119] i d = i ch = g m (V gs - V th )

[0120] where g m is the transconductance of the active transistor SW2, and V th is the threshold voltage of the active transistor SW2. Taking EPC2045 as an example, it can be known from its data sheet that the threshold voltage of the corresponding active transistor SW2 is 1.4V.

[0121] The condition for the passive transistor SW1 to enter the cut-off state from the reverse conduction state is that the drain current i d of the active transistor SW2 reaches the load inductor current I L , then the corresponding gate-source voltage V gs can be calculated by the following second formula:

[0122]

[0123] where I L is the load inductor current, g is the transconductance of the active transistor SW2, and V th is the threshold voltage of the active transistor SW2.

[0124] The condition for the operating region of the active transistor SW2 to enter the ohmic region is as follows in the third formula:

[0125] V ds = V gs - V th

[0126] where V th is the threshold voltage of the active transistor SW2.

[0127] As described above, in the embodiments of the present application, the above second formula and third formula are respectively used as the second preset condition and the third preset condition. The moment when the first detection value satisfies the second preset condition is the first detection time t 11 , and the moment when the second detection value satisfies the third preset condition is the second detection time t 12 . In this way, the satisfaction condition for the normal working state is that the first detection time t 11 is less than or equal to the second detection time t 12 ; the satisfaction condition for the fast-switching transient state is that the first detection time t 11 is greater than the second detection time t 12 .

[0128] The preset value of the second gate drive voltage V g needs to refer to the withstand range of the gate-source voltage V gs of the active transistor SW2. Taking EPC2045 as an example, since the withstand range of the gate-source voltage V gs of the active transistor SW2 is greater than or equal to -4V and less than or equal to 6V, therefore, the second gate drive voltage V g can be set to be greater than or equal to 0V and less than or equal to 5V. The preset value of the DC bus voltage V DC needs to refer to the withstand range of the drain-source voltage V ds of the active transistor SW2. For EPC2045, the maximum withstand value of the drain-source voltage V ds of the active transistor SW2 is 120V, so the DC bus voltage V DC can be set to typical values such as 12V, 24V, 36V, or 48V. The preset value of the load inductor current I L needs to refer to the withstand range of the drain current i d of the active transistor SW2. Taking EPC2045 as an example, the continuous maximum withstand value of its drain current i d is 16A, so the load inductor current I L should be set to a reasonable range below 16A.

[0129] In addition, considering the basic principle of the double-pulse test, that is, according to the set load inductor current I L , DC bus voltage V DC and the size of the load inductor L, it is necessary to set the first pulse time of the second gate drive voltage V g . Further, the first pulse time of the second gate drive voltage V g is set to the first preset threshold t g , and the calculation formula of the first preset threshold t g is:

[0130]

[0131] Among them, L is the value of the load inductor, and I L is the load inductor current, and V DC is the DC bus voltage.

[0132] As described above, as Figure 3 shown, in the embodiment of the present application, the following describes the specific steps for determining whether the actual switching process is in the normal operating state or the fast switching transient state.

[0133] It is determined by the identification module 2 whether the first detection value satisfies the second preset condition.

[0134] In the embodiment of the present invention, the second preset condition is:

[0135]

[0136] Among them, I L is the load inductor current, g m is the transconductance of the active transistor SW2, and V th is the threshold voltage of the active transistor SW2.

[0137] If the first detection value does not satisfy the second preset condition, the detection module 1 continues to perform real-time detection on the half-bridge circuit according to the first preset condition.

[0138] If the first detection value satisfies the second preset condition, the identification module 2 obtains the corresponding first detection time t 11 , and the identification module 2 determines whether the second detection value satisfies the third preset condition.

[0139] In the embodiment of the present invention, the third preset condition is:

[0140] V ds = V gs - V th

[0141] Among them, V th is the threshold voltage of the active transistor SW2.

[0142] If the second detection value does not satisfy the third preset condition, the detection module 1 continues to perform real-time detection on the half-bridge circuit according to the first preset condition.

[0143] If the second detection value satisfies the third preset condition, the identification module 2 obtains the corresponding second detection time t 12 ;

[0144] It is determined by the identification module 2 whether the first detection time t 11 is less than or equal to the second detection time t 12 .

[0145] If the first detection time t 11 is greater than the second detection time t 12 , then the current is in the fast-switching transient state.

[0146] In the embodiments of the present application, corresponding VI calibration methods are used for dynamic calibration for different switching states. For the fast-switching transient state, in the turn-off process in this case, the voltage relationship of the power loop is as follows:

[0147]

[0148] L d = L d_ext + L d_int

[0149] L s = L s_ext + L s_int

[0150] When the drain-source voltage V ds of the active transistor SW2 reaches the maximum value, it is necessary to ensure that:

[0151]

[0152] It can be seen that for fast transient tests, the influence of high-frequency noise makes it difficult to obtain second-order differential processing. Therefore, in response to this situation, the embodiments of the present application use the relationship between the voltage change point under the switching transient of the passive transistor SW1 and the drain current i d of the active transistor SW2 for corresponding calibration.

[0153] During the fast-switching transient process, during the turn-on process, when the drain current i d of the active transistor SW2 reaches the load inductor current I L , it corresponds to the moment when the drain-source voltage V ds1 of the passive transistor SW1 starts to transition and rise from the reverse conduction voltage V r . During the turn-off process, the moment when the drain-source voltage V ds1 of the passive transistor SW1 returns from the DC bus voltage V DC to the reverse conduction voltage V r corresponds to the drain current i d of the active transistor SW2 being equal to 0. Therefore, dynamic voltage-current (VI) calibration can be performed through these two special moments. V r is preset as the reverse conduction voltage of the active transistor SW2. Taking EPC2045 as an example, it can be seen from its data sheet that the reverse conduction voltage V r is equal to -1.7V.

[0154] Based on the above relationship, by monitoring the drain current i dand the drain-source voltage V of the passive switch SW1 ds1 to perform VI calibration. As Figure 6a shown, during the turn-on process, first detect the drain current i of the active switch SW2 d reaches the load inductor current I L moment, and at the same time find the drain-source voltage V of the passive switch SW1 ds1 starts to transition and rise from the reverse conduction voltage V r moment, and then calculate the time difference between these two moments. As Figure 6b shown, similarly, during the turn-off process, first detect the drain current i of the active switch SW2 d drops to 0 moment, and at the same time find the drain-source voltage V of the passive switch SW1 ds1 from the DC bus voltage V DC returns to the reverse conduction voltage V r moment, and then calculate the time difference between these two moments. By adjusting the test equipment or model parameters, these time differences can be used to accurately calibrate the VI relationship and achieve dynamic calibration.

[0155] Then, the calibration module 3 captures the first turn-off transient waveform and the second turn-off transient waveform corresponding to the third detection value and the fourth detection value respectively based on the fourth preset condition.

[0156] In the embodiment of the present application, the fourth preset condition is: the dual-pulse signal voltage reaches the falling edge of the first pulse. As Figure 5a and Figure 5b shown, use the second gate drive voltage V g to apply a dual-pulse signal voltage to the gate-source of the active switch SW2, that is, the gate-source voltage V of the active switch SW2 gs is the dual-pulse signal voltage. Based on the above fourth preset condition, at the falling edge of the first pulse, the turn-off transient waveform of the device, that is, the first turn-off transient waveform and the second turn-off transient waveform, can be captured.

[0157] The calibration module 3 obtains the third detection time t corresponding to the third detection value dropping to 0 based on the first turn-off transient waveform 13 .

[0158] The calibration module 3 obtains the fourth detection time t corresponding to the fourth detection value dropping to the reverse conduction voltage V based on the second turn-off transient waveform r 14 .

[0159] The calibration module 3 calculates the difference between the third detection time t 13 minus the fourth detection time t 14 to obtain the first time offset Δt1.

[0160] ​The calibration module 3 adjusts the first turn-off transient waveform by using the first time offset Δt1, so that the third detection time t of the first turn-off transient waveform 13 is aligned with the fourth detection time t of the second turn-off transient waveform 14 , and the detection module 1 continues to perform real-time detection on the half-bridge circuit according to the first preset condition.

[0161] Based on the fifth preset condition, the calibration module 3 captures the first turn-on transient waveform and the second turn-on transient waveform corresponding to the third detection value and the fourth detection value respectively.

[0162] In the embodiment of the present application, the fifth preset condition is: the voltage of the double-pulse signal reaches the rising edge of the second pulse. As Figure 5a and Figure 5b shown, a double-pulse signal voltage is applied to the gate-source of the active transistor SW2 by using the second gate drive voltage V g , that is, the gate-source voltage V gs of the active transistor SW2 is the double-pulse signal voltage. Based on the above fifth preset condition, the turn-on transient waveforms of the device, namely the first turn-on transient waveform and the second turn-on transient waveform, can be captured at the rising edge of the second pulse.

[0163] Based on the first turn-on transient waveform, the calibration module 3 obtains the fifth detection time t corresponding to the third detection value rising to the load inductor current I L . 15 .

[0164] Based on the second turn-on transient waveform, the calibration module 3 obtains the sixth detection time t corresponding to the fourth detection value starting to transition and rise from the reverse conduction voltage V r . 16 .

[0165] The calibration module 3 calculates the difference between the fifth detection time t 15 minus the sixth detection time t 16 to obtain the second time offset Δt2.

[0166] The calibration module 3 adjusts the first turn-on transient waveform by using the second time offset Δt2, so that the third detection time t of the first turn-on transient waveform 15 is aligned with the fourth detection time t of the second turn-on transient waveform 16 , and the detection module 1 continues to perform real-time detection on the half-bridge circuit according to the first preset condition.

[0167] For the normal working state, at this time, for the turn-off process of the active transistor SW2, the following equation can be listed based on the KVL relationship:

[0168]

[0169] Among them, V r is the reverse conduction voltage of the passive transistor SW1, and V DC is the DC bus voltage.

[0170] Therefore, the voltage overshoot of the active transistor SW2 is closely related to the voltage drop of the parasitic inductance caused by the change rate di d of its drain current i d / dt. Specifically, during the turn-off process, when the absolute value |di d | of the change rate di d / dt of the drain current i d / d t reaches the maximum value (i.e., the second maximum value ), the overshoot of the drain-source voltage V ds of the active transistor SW2 will also reach the maximum value (i.e., the first maximum value V dsmax ).

[0171] Based on the above relationship, the VI calibration can be performed by monitoring the change rate di d / dt of the drain current i d and the overshoot of the drain-source voltage V ds of the active transistor SW2. First, the moment corresponding to the first maximum value V dsmax is detected, and at the same time, the moment corresponding to the second maximum value is found, and then the time difference between these two moments is calculated. Using this time difference (time offset), the channel delay parameter of the current measurement probe can be adjusted in the channel setting menu of the oscilloscope, and the time offset is increased to accurately calibrate the voltage-current (VI) relationship; or the original data of the current measurement can be time-corrected through modeling programs such as Matlab and Python, and the time offset is increased to achieve dynamic voltage-current (VI) calibration. As Figure 7 shown, it is the waveform diagram of the change rate di d / dt of the drain current i d of the active transistor SW2 before and after calibration and the waveform diagram of the drain-source voltage V ds provided by an embodiment of the present invention under normal working conditions.

[0172] Referring to Figure 3 and Figure 4 , if the first detection time t 11 is less than or equal to the second detection time t 12 , then the calibration module 3 obtains the change rate di d / dt of the drain current i d based on each third detection value as the fifth detection value.

[0173] The calibration module 3 monitors the changes of the second detection value and the fifth detection value with the real-time detection time t during the turn-off process of the active switch SW2, and respectively obtains the first waveform and the second waveform.

[0174] Based on the first waveform, the calibration module 3 obtains the seventh detection time t corresponding to the second detection value reaching the first maximum value V dsmax 17 .

[0175] Based on the second waveform, the calibration module 3 obtains the eighth detection time t corresponding to the absolute value of the fifth detection value reaching the second maximum value 18 .

[0176] The calibration module 3 calculates the difference between the eighth detection time t 18 minus the seventh detection time t 17 to obtain the third time offset Δt3.

[0177] The calibration module 3 adjusts the second waveform using the third time offset Δt3 so that the eighth detection time t of the second waveform 18 is aligned with the seventh detection time t of the first waveform 17 , and the detection module 1 continues to perform real-time detection on the half-bridge circuit according to the first preset condition.

[0178] Compared with the prior art, a power loop dynamic VI calibration method provided by an embodiment of the present application obtains detection values through real-time detection of a half-bridge circuit, combines the second preset condition and the third preset condition to obtain the first detection time and the second detection time, and identifies the switch state through the comparison of the first detection time and the second detection time; when there is a fast switch transient, the first turn-off transient waveform and the second turn-off transient waveform are captured and the first time offset is calculated, the first turn-on transient waveform and the second turn-on transient waveform are captured and the second time offset is calculated, and the first time offset and the second time offset are used to achieve dynamic voltage-current (VI) calibration; when in the normal working state, the first waveform and the second waveform are monitored and the third time offset is calculated, and the third time offset is used to achieve dynamic voltage-current (VI) calibration. The embodiment of the present invention effectively avoids measurement errors caused by high-frequency noise and time deviation in traditional voltage-current (VI) calibration by accurately analyzing the relationship between current and voltage during the switch transient process.

[0179] The embodiment of the present application can adapt to different switch speeds and circuit parameters, ensuring the accuracy and synchronization of voltage and current measurements before the switch transient test of GaN HEMT. Through this method in the embodiment of the present application, the reliability of the test results can be significantly improved, providing a solid foundation for the performance evaluation and optimization of power electronic devices.

[0180] ​​To verify the effectiveness of the dynamic voltage-current calibration for GaN HEMT switch transient testing proposed in the embodiments of this application, a GaN HEMT double-pulse test considering parasitic parameters is used to verify the calibration method proposed in the embodiments of this application.

[0181] First, the model is applied to the conventional situation, where the equivalent drive resistance R g is relatively large and the parasitic inductance of the power loop does not reach an extreme level in the double-pulse test. In the embodiments of this application, the EPC2045 device is selected for testing, and the set working conditions are as follows: the equivalent drive resistance R g is equal to 50 Ω, the DC bus voltage V DC is equal to 48 V, the load inductor current I L is equal to 11 A, the gate parasitic inductance L g is equal to 1.66 nH, the source parasitic inductance L s is equal to 500 pH. When the loop parasitic inductance L loop is equal to 15.5 n, the double-pulse test results under this simulation working condition are as Figure 10 shown. When the loop parasitic inductance L loop is equal to 10.5 n, the double-pulse test results under this simulation working condition are as Figure 11 shown. As shown by Figure 10 and Figure 11 , it can be seen that in the conventional switching process, the maximum point of the change rate di d / dt of the drain current i d corresponds exactly to the point where the drain-source voltage V ds of the active transistor SW2 reaches the first maximum value V dsmax . Therefore, it can be used for voltage-current (VI) calibration.

[0182] After that, a double-pulse test is carried out under the fast-switching transient condition. A specific simulation working condition provided by the embodiments of this application is as follows: the DC bus voltage V DC is equal to 48 V, the load inductor current I L is equal to 11 A, the equivalent drive resistance R g is equal to 6 Ω, the loop parasitic inductance L loop is equal to 15.5 n, the gate parasitic inductance L g is equal to 1.66 nH, the source parasitic inductance L s is equal to 500 pH, and the reverse conduction voltage V r of EPC2045 is equal to -1.7 V, and the VI alignment point is judged. As shown by Figure 8a , for the turn-on process, the drain current i d of the active transistor SW2 is equal to the load inductor current I L corresponding to the fifth detection time t 15is 9.6175683 us, and the drain-source voltage V of the passive transistor SW1 ds1 equals the reverse conduction voltage V r The corresponding sixth detection time t 16 is 9.6170406 us, and the fifth detection time t 15 and the sixth detection time t 16 differ by 0.5277 nS. As Figure 8b shown, for the turn-off process, the drain current i of the active transistor SW2 d equals 0, and the corresponding third detection time t 13 is 3.462545 us. The drain-source voltage V of the passive transistor SW1 ds1 equals the reverse conduction voltage V r The corresponding fourth detection time t 14 is 3.462565 us. The difference between the third detection time t 13 and the fourth detection time t 14 is 0.02 nS.

[0183] Another specific simulation condition provided by the embodiment of the present application is: the DC bus voltage V DC equals 48 V, the load inductor current I L equals 11 A, the equivalent drive resistance R g equals 6 Ω, the loop parasitic inductance L loop equals 10.5 nH, and the reverse conduction voltage V of EPC2045 r equals -1.7 V. Then, the VI alignment point is judged. As Figure 9a shown, for the turn-on process, the drain current i of the active transistor SW2 d equals the load inductor current I L The corresponding fifth detection time t 15 is 9.6164968 us. The drain-source voltage V of the passive transistor SW1 ds1 equals the reverse conduction voltage V r The corresponding sixth detection time t 16 is 9.6161468 us. The difference between the fifth detection time t 15 and the sixth detection time t 16 is 0.35 nS. As Figure 9b shown, for the turn-off process, the drain current i of the active transistor SW2 d equals 0, and the corresponding third detection time t 13 is 3.462675 us. The drain-source voltage V of the passive transistor SW1 ds1 equals the reverse conduction voltage V r The corresponding fourth detection time t 14 is 3.462475 us. The third detection time t 13Subtract the fourth detection time t 14 The difference is 0.2 nS.

[0184] As described above, for the double-pulse test results under two simulation conditions of the fast-switching transient, the difference between the alignment points of the turn-on process and the turn-off process is less than 0.6 ns, within the allowable error time range, and the dynamic voltage-current (VI) calibration of the GaN HEMT switch transient test is completed.

[0185] The embodiment of the present application simplifies the calibration process. Without complex voltage-current (VI) calibration, by using key electrical characteristic points during the switching process, such as the maximum voltage overshoot point and the maximum current change rate point, accurate calibration can be achieved, greatly simplifying the calibration process.

[0186] In addition, the embodiment of the present invention also provides a power loop dynamic VI calibration device, which includes: a processor and a memory; the memory is used to store one or more program instructions; the processor is used to run one or more program instructions to execute the steps of a power loop dynamic VI calibration method as described in any one of the above.

[0187] In addition, the embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of a power loop dynamic VI calibration method as described in any one of the above are implemented.

[0188] In the embodiment of the present invention, the processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, a digital signal processor (DSP for short), an application specific integrated circuit (ASIC for short), a field programmable gate array (FPGA for short), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0189] It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present invention can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the art such as random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, register, etc. The processor reads the information in the storage medium and combines its hardware to complete the steps of the above method.

[0190] The storage medium can be a memory, for example, it can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories.

[0191] Among them, the non-volatile memory can be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash memory.

[0192] The volatile memory can be a Random Access Memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DRRAM).

[0193] The storage medium described in the embodiments of the present invention is intended to include but not limited to these and any other suitable types of memories.

[0194] Those skilled in the art should be able to realize that in one or more of the above examples, the functions described in the present invention can be implemented by a combination of hardware and software. When applying software, the corresponding functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. The computer-readable medium includes computer storage media and communication media, where the communication media includes any medium that facilitates the transfer of a computer program from one place to another. The storage medium can be any available medium that can be accessed by a general or special-purpose computer.

[0195] Although the present invention has been described in detail above with general descriptions and specific embodiments, on the basis of the present invention, some modifications or improvements can be made, which are obvious to those skilled in the art. Therefore, these modifications or improvements made without departing from the spirit of the present invention all fall within the scope of the present invention claimed.

Claims

1. A power circuit dynamic VI calibration method, characterized in that: The method comprises: Performing real-time detection on the half-bridge circuit according to the first preset condition to obtain a first detection value, a second detection value, a third detection value, and a fourth detection value; Determining whether the first detection value meets a second preset condition; If the first detection value meets the second preset condition, the corresponding first detection time t is obtained. 11 , and determining whether the second detection value satisfies a third preset condition; If the second detection value meets the third preset condition, the corresponding second detection time t is obtained. 12 ; Determine the first detection time t 11 whether it is less than or equal to the second detection time t2; If the first detection time t 11 Greater than the second detection time t 12 , then based on the fourth preset condition, the first turn-off transient waveform and the second turn-off transient waveform corresponding to the third detection value and the fourth detection value are captured respectively; Based on the first turn-off transient waveform, obtain the third detection time t corresponding to the third detection value dropping to 0 13 ; Based on the second turn-off transient waveform, the fourth detection value is obtained to drop to the reverse conduction voltage V r The corresponding fourth detection time t 14 ; Calculate the third detection time t 13 Subtract the fourth detection time t 14 The difference between the values ​​of Δt1 and Δt2 is obtained. The first time offset Δt1 is used to adjust the first turn-off transient waveform so that the third detection time t 13 The fourth detection time t of the second turn-off transient waveform 14 Align, and continue to perform real-time detection on the half-bridge circuit according to the first preset condition.

2. A power circuit dynamic VI calibration method as claimed in claim 1, characterized in that: The first detection value, the second detection value, the third detection value and the fourth detection value are respectively the gate-source voltage V of the active transistor SW2 in the half-bridge circuit. gs , drain-source voltage V ds and the drain current i d And the drain-source voltage V of the passive tube SW1 in the half-bridge circuit ds1 .

3. A power circuit dynamic VI calibration method as claimed in claim 2, characterized in that: The method further comprises: Based on a fifth preset condition, a first turn-on transient waveform and a second turn-on transient waveform corresponding to the third detection value and the fourth detection value are captured respectively; Based on the first turn-on transient waveform, the third detection value is obtained to rise to the load inductor current I L The corresponding fifth detection time t 15 ; Based on the second turn-on transient waveform, the fourth detection value is obtained starting from the reverse conduction voltage V r The sixth detection time t corresponding to the transition rise 16 ; Calculate the fifth detection time t 15 Subtract the sixth detection time t 16 The difference between the values ​​of Δt2 and Δt2 is obtained; The first turn-on transient waveform is adjusted by using the second time offset Δt2 so that the third detection time t 15 The fourth detection time t of the second turn-on transient waveform 16 Align, and continue to perform real-time detection on the half-bridge circuit according to the first preset condition.

4. A power circuit dynamic VI calibration method as claimed in claim 3, characterized in that: The method further comprises: If the first detection time t 11 Less than or equal to the second detection time t 12 , then the drain current i is obtained based on each third detection value d The rate of change of d / dt, as the fifth detection value; During the process of turning off the active switch SW2, monitor the changes of the second detection value and the fifth detection value with the real-time detection time t, and obtain the first waveform and the second waveform respectively; Based on the first waveform, the second detection value is obtained to reach a first maximum value V dsmax The corresponding seventh detection time t 17 ; Based on the second waveform, the absolute value of the fifth detection value is obtained to reach a second maximum value The corresponding eighth detection time t 18 ; Calculate the eighth detection time t 18 Subtract the seventh detection time t 17 The difference between the values ​​of Δt and Δt3 is obtained; The second waveform is adjusted by using the third time offset Δt3 so that the eighth detection time t 18 The seventh detection time t of the first waveform 17 Align, and continue to perform real-time detection on the half-bridge circuit according to the first preset condition.

5. A power circuit dynamic VI calibration method as claimed in claim 4, characterized in that: The first preset condition includes: The first gate drive voltage V of the passive tube SW1 g1 Set to zero; Using the second gate drive voltage V g Apply a double pulse signal voltage to the gate source of the active transistor SW2; and A DC bus voltage V is applied to the bus terminal of the half-bridge circuit. DC .

6. A power circuit dynamic VI calibration method as claimed in claim 5, characterized in that: The method further comprises: If the first detection value does not satisfy the second preset condition, or the second detection value does not satisfy the third preset condition, the half-bridge circuit continues to be detected in real time according to the first preset condition.

7. A power circuit dynamic VI calibration method as claimed in claim 6, characterized in that: The second preset condition is: Among them, I L is the load inductor current, g m is the transconductance of active transistor SW2, V th is the threshold voltage of active transistor SW2; The third preset condition is: V ds =V gs -V th Among them, V th is the threshold voltage of active transistor SW2.

8. A power circuit dynamic VI calibration system, characterized in that: The system comprises: A detection module, used to perform real-time detection on the half-bridge circuit according to a first preset condition to obtain a first detection value, a second detection value, a third detection value and a fourth detection value; Identify a module that performs the following steps: Determining whether the first detection value meets a second preset condition; If the first detection value meets the second preset condition, the corresponding first detection time t is obtained. 11 , and determining whether the second detection value satisfies a third preset condition; If the second detection value meets the third preset condition, the corresponding second detection time t is obtained. 12 ; Determine the first detection time t 11 Is it less than or equal to the second detection time t 12 ;as well as A calibration module is used to perform the following steps: If the first detection time t 11 Greater than the second detection time t 12 , then based on the fourth preset condition, the first turn-off transient waveform and the second turn-off transient waveform corresponding to the third detection value and the fourth detection value are captured respectively; Based on the first turn-off transient waveform, obtain the third detection time t corresponding to the third detection value dropping to 0 13 ; Based on the second turn-off transient waveform, the fourth detection value is obtained to drop to the reverse conduction voltage V r The corresponding fourth detection time t 14 ; Calculate the third detection time t 13 Subtract the fourth detection time t 14 The difference between the values ​​of Δt1 and Δt2 is obtained. The first time offset Δt1 is used to adjust the first turn-off transient waveform so that the third detection time t 13 The fourth detection time t of the second turn-off transient waveform 14 The detection module continues to perform real-time detection on the half-bridge circuit according to the first preset condition.

9. A power circuit dynamic VI calibration device, characterized in that: The device comprises: a processor and a memory; The memory is used to store one or more program instructions; The processor is used to run one or more program instructions to execute the steps of a power circuit dynamic VI calibration method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of a power circuit dynamic VI calibration method as claimed in any one of claims 1 to 7 are implemented.

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