Processor, processing method and system for automatically selecting RISC-V or X86 instruction set during initialization

Abstract

The present invention discloses a processor, processing method, and system for automatically selecting the RISC-V or X86 instruction set during the initialization phase. The processor includes an instruction stream detection module and a decoding configuration module. The decoding configuration module includes a multiplexer, a RISC-V decoding circuit, and an X86 decoding circuit. The instruction stream detection module is configured to extract an instruction stream, detect and analyze it, and then output a corresponding ISA control signal; the multiplexer is configured to receive the ISA control signal and connect the corresponding decoding circuit accordingly; the ISA control signal includes a first signal and a second signal. When the instruction stream detection module outputs the first signal, the multiplexer connects the X86 decoding circuit; when the instruction stream detection module outputs the second signal, the multiplexer connects the RISC-V decoding circuit. The processor of the present invention can automatically detect instruction stream features and configure corresponding decoding circuits, simplifying the CPU initialization process.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a processor, processing method, and system for automatically selecting a RISC-V or X86 instruction set during an initialization phase. Background Art

[0002] The instruction set architecture (ISA) is the core abstract model of computer architecture, determining how the processor is controlled by software. Common ISAs include x86 (widely used in personal computers and servers) and RISC-V (popular in embedded systems and emerging sectors due to its open-source and low-power nature). ISAs allow different implementations of the same architecture to vary in performance, size, and cost while maintaining binary compatibility. However, traditional CPUs are designed with a single ISA (such as x86 or RISC-V) and are unable to adapt to different software environments during initialization, resulting in wasted hardware resources or the need for multiple specialized CPUs. This single-ISA CPU design limits its application in multi-ISA environments, particularly those requiring compatibility with diverse software ecosystems. In modern computing, the need to support multiple ISAs is growing. For example, in cloud computing, virtual machines may need to run both x86 and RISC-V applications. In IoT devices, switching ISAs may be necessary based on task requirements to optimize power consumption and performance. Therefore, developing CPUs that can flexibly support multiple ISAs has become a significant technical challenge.

[0003] To address the above issues, a common approach in the prior art is to achieve compatibility by simulating the execution environment of one ISA on a CPU supporting another ISA through software emulation. For example, QEMU can run RISC-V programs on an X86 processor. While this approach can achieve compatibility between different ISAs, it suffers from significant technical deficiencies, including high performance overhead, low resource efficiency, and poor real-time performance. The instruction translation or interpretation process results in low execution efficiency, making it difficult to meet high-performance computing requirements. Furthermore, the emulation environment consumes additional resources, reducing system efficiency. For applications with high real-time requirements, the latency and uncertainty of the emulation further limit its applicability. On the other hand, existing processors that support multiple ISAs typically require complex hardware design or software intervention during initialization to determine which ISA to use. This approach not only increases development difficulty but may also introduce additional runtime overhead.

[0004] The disclosure of the above background technology content is only used to assist in understanding the inventive concept and technical solution of the present invention. It does not necessarily belong to the prior art of the present application, nor does it necessarily provide technical guidance. In the absence of clear evidence that the above content has been disclosed before the filing date of the present application, the above background technology should not be used to evaluate the novelty and creativity of the present application. Summary of the Invention

[0005] The purpose of the present invention is to provide a processor, processing method and system for automatically selecting RISC-V or X86 instruction sets during the initialization phase, which can automatically detect instruction stream characteristics and configure corresponding decoding circuits, thereby simplifying the CPU initialization process.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0007] A processor for automatically selecting a RISC-V or X86 instruction set during an initialization phase, comprising an instruction stream detection module and a decoding configuration module, the decoding configuration module comprising a multiplexer, a RISC-V decoding circuit, and an X86 decoding circuit, the multiplexer selectively electrically connected to the RISC-V decoding circuit or the X86 decoding circuit, the instruction stream detection module configured to extract an instruction stream, detect and analyze it, and then output a corresponding ISA control signal, the instruction stream comprising a RISC-V instruction sequence and / or an X86 instruction sequence; the multiplexer configured to receive the ISA control signal output by the instruction stream detection module and select and connect to a corresponding decoding circuit based on the ISA control signal;

[0008] The ISA control signal includes a first signal and a second signal. When the instruction stream detection module outputs the first signal, the multiplexer selects and connects to the X86 decoding circuit; when the instruction stream detection module outputs the second signal, the multiplexer selects and connects to the RISC-V decoding circuit.

[0009] The present invention realizes an efficient mechanism for the CPU to automatically select the X86 decoding circuit or the RISC-V decoding circuit according to the characteristics of the instruction stream during the initialization phase through the collaborative work of the instruction stream detection module and the decoding configuration module. The decoding configuration module generates an ISA control signal based on the detection results of the instruction stream detection module, thereby activating the X86 decoding circuit or the RISC-V decoding circuit inside the CPU. This dynamic configuration method can ensure that instructions are executed in a native manner without the need for translation or simulation, thereby significantly improving the initialization efficiency; this design allows a single CPU chip to automatically adapt to the corresponding instruction set according to the actual instruction content during initialization, greatly improving the flexibility of the system and reducing the waste of hardware resources. In addition, the decoding configuration module achieves fast switching through the hardware multiplexer, which is conducive to optimizing system performance.

[0010] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions described above, the instruction stream detection module includes an instruction register and a value-taking unit, the instruction register is electrically connected to the value-taking unit, the instruction stream is stored in the instruction register, and the value-taking unit is configured to take out the lower 8 bits of the instruction stream.

[0011] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions described above, the instruction stream detection module also includes a first comparator and a second comparator, and the first comparator and the second comparator are both connected to the value obtaining unit.

[0012] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the first comparator is configured to compare the lower 8 bits of the instruction stream retrieved by the value retrieval unit with a preset first fixed bit pattern and output a comparison result, and the second comparator is configured to compare the lower 7 bits of the instruction stream retrieved by the value retrieval unit with a preset second fixed bit pattern and output a comparison result. In some embodiments of the present invention, the first fixed bit pattern is the binary number 11101010, and the second fixed bit pattern is the binary number 1101111.

[0013] When the CPU starts, the instruction stream detection module reads the initial instruction stream from the reset vector in the memory of the instruction register and uses hardware logic (first comparator and second comparator) to quickly analyze its features, including instruction length and operation code mode. By analyzing these features, the RISC-V instruction set can be efficiently distinguished from the X86 instruction set.

[0014] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions described above, the multiplexer includes a control port and an output port, the control port is selectively electrically connected to the first comparator or the second comparator, and the control port is configured to receive an ISA control signal; the output port is selectively electrically connected to the RISC-V decoding circuit or the X86 decoding circuit, and the output port is configured to connect to the corresponding decoding circuit according to the ISA control signal.

[0015] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions described above, when the comparison result of the first comparator is consistent, the first comparator outputs the first signal to the multiplexer; when the comparison result of the first comparator is inconsistent, the second comparator responds to the comparison result and compares the lower 7 bits of the instruction stream obtained in the value-taking unit with a preset second fixed bit pattern.

[0016] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions described above, when the comparison result of the second comparator is consistent, the second comparator outputs the second signal to the multiplexer; otherwise, the second comparator outputs an abnormal signal.

[0017] Specifically, when the first comparator outputs a first signal after analysis and comparison, the control port of the multiplexer is now electrically connected to the first comparator, and at the same time, the output port of the multiplexer is connected to the X86 decoding circuit, so that the current instruction stream can be accurately sent to the X86 decoding circuit for subsequent processing. When the first comparator outputs a signal indicating an inconsistent comparison result after analysis and comparison, the second comparator will further compare the lower 7 bits of the instruction stream. When the second comparator outputs a second signal after analysis and comparison, the control port of the multiplexer is now electrically connected to the second comparator, and at the same time, the output port of the multiplexer is connected to the RISC-V decoding circuit, so that the current instruction stream can be accurately sent to the RISC-V decoding circuit for subsequent processing.

[0018] Furthermore, any one of the technical solutions or a combination of multiple technical solutions described above also includes an exception handling module, and the second comparator is also connected to the exception handling module, and the exception handling module is configured to receive the exception signal and perform exception processing on the instruction stream.

[0019] Further, based on any one of the technical solutions or a combination of multiple technical solutions described above, the first fixed bit pattern is stored in a first comparator, and the second fixed bit pattern is stored in a second comparator.

[0020] According to another aspect of the present invention, a method for automatically selecting a RISC-V or X86 instruction set during an initialization phase based on the above-mentioned processor is provided, comprising the following steps:

[0021] During the CPU initialization phase, the instruction stream is taken out by the instruction stream detection module, and after detection and analysis, the corresponding ISA control signal is output to the multiplexer.

[0022] After receiving the ISA control signal, the multiplexer selects and connects to the RISC-V decoding circuit or the X86 decoding circuit, so that the instruction stream is sent to the corresponding decoding circuit.

[0023] Furthermore, based on any one of the above technical solutions or a combination of multiple technical solutions, the method in which the instruction stream detection module extracts the instruction stream, detects and analyzes it, and then outputs the corresponding ISA control signal to the multiplexer is as follows:

[0024] The instruction stream detection module first compares the lower 8 bits of the obtained instruction stream with a preset first fixed bit pattern, and outputs a first signal if the comparison results are consistent;

[0025] If the comparison result is inconsistent, the lower 7 bits of the obtained instruction stream are compared with the preset second fixed bit pattern. If the comparison result is consistent, the second signal is output; otherwise, an abnormal signal is output.

[0026] Furthermore, any one of the above-mentioned technical solutions or a combination of multiple technical solutions further includes the following steps: when the instruction stream detection module compares the lower 7 bits of the obtained instruction stream with a preset second fixed bit pattern and the comparison result is inconsistent, the instruction stream detection module transmits the exception signal to the exception handling module, so that the instruction stream enters the exception handling process. When the first comparator and the second comparator fail to meet the characteristic conditions after comparison, the instruction stream detection module will determine that the current instruction stream is abnormal, thereby causing it to enter the exception handling process.

[0027] Furthermore, based on any one of the above technical solutions or a combination of multiple technical solutions, the exception handling process includes the following steps:

[0028] The exception handling module enters the exception handling mechanism after discovering an illegal instruction;

[0029] Save register information;

[0030] Jump to the exception handler entry and execute the exception handler;

[0031] If the exception handling fails or there is no response for a long time, the system will restart to reset.

[0032] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, the initialization phase is a phase after the CPU is powered on or reset.

[0033] According to another aspect of the present invention, the present invention provides a computer system, comprising a processor for automatically selecting the RISC-V or X86 instruction set during the initialization phase as described in any one of the above technical solutions or a combination of multiple technical solutions, and the computer system is based on the above processor and executes the above processing method.

[0034] The beneficial effects brought about by the technical solution provided by the present invention are as follows:

[0035] a. The present invention uses an instruction stream detection module to directly analyze instruction stream characteristics during CPU initialization and configure corresponding decoding circuits, avoiding the simulation process. This allows instructions in the initialization phase to be executed natively, which helps improve system performance and ensures a fast and efficient initialization process. It is particularly suitable for scenarios such as cloud computing and embedded systems.

[0036] b. The present invention supports X86 and RISC-V instruction set architectures through a single CPU, eliminating the need for separate hardware for each instruction set architecture, thereby reducing chip power consumption and manufacturing costs and optimizing resource utilization.

[0037] c. Through hardware modular design, the present invention can automatically complete the selection and decoding configuration of the instruction set architecture, simplifying the system architecture. It does not require complex initialization mechanisms or software intervention, which helps reduce design complexity, improves the maintainability and scalability of the system, and shortens the development cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 A schematic diagram of the structure of a processor for automatically selecting a RISC-V or X86 instruction set during the initialization phase, provided as an exemplary embodiment of the present invention;

[0040] Figure 2 A workflow diagram of a processor that automatically selects the RISC-V or X86 instruction set during the initialization phase is provided as an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0043] See also Figure 1 In one embodiment of the present invention, a processor for automatically selecting a RISC-V or X86 instruction set during an initialization phase is provided, comprising an instruction stream detection module, a decoding configuration module, and an exception handling module. The decoding configuration module and the exception handling module are both connected to the instruction stream detection module, wherein the instruction stream comprises a RISC-V instruction sequence and / or an X86 instruction sequence; the instruction stream detection module is configured to extract the instruction stream, detect and analyze it, and then output a corresponding ISA control signal; the decoding configuration module is configured to receive the ISA control signal and connect the corresponding decoding circuit accordingly; in addition, the instruction stream detection module is further configured to extract the instruction stream, detect and analyze it, and then output an exception signal (when the instruction stream does not meet the characteristic conditions of the RISC-V instruction set or the X86 instruction set); the exception handling module is configured to receive the exception signal and perform exception processing on the instruction stream.

[0044] Among them, the ISA control signal includes a first signal and a second signal. When the instruction stream detection module outputs the first signal, it means that the characteristics of the read instruction stream conform to the characteristics of the X86 instruction set; when the instruction stream detection module outputs the second signal, it means that the characteristics of the read instruction stream conform to the characteristics of the RISC-V instruction set.

[0045] Furthermore, the instruction stream detection module includes an instruction register, a value-taking unit, a first comparator and a second comparator. The instruction register is electrically connected to the value-taking unit, the instruction stream is stored in the instruction register, and the value-taking unit is configured to take out the lower 8 bits of the instruction stream; the first comparator and the second comparator are both connected to the value-taking unit, and a first fixed bit pattern is preset in the first comparator, and a second fixed bit pattern is preset in the second comparator. In this embodiment, the first fixed bit pattern is the binary number 11101010, and the second fixed bit pattern is the binary number 1101111.

[0046] The first comparator is configured to compare the lower 8 bits of the instruction stream retrieved by the value retrieval unit with a preset first fixed bit pattern 11101010 and output a comparison result, and the second comparator is configured to compare the lower 7 bits of the instruction stream retrieved by the value retrieval unit with a preset second fixed bit pattern 1101111 and output a comparison result. The features compared by the first comparator and the second comparator include instruction length and opcode mode.

[0047] Furthermore, the decoding configuration module includes a multiplexer, a RISC-V decoding circuit, and an X86 decoding circuit. The multiplexer is selectively electrically connected to the RISC-V decoding circuit or the X86 decoding circuit. The multiplexer is configured to receive the ISA control signal output by the instruction stream detection module and select and connect to the corresponding decoding circuit based on the ISA control signal. Among them, the multiplexer is used to select one of the multiple input signal sources as the output based on the control signal. It includes a control port and an output port. The control port is selectively electrically connected to the first comparator or the second comparator. The control port is configured to receive the ISA control signal; the output port is selectively electrically connected to the RISC-V decoding circuit or the X86 decoding circuit. The output port is configured to connect to the corresponding decoding circuit based on the ISA control signal. The setting of the hardware multiplexer can ensure that the RISC-V decoding circuit and the X86 decoding circuit are quickly switched according to the characteristics of the instruction stream, which is conducive to optimizing system performance.

[0048] When the lower 8 bits of the instruction stream compared by the first comparator are consistent with the preset first fixed bit pattern, the first comparator will output a first signal. At this time, the control port of the multiplexer is electrically connected to the first comparator. The multiplexer will receive the first signal from the first comparator, and in response to the first signal, the output port of the multiplexer will select and connect to the X86 decoding circuit, so that the current instruction stream can be accurately sent to the X86 decoding circuit for subsequent processing. When the lower 8 bits of the instruction stream compared by the first comparator are inconsistent with the preset first fixed bit pattern, the first comparator will transmit the comparison result signal to the second comparator. The second comparator will respond to the comparison result and compare the lower 7 bits of the instruction stream obtained in the value unit with the preset second fixed bit pattern. When the lower 7 bits of the instruction stream compared by the second comparator are consistent with the preset second fixed bit pattern, the control port of the multiplexer will switch to be electrically connected to the second comparator. The multiplexer will receive the second signal from the second comparator and respond to the second signal to select and connect the output port of the multiplexer to the RISC-V decoding circuit, so that the current instruction stream can be accurately sent to the RISC-V decoding circuit for subsequent processing. When the lower 7 bits of the instruction stream compared by the second comparator are inconsistent with the preset second fixed bit pattern, the current instruction stream will be determined to be abnormal, and the second comparator will output an abnormal signal.

[0049] Furthermore, the second comparator is also connected to the exception handling module. After receiving the exception signal output from the second comparator, the exception handling module performs exception processing on the instruction stream, so that the current instruction stream enters the exception handling process.

[0050] like Figure 2 As shown, the present invention also provides a processing method based on the above processor, comprising the following steps:

[0051] During the CPU initialization phase, the instruction stream is stored in the instruction register, and the lower 8 bits of the instruction stream stored in the instruction register are extracted by the value-taking unit in the instruction stream detection module. The initialization phase is the phase after the CPU is powered on or reset. First, the first comparator compares the lower 8 bits of the instruction stream obtained by the value-taking unit with the preset first fixed bit pattern 11101010. When the comparison results are consistent, the first comparator outputs a first signal and is electrically connected to the control port of the multiplexer. After receiving the first signal, the multiplexer controls its output port to select and connect to the X86 decoding circuit to turn on the X86 decoding circuit. The instruction stream accurately enters the X86 decoding circuit and performs subsequent processing.

[0052] Subsequently, if the lower 8 bits of the instruction stream compared by the first comparator are inconsistent with the preset first fixed bit pattern 11101010, the second comparator will be triggered to compare the lower 7 bits of the obtained instruction stream with the preset second fixed bit pattern 1101111. When the comparison result is consistent, the second comparator outputs a second signal to the multiplexer, and the multiplexer will switch to the control port to be electrically connected to the second comparator and control the output port selection and connection to the RISC-V decoding circuit to turn on the RISC-V decoding circuit. The instruction stream accurately enters the RISC-V decoding circuit and performs subsequent processing.

[0053] If the lower 7 bits of the instruction stream compared by the second comparator do not match the preset second fixed bit pattern 1101111, an exception signal is transmitted to the exception handling module. The exception handling module responds to the exception signal and causes the instruction stream to enter the exception handling process. The exception handling process includes: upon detecting an illegal instruction, the exception handling module enters the exception handling mechanism; saves the PC register information; jumps to the exception handling program entry and executes the exception handling program; and if the exception handling fails or remains unresponsive for an extended period, the system is restarted to reset.

[0054] A computer system including a processor as described above for automatically selecting the RISC-V or X86 instruction set during the initialization phase, based on the above processor and executing the above processing method, automatically identifies instruction stream features during the CPU initialization phase and configures corresponding decoding circuits for them, without relying on software simulation or manual intervention. This can greatly improve the flexibility of the system, reduce hardware resource waste, and simplify the initialization process under multi-architecture support.

[0055] The processor of the present invention realizes an efficient mechanism for automatically selecting an X86 decoding circuit or a RISC-V decoding circuit according to the characteristics of the instruction stream during the CPU initialization phase through the collaborative work of the instruction stream detection module and the decoding configuration module. This dynamic configuration method can ensure that instructions are executed in a native manner without the need for translation or simulation, thereby significantly improving initialization efficiency; it enables a single CPU chip to automatically adapt to the corresponding instruction set according to the actual instruction content during initialization, greatly improving the flexibility of the system and reducing the waste of hardware resources.

[0056] Due to the advanced nature of this technical solution, the technology of the present invention is particularly suitable for application in general-purpose processors, server chips, edge computing devices and high-performance embedded systems that support RISC-V and X86 dual instruction sets, and can effectively improve startup efficiency and reduce development complexity.

[0057] In general, compared with existing technologies, this technical solution has significant advantages in performance improvement, resource efficiency and cost reduction, and simplification of heterogeneous CPU design.

[0058] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0059] The above is only a specific implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A processor for automatically selecting RISC-V or X86 instruction set during initialization, characterized in that: The system comprises an instruction stream detection module and a decoding configuration module, wherein the decoding configuration module comprises a multiplexer, a RISC-V decoding circuit and an X86 decoding circuit, wherein the multiplexer is selectively electrically connected to the RISC-V decoding circuit or the X86 decoding circuit; the instruction stream detection module is configured to extract an instruction stream, detect and analyze it, and then output a corresponding ISA control signal, wherein the instruction stream comprises a RISC-V instruction sequence and / or an X86 instruction sequence; and the multiplexer is configured to receive the ISA control signal output by the instruction stream detection module and select and connect to the corresponding decoding circuit according to the ISA control signal. The instruction stream detection module includes an instruction register, a value obtaining unit, a first comparator and a second comparator, the instruction register is electrically connected to the value obtaining unit, the instruction stream is stored in the instruction register, the value obtaining unit is configured to obtain the lower 8 bits of the instruction stream, the first comparator and the second comparator are both connected to the value obtaining unit, the first comparator is configured to compare the lower 8 bits of the instruction stream obtained in the value obtaining unit with a preset first fixed bit pattern and output a comparison result, and the second comparator is configured to compare the lower 7 bits of the instruction stream obtained in the value obtaining unit with a preset second fixed bit pattern and output a comparison result; The ISA control signal includes a first signal and a second signal. When the instruction stream detection module outputs the first signal, the multiplexer selects and connects to the X86 decoding circuit; when the instruction stream detection module outputs the second signal, the multiplexer selects and connects to the RISC-V decoding circuit.

2. The processor according to claim 1, wherein: The multiplexer includes a control port and an output port, the control port is selectively electrically connected to the first comparator or the second comparator, and the control port is configured to receive an ISA control signal; the output port is selectively electrically connected to the RISC-V decoding circuit or the X86 decoding circuit, and the output port is configured to connect the corresponding decoding circuit according to the ISA control signal.

3. The processor according to claim 2, wherein: When the comparison result of the first comparator is consistent, the first comparator outputs the first signal to the multiplexer; when the comparison result of the first comparator is inconsistent, the second comparator responds to the comparison result and compares the lower 7 bits of the instruction stream obtained in the value unit with the preset second fixed bit pattern.

4. The processor according to claim 3, wherein: When the comparison result of the second comparator is consistent, the second comparator outputs the second signal to the multiplexer; otherwise, the second comparator outputs an abnormal signal.

5. The processor according to claim 4, wherein: The system further includes an exception processing module, to which the second comparator is further connected. The exception processing module is configured to receive the exception signal and perform exception processing on the instruction stream. The processor according to claim 1 , wherein: The first fixed bit pattern is stored in a first comparator, and the second fixed bit pattern is stored in a second comparator.

7. A processing method based on the processor according to any one of claims 1 to 6, characterized in that: The steps include: During the CPU initialization phase, the instruction stream is taken out by the instruction stream detection module, and after detection and analysis, the corresponding ISA control signal is output to the multiplexer. After receiving the ISA control signal, the multiplexer selects and connects to the RISC-V decoding circuit or the X86 decoding circuit, so that the instruction stream is sent to the corresponding decoding circuit.

8. The processing method according to claim 7, characterized in that: The method in which the instruction stream detection module extracts the instruction stream, detects and analyzes it, and then outputs the corresponding ISA control signal to the multiplexer is as follows: The instruction stream detection module first compares the lower 8 bits of the obtained instruction stream with a preset first fixed bit pattern, and outputs a first signal if the comparison results are consistent; If the comparison result is inconsistent, the lower 7 bits of the obtained instruction stream are compared with the preset second fixed bit pattern, and if the comparison result is consistent, a second signal is output; Otherwise, an abnormal signal is output.

9. The processing method according to claim 8, characterized in that: The following steps are also included: When the instruction stream detection module compares the lower 7 bits of the obtained instruction stream with the preset second fixed bit pattern and the comparison result is inconsistent, the instruction stream detection module transmits the exception signal to the exception handling module, so that the instruction stream enters the exception handling process.

10. The processing method according to claim 9, characterized in that: The exception handling process includes the following steps: The exception handling module enters the exception handling mechanism after discovering an illegal instruction; Save register information; Jump to the exception handler entry and execute the exception handler; If the exception handling fails or there is no response for a long time, the system will restart to reset.

11. The processing method according to claim 7, characterized in that: The initialization phase is the phase after the CPU is powered on or reset.

12. A computer system, characterized in that: A processor comprising a processor for automatically selecting a RISC-V or X86 instruction set during an initialization phase as described in any one of claims 1 to 6.

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