Formation method of semiconductor structure
By forming a modified layer at the trench fillet corners of the semiconductor device and removing the modified layer, the problem of rounded corners at the bottom of the trench is solved, the conformity of the trench and the quality of the epitaxial layer are improved, and the performance of the semiconductor structure is improved.
Patent Information
- Application Number
- CN202311840254.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-27
- Publication Date
- 2025-06-27
AI Technical Summary
During the etching process of semiconductor devices, the bottom of the trench is prone to problems with the bottom of the trench, resulting in lattice damage, affecting the subsequent growth of the silicon germanium epitaxial layer and carrier mobility, thereby reducing device performance.
The base at the rounded corners of the trench is modified by reactive ion beam etching process to form a modified layer, and the modified layer is removed through the ion beam etching process to correct the rounded corners between the side walls of the trench and the bottom.
By correcting the rounded corners at the bottom of the trench, the conformity of the trench is improved, the quality of the subsequent epitaxial layer is improved, and the performance of the semiconductor structure is improved.
Smart Images
Figure CN120221406A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a method for forming a semiconductor structure. Background Art
[0002] With the continuous improvement of the integration degree of semiconductor devices, the processing line width is getting smaller and smaller, and stable and good device performance poses a huge challenge to the etching process. At present, during the process of etching a semiconductor substrate to form a trench, foot effect defects such as Footing morphology, Taper morphology, or a bottom corner (CornerRounding) morphology combining the two are likely to appear at the bottom of the trench. Using an inductively coupled plasma (ICP) etching process to form a trench can solve the Footing problem and the Taper problem, but cannot solve the bottom corner problem. The bottom corner will cause lattice damage in the trench, affect the epitaxy and dislocation of the subsequent silicon-germanium epitaxial layer growth, reduce the carrier mobility, and seriously affect the performance of the device.
[0003] Therefore, there is an urgent need to provide a method for forming a semiconductor structure that can improve the bottom corner problem during trench etching. Summary of the Invention
[0004] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which effectively improves the corner problem formed between the sidewall and the bottom of the trench, improves the quality of the epitaxial layer subsequently grown in the trench, and improves the performance of the semiconductor structure.
[0005] To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a trench in the substrate, and the included angle formed by the sidewall and the bottom of the trench is a rounded corner; performing a modification treatment on the substrate at the rounded corner using a reactive ion beam etching process to form a modified layer in the substrate at the rounded corner; removing the modified layer using an ion beam etching process.
[0006] Optionally, after the ion beam etching process, the bottom size of the trench increases.
[0007] Optionally, the etching selectivity of the modified layer to the substrate is 2:1 to 10:1.
[0008] Optionally, the reactive gas of the reactive ion beam etching process is oxygen or nitrogen.
[0009] Optionally, the screen grid voltage of the reactive ion beam etching process is 75V to 600V, the ion acceleration bias voltage is 100V to 1200V, the total gas flow rate is 10sccm to 100sccm, and the chamber pressure is 0.1mT to 5mT.
[0010] Optionally, when the substrate at the rounded corner is modified by a reactive ion beam etching process, the angle between the incident direction of the ion beam and the normal of the substrate is 10° to 80°.
[0011] Optionally, the etching gas for the ion beam etching process is one or more of inert gases.
[0012] Optionally, the inert gas includes one or more of Ar, Kr, Xe, Ne, and He.
[0013] Optionally, the screen grid voltage of the ion beam etching process is 50V to 400V, the total gas flow rate is 10 sccm to 100 sccm, and the chamber pressure is 0.1 mT to 5 mT.
[0014] Optionally, the modified layer is removed by an ion beam etching process, and the angle between the incident direction of the ion beam and the normal of the substrate is 10° to 30°.
[0015] Optionally, the aspect ratio of the trench is less than 10:1.
[0016] Optionally, after removing the modified layer, an epitaxial layer is formed in the trench.
[0017] Optionally, after forming the epitaxial layer, the epitaxial layer is etched to form a plurality of discretely arranged fins in the trench.
[0018] Optionally, the material of the epitaxial layer includes germanium silicon and silicon.
[0019] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0020] After etching the substrate to form a trench, the substrate at the rounded corner of the trench is first modified by a reactive ion beam etching process to form a modified layer in the substrate at the rounded corner. The modified layer has a high selectivity ratio with the substrate. Then, by using the ion beam etching process and adjusting the energy, angle, etc. of the ion beam, the modified layer is etched and removed, so that the rounded corner formed between the side wall and the bottom of the trench can be corrected, and a trench with high conformal property can be obtained, which is beneficial to the quality of the subsequent grown epitaxial layer and is beneficial to improving the performance of the finally formed semiconductor structure. Description of the Drawings
[0021] Figure 1 is a schematic structural diagram of the semiconductor formation process in an embodiment;
[0022] Figures 2 to 9 is a schematic structural diagram corresponding to each step of the semiconductor formation process in an embodiment of the present invention. Detailed Embodiments
[0023] Figure 1 is a schematic structural diagram of the semiconductor formation process in one embodiment.
[0024] Referring to Figure 1 , as described in the background art, currently, the angle between the side wall and the bottom of the groove 11 formed by etching the substrate 10 is a rounded corner. A single inductively coupled plasma (ICP) etching process cannot solve the problem of the bottom rounded corner. The bottom rounded corner problem will cause lattice damage, affect the quality of the subsequent epitaxial layer generated, reduce the carrier mobility, and inhibit the performance of the finally formed semiconductor device.
[0025] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including providing a substrate; forming a groove in the substrate, the angle formed by the side wall and the bottom of the groove being a rounded corner; using a reactive ion beam etching process to modify the substrate at the rounded corner to form a modified layer in the substrate at the rounded corner; and then using an ion beam etching process to remove the modified layer. By forming the modified layer through the modification treatment, the etching selectivity between the modified layer and the substrate is improved. When using the ion beam etching process, the modified layer is removed by adjusting the energy and angle of the ion beam, so as to achieve the effect of correcting the bottom rounded corner, expanding the bottom size of the groove, obtaining a groove with high conformal transfer of the mask layer pattern, which is beneficial to improving the quality of the subsequent epitaxial layer formed and improving the performance of the finally formed semiconductor structure.
[0026] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following will describe the specific embodiments of the present invention in detail with reference to the accompanying drawings.
[0027] Figures 2 to 9 is a schematic structural diagram corresponding to each step in the semiconductor formation process in one embodiment of the present invention.
[0028] Referring to Figure 2 , provide a substrate 100.
[0029] In this embodiment, the optional semiconductor substrate 100 includes materials such as silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium.
[0030] After forming the substrate 100, form a groove in the substrate 100, and the bottom surface of the groove has a lattice damage layer.
[0031] The aspect ratio of the groove formed in the substrate 100 is less than 10:1.
[0032] Before forming the groove in the substrate 100, it further includes forming a mask layer on the surface of the substrate 100 and etching the substrate 100 using the mask layer as a mask.
[0033] Optionally, the mask layer can be a multi-layer structure or a hard mask structure.
[0034] When the mask layer is a multi-layer structure, it mainly includes an anti-reflection coating on the substrate 100 and a photoresist layer on the surface of the anti-reflection coating; when the mask layer is a hard mask structure, it mainly includes an oxynitride oxide dielectric layer on the substrate 100, an anti-reflection coating on the oxynitride oxide dielectric layer, and a photoresist layer on the anti-reflection coating.
[0035] Continuing to refer to Figure 2 , in this embodiment, the mask layer is a multi-layer structure, and the mask layer includes an oxide layer 101 on the surface of the substrate 100, a spin-on carbon layer 102 on the surface of the oxide layer 101, a dielectric anti-reflection coating 103 on the surface of the spin-on carbon layer 102, and a photoresist layer 104 on the surface of the dielectric anti-reflection coating 103.
[0036] In this embodiment, the photoresist layer 104 has a pattern, and the pattern is used to define the size and position of the trench to be formed.
[0037] In other embodiments, when the mask layer is a multi-layer structure, the mask layer includes an oxide layer on the surface of the substrate 100, an organic dielectric layer on the surface of the oxide layer, a bottom anti-reflection coating on the surface of the organic dielectric layer, and a photoresist layer on the surface of the bottom anti-reflection coating.
[0038] In other embodiments, when the mask layer is a hard mask structure, the mask layer can also be an oxide layer on the surface of the substrate 100, a silicon nitride layer on the surface of the oxide layer, an organic dielectric layer on the surface of the silicon nitride layer, a bottom anti-reflection coating on the surface of the organic dielectric layer, and a photoresist layer on the surface of the bottom anti-reflection coating; or an oxide layer on the surface of the substrate 100, a silicon nitride layer on the surface of the oxide layer, a tetraethyl orthosilicate layer on the surface of the silicon nitride, a spin-on carbon layer on the surface of the tetraethyl orthosilicate layer, a bottom anti-reflection coating on the surface of the spin-on carbon layer, and a photoresist layer on the surface of the bottom anti-reflection coating; or the mask layer includes a silicon nitride layer on the surface of the substrate 100, an oxide layer on the surface of the silicon nitride, a spin-on carbon layer on the surface of the oxide layer, a dielectric anti-reflection coating on the surface of the spin-on carbon layer, and a photoresist layer on the surface of the dielectric anti-reflection coating.
[0039] Refer to Figure 3 , using the photoresist layer 104 as a mask, etching the dielectric anti-reflection coating 103, spin-on carbon layer 102, oxide layer 101, and substrate 100 in sequence to form a trench 105 in the substrate 100, and removing the photoresist layer 104 and dielectric anti-reflection layer 103.
[0040] In this embodiment, an inductively coupled plasma (ICP) etching process is used to etch the substrate 100 to form a trench 105 in the substrate 100.
[0041] In other embodiments, other dry etching processes or wet etching processes may also be used to etch the substrate 100 to form a trench.
[0042] Optionally, during the process of using the ICP etching process to etch the substrate 100 to form the trench 105, the source power range is 50 W to 1500 W, and the bias electrode power is 100 W to 1500 W; the etching gas uses a mixed gas of a fluorine-based gas and an auxiliary gas. Among them, the fluorine-based gas includes one or more of CF4, CHF3, CH2F2, SF6, NF3, C2F6, C3F8, C2HF5, and the auxiliary gas includes one or more of Ar, N2, O2, He, CH4.
[0043] Optionally, the etching chamber pressure of the ICP etching process is 5 mT to 30 mT, and the total gas flow rate is 5 sccm to 1000 sccm.
[0044] In this embodiment, the source power used during the ICP etching process is 300 W, and the bias electrode power is 500 W; the etching gas uses a combination of fluorine-based gases such as CHF3, SF6, CF4 and auxiliary gases such as Ar, He; the etching chamber pressure is 10 mT, the gas flow rate is 600 sccm, and the reaction temperature is 40 °C.
[0045] In this embodiment, the aspect ratio of the trench 106 formed in the substrate 100 is 1:1.
[0046] In this embodiment, after the trench 105 is formed by etching the substrate 100, the included angle formed by the side wall and the bottom of the trench 105 is a rounded corner.
[0047] Reference Figure 4 and Figure 5 , a reactive ion beam etching process is used to modify the substrate 100 at the rounded corner, and a modified layer 106 is formed in the substrate 100 at the rounded corner.
[0048] Figure 4 The arrow in
[0049] Optionally, when the substrate 100 at the rounded corner is modified by a reactive ion beam etching process, the angle between the incident direction of the ion beam and the normal of the substrate 100 is 10° to 80°. The ion beam has a certain incident angle to achieve the directional oxidation of the substrate 100 at the rounded corner of the trench 105, ensuring that the ions can strike the entire rounded corner at the bottom and side walls of the trench 105, so as to ensure that the modified layer can cover the substrate 100 at the entire bottom rounded corner.
[0050] In this embodiment, the incident angle of the ion beam is 45°. The incident angle is the angle between the incident direction of the ion beam and the normal of the substrate 100, which is more conducive to the ion beam directly hitting the substrate 100 at the bottom rounded corner of the trench 105, and accurately realizing the modification treatment of the substrate 100 at the rounded corner.
[0051] Optionally, the screen grid voltage of the reactive ion beam etching process is 75V to 600V, and the ion acceleration bias voltage is 100ACV to 1200ACV. The greater the screen grid voltage, the greater the impact energy of the ion beam on the target and the higher the etching efficiency. However, if the screen grid voltage is too large, lattice damage will be introduced during the impact process. Therefore, the screen grid voltage is controlled within the range of 75V to 600V; the ion acceleration bias voltage also affects the ion energy. If the ion energy is too high, the depth of the formed modified layer will be too deep. If the ion energy is too low, it cannot ensure that the substrates at the rounded corners are all modified. Therefore, the ion acceleration bias voltage is controlled between 100ACV and 1200ACV.
[0052] In this embodiment, the screen grid voltage used is 200V, and the ion acceleration bias voltage is 500ACV.
[0053] Optionally, the etching chamber pressure range of the reactive ion beam etching process is 0.1mT to 5mT, the total gas flow rate is 10sccm to 100sccm, and the reaction time is 20s to 200s. The etching chamber pressure is related to the mean free path of the ions. A low chamber pressure is beneficial to increasing the mean free path of the molecules, with better directionality, improving the collimation of the ions, and enhancing the modification ability of the ions. In addition, the gas pressure has a great influence on the uniformity, and the uniformity is better at a certain chamber pressure, so that a higher uniformity process modification can be achieved. In addition, the total gas flow rate is related to the reaction rate. Among them, as the total gas flow rate range increases, the reaction rate first rises, reaches the maximum value, and then the reaction rate decreases slightly at a larger flow rate. Therefore, the total gas flow rate cannot be too large or too small; at the same time, the reaction time cannot be too short, otherwise the modified range is too small, and the reaction time cannot be too long, otherwise the modified range will be too large and the modification degree will be too deep.
[0054] In this embodiment, the chamber pressure used during the etching process is 0.5mT, the total gas flow rate is 50sccm, and the etching time is controlled at about 50s.
[0055] In this embodiment, the reaction gas used in the reactive ion beam etching process is oxygen. Oxygen generates oxygen ions in the reactive ion beam etching process, and the oxygen ions perform an oxidation reaction on the substrate 100 at the rounded corners to generate an oxide layer.
[0056] In other embodiments, the reactive ion beam etching process may also use nitrogen to perform a nitriding reaction on the substrate 100 at the rounded corners to generate a nitride layer.
[0057] The purpose of the modification treatment is to increase the etching selectivity between the modified layer 106 and the substrate 100. The etching selectivity between the modified layer 106 and the substrate 100 is 2:1 to 10:1, and the modified layer 106 can be well removed in the subsequent ion beam etching process without damaging the substrate 100.
[0058] In other embodiments, the position and thickness of the formed modified layer can be adjusted by adjusting the relevant process parameters of the reactive ion beam etching. Subsequently, by etching to remove the modified layer, trenches with different bottom shapes can be formed.
[0059] Reference Figure 6 and Figure 7 , the ion beam etching process is used to remove the modified layer 106, and the bottom size of the formed trench 105 increases.
[0060] Figure 6 The arrow in represents the incident direction of the ion beam in the ion beam etching process.
[0061] In this embodiment, after the ion beam etching process is used to remove the modified layer 106, the included angle between the sidewall and the bottom of the trench 105 is close to 90°, which improves the bottom rounding problem, is beneficial to improving the quality of the subsequent epitaxy, greatly reduces epitaxial defects, avoids the fluctuation of the effective height of the fins formed subsequently, improves the performance stability of the device, improves the process window of the device, improves the integration density of the device, and improves the overall electrical performance of the device.
[0062] Optionally, when using the ion beam etching process to remove the modified layer 106, the included angle between the incident direction of the ion beam and the normal of the substrate 100 is 0° to 30°. The ion beam has a certain incident angle to ensure that the striking range of the ion beam covers the modified layer 106.
[0063] In this embodiment, the incident angle of the ion beam is 10°. The incident angle is the included angle between the incident direction of the ion beam and the normal of the substrate 100, which is more conducive to the ion beam directly hitting the modified layer 106 to achieve the removal of the modified layer 106.
[0064] Optionally, the screen grid voltage of the ion beam etching process is 50V to 400V. The greater the screen grid voltage, the greater the impact energy of the ion beam on the target and the higher the etching efficiency. However, if the screen grid voltage is too large, lattice damage will be introduced during the impact process. Therefore, the range of the screen grid voltage is controlled between 50V and 400V.
[0065] In this embodiment, the screen grid voltage used is 200V.
[0066] Optionally, the pressure range of the etching chamber in the ion beam etching process is 0.1mT to 5mT, the total gas flow rate is 10sccm to 100sccm, and the etching time is 20s to 200s. The pressure of the etching chamber is related to the mean free path of ions. A lower chamber pressure is beneficial to increasing the mean free path of molecules, with better directionality, improved ion collimation, and enhanced ion modification ability. Moreover, the gas pressure has a great influence on uniformity, and better uniformity can be achieved at a certain chamber pressure, thus enabling a more uniform process modification. In addition, the total gas flow rate is related to the etching rate. As the total gas flow rate range increases, the etching rate first rises, reaches a maximum value, and then slightly decreases at a larger flow rate. Therefore, the total gas flow rate cannot be too large or too small. At the same time, the etching time cannot be too short, otherwise the etching of the modified layer 106 is not completed, and the etching time cannot be too long either, as this will lead to over-etching.
[0067] In this embodiment, the chamber pressure used during the etching process is 0.5mT, the total gas flow rate is 50sccm, and the etching time is controlled at about 200s.
[0068] The etching gas used in the ion beam etching process is one or more of inert gases, and the inert gases include one or more of Ar, Kr, Xe, Ne, and He.
[0069] In this embodiment, the etching gas used in the ion beam etching process is Ar.
[0070] Reference Figure 8 , after removing the modified layer 106, an epitaxial layer 107 is formed in the trench 105.
[0071] Optionally, the material of the epitaxial layer 107 is germanium silicon, silicon.
[0072] In this embodiment, the material of the epitaxial layer 107 is germanium silicon.
[0073] In this embodiment, the epitaxial layer 107 is formed in the trench 105 by epitaxial growth.
[0074] Reference Figure 9 , after forming the epitaxial layer 107, it further includes etching the epitaxial layer 107 to form a plurality of fin portions 108 arranged discretely.
[0075] In this embodiment, the epitaxial layer 107 is etched by using an ICP etching process.
[0076] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate; Forming a groove in the substrate, where the included angle formed by the side wall and the bottom of the groove is a rounded corner; Performing a modification treatment on the substrate at the rounded corner by using a reactive ion beam etching process to form a modified layer in the substrate at the rounded corner; Removing the modified layer by using an ion beam etching process.
2. The method for forming a semiconductor structure according to claim 1, wherein After the ion beam etching process, the bottom size of the groove increases.
3. The method for forming a semiconductor structure as described in claim 1, wherein The etching selectivity ratio of the modified layer to the substrate is 2:1 to 10:
1.
4. The method for forming a semiconductor structure according to claim 1, wherein, The reactive gas of the reactive ion beam etching process is oxygen or nitrogen.
5. The method for forming a semiconductor structure according to claim 1, wherein, For the reactive ion beam etching process, the screen grid voltage is 75V to 600V, the ion acceleration bias voltage is 100ACV to 1200ACV, the total gas flow rate is 10sccm to 100sccm, and the chamber pressure is 0.1mT to 5mT.
6. The method for forming a semiconductor structure according to claim 1, wherein When performing the modification treatment on the substrate at the rounded corner by using the reactive ion beam etching process, the included angle between the incident direction of the ion beam and the normal of the substrate is 10° to 80°.
7. The method for forming a semiconductor structure according to claim 1, wherein The etching gas of the ion beam etching process uses one or more of inert gases.
8. The method for forming a semiconductor structure according to claim 7, wherein, The inert gases include one or more of Ar, Kr, Xe, Ne, and He.
9. The method for forming a semiconductor structure according to claim 1, wherein, For the ion beam etching process, the screen grid voltage is 50V to 400V, the total gas flow rate is 10sccm to 100sccm, and the chamber pressure is 0.1mT to 5mT.
10. The method for forming a semiconductor structure as described in claim 1, wherein, When removing the modified layer by using the ion beam etching process, the included angle between the incident direction of the ion beam and the normal of the substrate is 0° to 30°.
11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The depth-to-width ratio of the groove is less than 10:
1.
12. The method for forming a semiconductor structure according to claim 1, wherein After removing the modified layer, it further includes forming an epitaxial layer in the groove.
13. The method for forming a semiconductor structure according to claim 12, wherein, After forming the epitaxial layer, it further includes etching the epitaxial layer to form a plurality of fin portions arranged discretely in the groove.
14. The method for forming a semiconductor structure according to claim 12, wherein, The material of the epitaxial layer includes germanium silicon and silicon.