Image sensor, preparation method thereof and electronic equipment

Abstract

The invention provides an image sensor and a preparation method thereof, and electronic equipment, and the image sensor comprises a semiconductor substrate which comprises a plurality of pixel units which are arranged in an array; the interconnection layer is located on the semiconductor substrate; the storage element layer is located on the semiconductor substrate and comprises a plurality of storage units arranged in an array mode, and the storage units correspond to the pixel units; wherein the storage unit comprises a first polar plate structure and a second polar plate structure, the first polar plate structure comprises an accommodating area, and the second polar plate structure is electrically led out through the accommodating area based on an interconnection layer. According to the invention, the storage element layer is arranged in the interconnection layer, and the storage unit corresponds to the pixel unit, so that the arrangement of the storage element can be effectively realized, the compactness of the device layout can be improved, the lead-out mode of another polar plate structure is realized through the interconnection layer based on the design of the accommodating area, and the process design and the implementation mode can be further optimized.

Description

Technical Field

[0001] The present invention belongs to the technical field of image sensor structures and manufacturing technologies, and particularly relates to an image sensor, a manufacturing method thereof, and an electronic device. Background Art

[0002] An image sensor is an important component of a digital camera. According to different components, it can be divided into two categories: CCD (Charge Coupled Device) and CMOS (Complementary Metal-Oxide Semiconductor). With the continuous development of CMOS integrated circuit manufacturing technology, especially CMOS image sensor design and manufacturing technology, CMOS image sensors have gradually replaced CCD image sensors and become the mainstream. CMOS image sensors have advantages such as low voltage, low power consumption, low cost, and high integration, and have important application values in fields such as machine vision, consumer electronics, high-definition monitoring, and medical imaging.

[0003] With the development of image sensors, some storage elements often need to be configured in the pixel circuit. For example, it can be used to receive the charge overflowing from the photoelectric conversion element under high light, can be used to perform quantization of signals for photoelectric conversion under different gains, and can also be used to store part of the implementation of global exposure, etc. However, due to factors such as limited space for device preparation and the complexity of the preparation process caused by performance requirements, it is difficult to obtain effectively configured storage elements and it is difficult to form an effective layout of storage elements in the image sensor.

[0004] Therefore, how to provide an image sensor, a manufacturing method thereof, and an electronic device to solve the problems in the prior art that it is difficult to effectively arrange storage elements in the image sensor and it is difficult to effectively simplify the process, etc.

[0005] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide an image sensor, a manufacturing method thereof, and an electronic device, which are used to solve the problems in the prior art that it is difficult to obtain effectively configured storage elements in the image sensor and it is difficult to form an effective layout of storage elements, etc.

[0007] To achieve the above purpose and other related purposes, the present invention provides an image sensor, including:

[0008] A semiconductor substrate, the semiconductor substrate including a plurality of pixel units arranged in an array;

[0009] An interconnect layer, the interconnect layer being located on the semiconductor substrate;

[0010] A storage element layer, located on the semiconductor substrate, and the storage element layer including a plurality of storage units arranged in an array, the storage units being arranged corresponding to the pixel units; wherein:

[0011] The storage unit includes a first electrode plate structure and a second electrode plate structure, the first electrode plate structure including a receiving area, and the second electrode plate structure being electrically led out through the receiving area and based on the interconnect layer.

[0012] Optionally, the first electrode plate structure includes a receiving opening and a plate body portion surrounding the receiving opening, wherein the receiving opening defines the receiving area, and the first electrode plate structure is electrically led out based on the plate body portion.

[0013] Optionally, the plate body portion includes a capacitance configuration portion and an electrical lead-out portion, the capacitance configuration portion being disposed opposite to the second electrode plate structure, and the electrical lead-out portion extending from a side portion of the second electrode plate structure and the first electrode plate structure being electrically led out based on the electrical lead-out portion.

[0014] Optionally, the storage unit includes a first electrode lead-out structure, there being a first contact area between the first electrode lead-out structure and the first electrode plate structure, and the first electrode plate structure being electrically led out based on the first contact area and through the plate body portion.

[0015] Optionally, when the plate body portion includes the capacitance configuration portion and the electrical lead-out portion, the electrical lead-out portion extends from a side portion of the second electrode plate structure towards the semiconductor substrate to form a position adjustment area.

[0016] Optionally, the storage unit includes a second electrode lead-out structure, there being a second contact area between the second electrode lead-out structure and the second electrode plate structure, and a positive projection of the second contact area on the semiconductor substrate surface being located within a positive projection of the receiving area on the semiconductor substrate surface, so as to electrically lead out the second electrode plate structure based on the second contact area.

[0017] Optionally, the second electrode plate structure includes at least two second electrode plate layers, and each of the second electrode plate layers includes a lead-out area corresponding to the receiving area, and the lead-out areas of the second electrode plate layers are electrically connected through the second electrode lead-out structure.

[0018] Optionally, in each of the lead-out regions corresponding to the accommodation region, there is direct contact between two adjacent lead-out regions or there is an interlayer dielectric layer therebetween.

[0019] Optionally, the first electrode plate structure includes at least two first electrode plate layers corresponding to the second electrode plate layer.

[0020] Optionally, the interconnecting layer includes a transition layer on the semiconductor substrate, the second electrode plate structure includes a bottom second electrode plate layer on the surface of the transition layer, the first electrode plate structure includes a bottom first electrode plate layer on the bottom second electrode plate layer, the bottom first electrode plate layer extends from the surface of the bottom second electrode plate layer towards the transition layer to form a bottom contact portion, and a capacitive dielectric layer is formed between at least the bottom contact portion and the surface of the transition layer.

[0021] Optionally, the first electrode plate structure has an inclined portion disposed on the periphery of the accommodation region.

[0022] Optionally, the manner in which the storage unit and the pixel unit are correspondingly arranged includes that the center of the storage unit and the center of the pixel unit using the storage unit are vertically correspondingly arranged.

[0023] Optionally, the pixel unit has a capacitive connection point, the storage unit has a pixel connection point, the pixel connection point includes electrical lead-out points of the first electrode plate structure and the second electrode plate structure, and the capacitive connection point is electrically connected to the corresponding pixel connection point through the interconnecting layer.

[0024] Optionally, the storage unit includes at least two storage sub-elements, and the arrangement manner of the at least two storage sub-elements includes:

[0025] Each of the storage sub-elements is independently arranged, or there is sharing of the first electrode plate structures of at least two storage sub-elements, or the first electrode plate structures of each storage sub-element are shared and correspondingly include at least two second electrode plate structures, and the shared first electrode plate structure includes accommodation regions corresponding to the number of second electrode plate structures.

[0026] Optionally, the first electrode plate structure further includes a wiring region spaced from the accommodation region, and the interconnecting layer includes a plurality of interconnecting contact posts corresponding to the wiring region to realize electrical connection of devices to be connected.

[0027] Optionally, the interconnecting layer includes a first wiring structure layer, and the first electrode lead-out structure, the second electrode lead-out structure and the interconnecting contact posts all extend to the first wiring structure layer and realize electrical connection through the first wiring structure layer.

[0028] Optionally, the depths of the interconnection contact posts, the first electrode lead-out structure, and the second electrode lead-out structure are all the same.

[0029] Optionally, the storage unit has a symmetry axis in a first direction, and the wiring area and the lead-out area of the first electrode structure are arranged in the first direction. Wherein, when the storage unit includes at least two storage sub-elements, each of the storage sub-elements is arranged in a second direction different from the first direction and is disposed on both sides of the symmetry axis.

[0030] The present invention also provides an electronic device, including the image sensor according to any one of the above solutions.

[0031] The present invention also provides a method for manufacturing the image sensor according to any one of the above solutions. In addition, the above image sensor structure of the present invention can also be manufactured by other methods, wherein:

[0032] The manufacturing method includes the following steps:

[0033] Providing the semiconductor substrate including a plurality of pixel units arranged in an array;

[0034] Manufacturing the interconnection layer and the storage element layer on the semiconductor substrate to obtain the image sensor, wherein the storage element layer is formed during the manufacturing process of the interconnection layer.

[0035] Optionally, manufacturing the interconnection layer and the storage element layer includes the following steps:

[0036] Manufacturing a first interconnection layer on the semiconductor substrate;

[0037] Manufacturing a first electrode structure and a second electrode structure having accommodation areas on the first interconnection layer;

[0038] Manufacturing a second interconnection layer on the first interconnection layer formed with the first electrode structure and the second electrode structure; wherein:

[0039] During the manufacturing process of the second interconnection layer, forming the first electrode lead-out structure, the second electrode lead-out structure, and the interconnection contact posts penetrating the second interconnection layer.

[0040] Optionally, during the manufacturing process of the first electrode structure and the second electrode structure having accommodation areas, the method includes:

[0041] Forming an interlayer dielectric material layer between the first electrode structure and the second electrode structure;

[0042] Etch the interlayer dielectric material layer to obtain a second electrode structure composed of at least two second electrode layers, and there is direct contact between two adjacent second electrode layers;

[0043] Alternatively, based on the interlayer dielectric material layer, obtain a second electrode structure composed of at least two second electrode layers, and there is isolation between two adjacent second electrode layers through the interlayer dielectric material layer.

[0044] As described above, the image sensor, its manufacturing method, and the electronic device of the present invention can improve the compactness of the device layout by arranging the storage element layer in the interconnect layer and corresponding the storage unit to the pixel unit, effectively realize the arrangement of the storage element in the image sensor. Based on the design method of the accommodating area and by the way of leading out the additional electrode structure through the interconnect layer in the existing image sensor, the layout design of the storage element and the leading-out structure can be further optimized, the storage capacity of the storage element can be improved, and the image quality can be optimized. Description of the Drawings

[0045] Figure 1 Shown as a basic structural block diagram of an image sensor system.

[0046] Figure 2 Shown as a schematic diagram of a pixel circuit corresponding to a pixel unit in an image sensor.

[0047] Figure 3 Shown as a flowchart of manufacturing an image sensor according to an embodiment of the present application.

[0048] Figure 4 Shown as a schematic structural diagram of forming a first interconnect layer in manufacturing an image sensor according to an embodiment of the present application.

[0049] Figures 5 - 10 Shown as a schematic diagram of a structure obtained by forming a first electrode structure and a second electrode structure in manufacturing an image sensor according to an embodiment of the present application.

[0050] Figures 11 - 14 Shown as a schematic diagram of forming a second interconnect layer in manufacturing an image sensor according to an embodiment of the present application.

[0051] Figure 15 Shown as a top view of a structure obtained in manufacturing an image sensor according to an embodiment of the present application.

[0052] Figure 16 Shown as a top view of the corresponding structure of a semiconductor substrate and a storage element layer in an embodiment of the present application.

[0053] Figure 17 Shown as a three-dimensional view of the corresponding structure of a semiconductor substrate and a storage element layer in an embodiment of the present application.

[0054] Figure 18 It shows a top view of another structure obtained in the preparation of the image sensor according to the embodiment of the present application.

[0055] Figure 19 It shows a performance comparison diagram of two image sensor structures according to the embodiment of the present application.

[0056] Figure 20 It shows a cross-sectional view of the structure of another image sensor obtained according to the embodiment of the present application.

[0057] Figures 21 - 26 It shows a schematic diagram of another structure obtained by forming the first electrode plate structure and the second electrode plate structure in the preparation of the image sensor according to the embodiment of the present application.

[0058] Figure 27 It shows a cross-sectional view of the structure of another image sensor obtained according to the embodiment of the present application.

[0059] Description of component numbers

[0060] 100 Semiconductor substrate

[0061] 100a Pixel unit

[0062] 200a First interconnection layer

[0063] 200b Second interconnection layer

[0064] 201 First dielectric layer

[0065] 202 First interconnection wiring layer

[0066] 203 Etch stop layer

[0067] 204 Transition layer

[0068] 205 Second dielectric layer

[0069] 206a, 206b, 206c Interconnection contact holes

[0070] 207 Conductive material layer

[0071] 208a Second electrode lead-out structure

[0072] 208b First electrode lead-out structure

[0073] 208c Interconnection contact post

[0074] 209 Second interconnection wiring layer

[0075] 300 Storage element layer

[0076] 300a Storage unit

[0077] The second bottom plate layer of 302

[0078] The first plate structure of 305

[0079] The accommodating opening of 305a

[0080] The main body part of the plate of 305b

[0081] The second upper plate layer of 308

[0082] The second plate structure of 309 Specific implementation manners

[0083] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0084] It should be emphasized that the term "comprising / including" when used herein refers to the presence of features, whole things, steps or components, but does not exclude the presence or addition of one or more other features, whole things, steps or components.

[0085] Features described and / or shown for one implementation manner can be used in the same or similar manner in one or more other implementation manners, combined with features in other implementation manners, or replace features in other implementation manners.

[0086] When detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure will be enlarged locally out of the general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention herein. In addition, in actual production, three-dimensional spatial dimensions of length, width and depth should be included.

[0087] For convenience of description, spatial relationship terms such as "under", "below", "lower than", "beneath", "above", "on" etc. may be used herein to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to encompass other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can also be one or more intervening layers.

[0088] In the context of the present application, the structure in which the described first feature is "above" the second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0089] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and proportion of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0090] The following provides a detailed description of the content proposed by the present invention in conjunction with the respective drawings of the present invention.

[0091] Figure 1 It is shown as a basic structural block diagram of an image sensor system. The image sensor includes a readout circuit and a control circuit connected to a pixel array. Additionally, a functional logic unit is connected to the readout circuit, and the readout circuit and the control circuit are connected to a status register to achieve control of the pixel array. The pixel array includes a plurality of pixels (P1, P2, P3) arranged in rows (R1, R2, R3... Ry) and columns (C1, C2, C3... Cx). The pixel signals output by the pixel array are output to the readout circuit via column lines. In some applications, after the pixels acquire image data, they are read out in a readout mode specified by the status register and then transmitted to the functional logic unit. In a specific implementation, the readout circuit may include an analog-to-digital conversion (ADC) circuit and other circuits.

[0092] In certain applications, the status register may include a programmed selection system for determining whether the readout system exposes and reads through a rolling shutter mode or a global shutter mode. The functional logic unit may store the original image data or the image data after image processing. In some implementations, the readout circuit may read out one row of image data along the readout column lines at a time. Of course, other methods may also be used to read out the image data. The operation of the control circuit can be determined by the current settings of the status register. For example, the control circuit generates a shutter signal for controlling image acquisition. In certain applications, this shutter signal may be a global exposure signal, such that all pixels of the pixel array simultaneously acquire their image data through a single acquisition window. In other applications, this shutter signal may also be a rolling exposure signal, such that the pixels of each pixel row of the pixel array continuously perform exposure reading operations through the acquisition window.

[0093] Figure 2 It is shown as a schematic diagram of a pixel unit in an image sensor. As Figure 2As shown, each pixel unit includes a photoelectric conversion element (e.g., a photodiode) and a pixel circuit (shown as transistors within the dashed box in the figure). The photodiode can be a buried photodiode (PPD) applied in current image sensors. In an application example, the pixel circuit includes a reset transistor (RST), a source follower transistor (SF), and a pixel selection transistor (RS), which are connected to a transfer transistor (TX) and a photodiode as shown in Figure 2 . In an application example of a stacked structure, the pixel circuit includes a reset transistor, a source follower transistor, and a pixel selection transistor disposed on a first circuit chip, and further includes a transfer transistor disposed on a second circuit chip. The photodiode in the second circuit chip is connected to other transistors in the first circuit chip based on the transfer transistor. In a further application example, the pixel circuit may further include a gain control transistor (DCG) connected between a floating diffusion region (FD) and the reset transistor. During operation, the photoelectric conversion element generates photo charges in response to incident light during the exposure process. The transfer transistor connects and transfers a signal, which controls the transfer transistor to transfer the charges accumulated in the photoelectric conversion element to the floating diffusion region. The reset transistor is connected between the power supply voltage and the floating diffusion region, and responds to a reset signal to reset the sensor pixel circuit (e.g., discharge or charge the floating diffusion region and the photodiode to the current voltage). The floating diffusion region is connected to the gate of the source follower transistor. The source follower transistor is connected between the power supply voltage and the pixel selection transistor, responds to the potential of the floating diffusion region and outputs it. The pixel selection transistor connects the source follower transistor and the bit line, and realizes pixel selection readout and outputs it to the readout column in response to a pixel selection control signal.

[0094] However, in existing image sensors, due to factors such as limited space for device fabrication and the complexity of the fabrication process caused by performance requirements, it is difficult to obtain effectively configured storage elements, difficult to form an effective layout of storage elements in the image sensor, and difficult to fabricate storage elements through an effective process, etc., resulting in limited improvement in the image quality formed by the image sensor. The image sensor and its fabrication method of the present application can effectively solve the above problems, and will be described in detail below in combination with specific embodiments.

[0095] Embodiment 1:

[0096] Please refer to Figure 3 As shown, this embodiment provides a fabrication method of an image sensor and its corresponding structure, Figure 3 which is shown as a flowchart of this fabrication method. Among them, this fabrication method includes the following steps:

[0097] S1: Provide a semiconductor substrate including a plurality of pixel units arranged in an array;

[0098] S2: Prepare an interconnection layer and a storage element layer on a semiconductor substrate to obtain an image sensor, wherein the storage element layer is formed during the preparation process of the interconnection layer.

[0099] In this embodiment, the storage element layer is prepared during the preparation process of the interconnection layer of the image sensor. By means of existing processes and structures, the arrangement and preparation of the storage elements can be realized, which can simplify the process and save costs.

[0100] Please refer to Figures 4 - 14 As shown, the steps of preparing the interconnection layer and the storage element layer in this embodiment are as follows:

[0101] First, as Figure 4 shown, prepare a first interconnection layer 200a on the semiconductor substrate.

[0102] Specifically, the semiconductor substrate ( Figure 4 not shown in the figure) can be any structure used to prepare various functional areas of the image sensor in the field of image sensors. Based on the semiconductor substrate, photosensitive elements, various pixel transistors of the CMOS image sensor, and interconnection wiring can be prepared. Among them, the semiconductor substrate can be a structure composed of a single-layer material layer, including but not limited to a silicon substrate. The elements in each area are prepared in the silicon substrate, and its material can be single-crystalline silicon, single-crystalline germanium, polycrystalline silicon, amorphous silicon, or silicon-germanium compound, etc.

[0103] In addition, the semiconductor substrate can also be a stacked structure composed of two or more material layers, and each area is prepared in any required layer thereof. For example, the semiconductor substrate includes a silicon substrate and an epitaxial layer (EPI) formed on the silicon substrate. Photoelectric conversion elements and transistor components (such as including charge transfer elements) are prepared in the epitaxial layer. Further, a back-illuminated image sensor can be prepared based on the above structure. Of course, the semiconductor substrate can also be silicon-on-insulator (SOI), etc. In addition, the semiconductor substrate can also have N-type doped or P-type doped regions to enable the devices prepared therein to meet the functional requirements.

[0104] Specifically, the first interconnection layer 200a can be a part of the structural layer used to realize the electrical connection and lead-out of each transistor in the image sensor and can be a part of the interconnection structure of the existing image sensor. Each structural layer can be prepared by using existing materials and processes.

[0105] In one example, the first interconnect layer 200a includes a first dielectric layer 201 formed on a semiconductor substrate, a first interconnect wiring layer 202 formed in the first dielectric layer 201. Further, the first interconnect layer 200a may also include an etch stop layer 203 formed on the first interconnect wiring layer 202. Among them, the material of the first dielectric layer 201 includes but is not limited to silicon oxide, the material of the etch stop layer 203 includes but is not limited to silicon nitride, and the material of the first interconnect wiring layer 202 includes but is not limited to copper.

[0106] In an alternative example, the first interconnect layer 200a includes a transition layer 204 formed on the first interconnect wiring layer 202. When the etch stop layer 203 is formed, the transition layer 204 is formed on the surface of the etch stop layer 203. Among them, the transition layer 204 can be formed by a thermal oxidation process, and the material can be silicon oxide. Based on the transition layer 204, it is beneficial to prepare the subsequent storage element layer 300.

[0107] Next, as Figures 5 - 10 shown, a first electrode plate structure 305 with a receiving area and a second electrode plate structure 309 are prepared on the first interconnect layer 200a to form a storage element layer 300.

[0108] In this embodiment, the methods for preparing the first electrode plate structure 305 and the second electrode plate structure 309 include:

[0109] As Figure 5 shown, a bottom second electrode plate material layer 301 is prepared on the first interconnect layer 200a. The material of the bottom second electrode plate material layer 301 includes but is not limited to Cu, TIN, and can be formed based on a PVD process; when the transition layer 204 is formed, the bottom second electrode plate material layer 301 is prepared on the surface of the transition layer 204.

[0110] As Figure 6 shown, the bottom second electrode plate material layer 301 is etched to obtain a bottom second electrode plate layer 302;

[0111] As Figure 7 shown, a first interlayer dielectric material layer 303 and a bottom first electrode plate material layer 304 are deposited on the first interconnect layer 200a where the bottom second electrode plate layer 302 is obtained;

[0112] Among them, when the transition layer 204 is formed, the first interlayer dielectric material layer 303 is formed on the surface of the bottom second electrode plate layer 302 and further extends to form on the surface of the transition layer 204, and can be used as an intermediate layer for leading out the first electrode plate structure 305 and a capacitor dielectric layer in the future. The setting of the transition layer 204 can be beneficial to the preparation of the storage element layer and its layout in the device.

[0113] AsFigure 8 As shown, etch the bottom first electrode material layer 304 to obtain the first electrode layer 305. In this embodiment, in the step of preparing the first electrode layer 305, a receiving area for leading out the second electrode structure 309 is formed, which is beneficial to the overall structure design of the capacitor and the flexible design of the leading-out components.

[0114] As Figure 9 shown, deposit the second interlayer dielectric material layer 306 and the upper second electrode material layer 307 on the structure of the obtained first electrode layer 305; the upper second electrode material layer 307 is at least located in the receiving area;

[0115] As Figure 10 shown, etch the upper second electrode material layer 307 to obtain the upper second electrode layer 308.

[0116] So far, the first electrode structure 305 and the second electrode structure 309 are prepared. In this embodiment, the first electrode layer directly constitutes the first electrode structure. It can be understood that, for the sake of simplicity of description, the same reference numeral is used here. In addition, the bottom second electrode layer 302 and the upper second electrode layer 308 constitute the second electrode structure 309 in this embodiment, and can act together as one electrode after forming the storage element.

[0117] In this embodiment, an interlayer dielectric material layer is formed between the first electrode structure 305 and the second electrode structure 309, that is, the first interlayer dielectric material layer 303 and the second interlayer dielectric material layer 306. As the dielectric layer between the electrodes of the storage element (capacitor), the materials of both can be selected as the h-k dielectric layer. In one example, the materials of both can be selected as HfOx, AlO or their stacks. In addition, the materials of the electrode layers of each electrode structure in the storage element include but are not limited to Cu and TIN. Among them, in the second electrode structure 309 formed by at least two second electrode layers obtained, there is an interlayer dielectric material layer separating between adjacent two second electrode layers. That is, in this embodiment, the second electrode structure 309 is composed of the bottom second electrode layer 302 and the upper second electrode layer 308, and the two second electrode layers are separated by the first interlayer dielectric material layer 303 and the second interlayer dielectric material layer 306 to form the storage element.

[0118] Finally, as Figures 11 - 14 shown, prepare the second interconnect layer 200b on the first electrode structure 305 and the second electrode structure 309; during the preparation process of the second interconnect layer 200b, prepare the first electrode lead-out structure 208a, the second electrode lead-out structure 208b and the interconnect contact post 208c penetrating the second interconnect layer 200b to realize the electrical lead-out of the first electrode structure 305 and the second electrode structure 309 and the electrical connection of the device to be connected.

[0119] In this embodiment, the method for preparing the second interconnect layer 200b includes:

[0120] First, as Figure 11 shown, a second dielectric layer 205 is formed on the first interconnect layer 200a having the first electrode structure 305 and the second electrode structure 309. The material of the second dielectric layer 205 includes but is not limited to silicon oxide and can be deposited by PVD or CVD.

[0121] Next, as Figure 12 shown, via holes for interconnecting are formed in the second dielectric layer 205. Figure 12 As shown in [reference], there are three via holes for interconnecting, namely via holes for interconnecting 206a, 206b, and 206c, which can be obtained by a lithography-etching process.

[0122] In one example, the via holes for interconnecting 206a, 206b, and 206c penetrate through the second dielectric layer 205. Further, in this example, the via hole for interconnecting 206b penetrates through the first electrode structure 305 to electrically lead out the first electrode structure 305 subsequently, and the via hole for interconnecting 206a penetrates through the second electrode structure 309 to electrically lead out the second electrode structure 309 subsequently. In addition, in other examples, the depths of the via hole for interconnecting 206b and the via hole for interconnecting 206a can also be in other ways, as long as the electrical connection of the corresponding electrode structure can be achieved based on the filled conductive material. Additionally, due to the existence of the accommodation area, the depth configuration of the via hole for interconnecting 206b and the via hole for interconnecting 206a can be more flexible, and the etching conditions can be selected flexibly.

[0123] In a further example, there is also a via hole for interconnecting 206c. The interconnect layer includes a first wiring structure layer 202. The via hole for interconnecting 206c penetrates through the second dielectric layer 205 and extends to the first wiring structure layer 202 and is electrically connected, so as to achieve the electrical connection or lead-out of the devices in the image sensor based on the first wiring structure layer 202.

[0124] In an alternative example, the via holes for interconnecting 206a, 206b, and 206c all extend to the first wiring structure layer 202. Among them, the via holes for interconnecting 206a, 206b, and 206c can respectively correspond to the first wiring structure blocks 202a, 202b, and 202c in different first wiring structure layers 202. The formed via holes for interconnecting expose the corresponding wiring structure blocks to prevent short circuits between them. The above method can effectively achieve the electrical lead-out of the first electrode structure 305 and the second electrode structure 309, and has less depth limitation on the lead-out structure, and it is not easy to short-circuit between them. In addition, it can be prepared by the same process as the contact post structure in the interconnect layer, simplifying the process.

[0125] Continuing, as Figure 13As shown, a conductive material layer 207 is filled in each of the interconnected contact holes to prepare a first electrode lead-out structure 208b, a second electrode lead-out structure 208a, and an interconnected contact post 208c based on the conductive material layer 207. In this embodiment, the conductive material layer 207 is filled into each of the interconnected contact holes and extends to cover the second dielectric layer 205. The conductive material layer can be prepared based on a PVD process, and the material includes but is not limited to copper.

[0126] Finally, as Figure 14 shown, after the formation of the conductive material layer 207, a CMP process can be used to polish it to obtain an electrical connection structure that fills each of the interconnected contact holes, such as a first electrode lead-out structure 208b, a second electrode lead-out structure 208a, and an interconnected contact post 208c. Further, a second interconnect wiring layer 209 can be prepared on the basis of the formed electrical connection structures. The material of the first interconnect wiring layer 209 includes but is not limited to copper. The second interconnect wiring layer 209 can include a plurality of second wiring structure blocks 209a, 209b, 209c, and each second wiring structure block is electrically connected to the corresponding electrical connection structure to further complete the electrical connection of the structure to be connected. Of course, in other examples, other methods can also be used to prepare the second wiring structure blocks 209a, 209b, 209c and the corresponding first electrode lead-out structure 208b, second electrode lead-out structure 208a, and interconnected contact post 208c, such as forming them into an integral structure.

[0127] So far, a storage element layer and the corresponding electrical lead-out structures are preliminarily formed in the interconnect layer. It should be noted that the first wiring structure layer 202 and the second interconnect wiring layer 209 can be metal wiring layers of different layers in the interconnect layer. For example, an image sensor includes five metal wiring layers, and the first wiring structure layer 202 and the second interconnect wiring layer 209 can be the fourth and fifth layers among them, and the storage element layer is arranged therein.

[0128] Please refer to Figures 14 - 17 shown. Corresponding to the above preparation method, this embodiment provides an image sensor. Among them, the structural settings and material selections in the image sensor can be referred to the descriptions in the method, and similar features will not be elaborated here. Of course, the image sensor in this embodiment can also be prepared by other methods. Among them, the image sensor includes: a semiconductor substrate 100, an interconnect layer, and a storage element layer 300.

[0129] The semiconductor substrate 100 includes a plurality of pixel units 100a arranged in an array. The pixel unit 100a can be any pixel unit in an existing image sensor, including a photoelectric conversion element and the corresponding pixel circuit. Among them, the pixel units 100a arranged in rows and columns can form an M×N pixel array, where both M and N are integers greater than 1. Of course, it can also be a pixel array in which odd rows and even rows are staggered. Figure 16The pixel unit 100a shown in the example is composed of four photoelectric conversion elements sharing.

[0130] The interconnection layer is located on the semiconductor substrate 100 and is used to realize the electrical connection and electrical lead-out of the devices of the image sensor. It can be composed of several dielectric layers, metal layers and several conductive posts CT. The material of the dielectric layer includes but is not limited to silicon oxide, and the materials of the metal layer and the conductive posts include but are not limited to copper, corresponding to the first interconnection layer 200a and the second interconnection layer 200b described in the preparation method.

[0131] The storage element layer 300 includes several storage units 300a arranged in an array, and the storage units 300a correspond to the pixel units 100a. The correspondence means that the storage units 300a are used to realize the functions required in the pixel units 100a. It can be that one storage unit 300a corresponds to one pixel unit 100a, or one storage unit 300a corresponds to at least two pixel units 100a. Of course, in other embodiments, it can also be that one pixel unit 100a corresponds to at least two storage units 300a.

[0132] In one example, the way the storage unit 300a and the pixel unit 100a are arranged corresponding to each other includes that the center of the storage unit is set corresponding to the center of the pixel unit using this storage unit up and down, that is, the storage unit 300a and the pixel unit 100a are set corresponding to each other up and down. In one implementation, the center of the storage unit 300a is aligned with the center of the pixel unit 100a up and down. Further, in a group of pixel units 100a and storage units 300a, the storage unit 300a can be used to realize the use of the corresponding pixel units 100a in the same group. Of course, in other embodiments, sharing or other ways can also be adopted.

[0133] Among them, as Figure 16 shown, in an optional example, four photoelectric conversion elements share to form the pixel unit 100a. The storage units 300a in the storage element layer 300 are arranged in an array. One pixel unit 100a corresponds to one storage unit 300a, and they are set corresponding to each other up and down in position, and their centers are aligned. Based on the corresponding storage unit 300a and pixel unit 100a, it is beneficial to realize the reasonable layout of the device space, and beneficial to realize the optimization of signal transmission and wiring design.

[0134] In addition, as Figure 17As shown, in one example, the pixel unit 100a has a capacitive connection point 208a', and the storage unit 300a has a pixel connection point. The pixel connection point includes electrical lead-out points of a first plate structure and a second plate structure. For example, in the illustration, it is the second plate lead-out structure 208a. The capacitive connection point 208a' is electrically connected to the corresponding pixel connection point through an interconnect layer. Among them, the illustration also shows that there is a metal wiring layer in other interconnect layers between the semiconductor substrate and the storage element layer, and the connection between the pixel and the storage element can be further realized based on the intermediate connection point 208a'' thereon. The design method of this example can facilitate the interconnection based on the corresponding setting of the pixel and the storage unit, can improve the parasitic influence, and can increase the signal-to-noise ratio.

[0135] It should be noted that the storage elements in the storage element unit can be used for signal accumulation, storage, quantization, etc. For example, there may be a conversion gain control element in the pixel unit, and the storage element is used to realize signal quantization at a corresponding gain (such as a lower gain); there may be an overflow path in the pixel unit. During the exposure process, the charge signal generated in the photoelectric conversion element overflows into the corresponding storage element for storing the exposure signal; it can also be in a circuit that improves the dynamic range or solves LED flicker suppression through photoelectric conversion elements with different high and low sensitivities, and is used for storing the signal of the low-sensitivity photoelectric conversion element, so as to adapt to the generation of charge signals for long-term exposure. In addition, it can also be in a global exposure circuit, including a globally transferred charge signal and / or a reset signal. The storage element can be used for temporarily storing the above signals, so as to read out and quantize them from the storage element in subsequent quantization steps.

[0136] Continue to refer to Figure 14 and Figure 15 As shown, the storage unit 300a includes a first plate structure 305 and a second plate structure 309. The first plate structure 305 includes a receiving area. The second plate structure 309 is electrically led out through the receiving area and based on the interconnect layer. The design of the receiving area is conducive to flexible electrical lead-out of the first plate structure 305 and the second plate structure 309, facilitating compact lead-out, so as to form a compact correspondence with the pixel unit, and at the same time facilitating lead-out through the interconnect layer, which is beneficial to alleviating the parasitic capacitance caused by the lead-out structure.

[0137] Such as Figure 14As shown, in this embodiment, the first electrode plate structure 305 includes a receiving opening 305a and an electrode plate main body portion 305b surrounding the receiving opening 305a. The receiving opening 305a defines a receiving area. The first electrode plate structure 305 realizes electrical lead-out based on the electrode plate main body portion 305b, and the second electrode plate structure 309 realizes electrical lead-out through the receiving opening 305a. In this example, the receiving area is formed by defining an opening, so that the receiving area corresponding to the receiving opening is separated from the electrode plate main body portion 305 for electrical lead-out of the first electrode plate structure, enabling flexible design of the depth of the electrical lead-out structure of the second electrode plate structure 309 and process selection.

[0138] In a further example, the electrode plate main body portion 305b includes a capacitance configuration portion and an electrical lead-out portion, which can be seen in Figure 14 At the dotted line in the first electrode plate structure 305 in [reference], the left side is the capacitance configuration portion and the right side is the electrical lead-out portion. Among them, the capacitance configuration portion is disposed opposite to the second electrode plate structure 309, and the electrical lead-out portion extends from the side portion of the second electrode plate structure 309 and realizes the electrical lead-out of the first electrode plate structure 305 based on the electrical lead-out portion.

[0139] In this example, when the electrode plate main body portion 305b includes the capacitance configuration portion and the electrical lead-out portion, the electrode plate main body portion has an electrical lead-out portion extending out of the second electrode plate structure 309, so that the position thereof can be flexibly designed based on the electrical lead-out portion to realize the electrical lead-out of the first electrode plate structure 305. In this example, the electrical lead-out portion extends from the side portion of the second electrode plate structure 309 toward the semiconductor substrate to form a position adjustment area. Through the position adjustment area in this example, the first electrode plate structure can be moved toward the part in the second electrode plate structure that needs to be electrically lead-out connected. For example, Figure 14 As shown, the moving distance of the first electrode plate structure is s, so that the height difference between the first electrode plate structure and the bottom second electrode plate layer is reduced. Among them, to realize the electrical lead-out of the second electrode plate structure, the second electrode lead-out structure 208a needs to be prepared to the bottom second electrode plate layer 302, which is beneficial to the realization of the electrical lead-out of the two electrode plate structures and the design of their manufacturing processes, and is also beneficial to the arrangement of the first interlayer dielectric material layer 303 and the second interlayer dielectric material layer 306 between the electrode plates.

[0140] Continue to refer to Figure 14 As shown, the storage unit includes a first electrode lead-out structure 208b, and the first electrode lead-out structure 208b and the first electrode plate structure 305 have a first contact area 305c to realize the electrical lead-out of the first electrode plate structure 305 based on the first contact area 305c. The first contact area can be an area corresponding to electrical interconnection.

[0141] Continue to refer to Figure 14As shown, the storage unit includes a second electrode lead-out structure 208a. The second electrode lead-out structure 208a has a second contact region 302a with the second plate structure 309, and the orthographic projection of the second contact region 302a on the semiconductor substrate surface is located within the orthographic projection of the accommodation region (accommodation opening 305a) on the semiconductor substrate surface, so as to electrically lead out the second plate structure 309 based on the second contact region 302a. Among them, forming the accommodation opening based on an etching process and forming the second electrode lead-out structure 208a based on an etching filling process are beneficial to accurately define the position of the corresponding second contact region 302a and improve the product yield.

[0142] In an alternative example, for the second plate structure 309, there is an interlayer dielectric layer between two adjacent lead-out portions among the lead-out portions corresponding to the accommodation region. In this example, there are a first interlayer dielectric material layer 303 and a second interlayer dielectric material layer 306. The interlayer dielectric layer exists between the side walls of the first plate structure 305 and the corresponding second plate structure 309, which can further increase the capacitance value and improve the area utilization rate.

[0143] Continue to refer to Figure 14 As shown, in an example, the interconnect layer includes a transition layer 204 located on the semiconductor substrate. The second plate structure 309 includes a bottom second plate layer disposed on the surface of the transition layer, that is, the bottom second plate layer 302. The first plate structure 305 includes a bottom first plate layer located on the bottom second plate layer, and the bottom first plate layer extends from the surface of the bottom second plate layer to the direction of the transition layer 204 to form a bottom contact portion, so as to electrically lead out the first plate structure 305 based on the bottom contact portion. Further, there is also a first interlayer dielectric material layer 303 between the bottom first plate layer and the transition layer 204. The formation of the transition layer 204 can be beneficial to block the mutual influence with the lower material layer, and in addition, it is beneficial to be compatible with the preparation of different material layers based on the transition layer 204, so that different material layers with good performance can be obtained on its upper surface.

[0144] Please refer to Figure 15 As shown, in an example, the storage unit includes at least two storage sub-elements, that is, different plate structures can be used for potential connection to form at least two capacitors. Of course, in other examples, there can also be only one storage sub-element in a storage unit, including a first plate structure and a second plate structure. Among them, the arrangement of the at least two existing storage sub-elements includes:

[0145] Each storage sub-element is independently arranged. For example, taking two storage sub-elements as an example, it includes two independent first electrode plate structures and corresponding two independent second electrode plate structures, which are respectively connected in potential to form two storage sub-elements. Or, the arrangement can also be: there is sharing of the first electrode plate structures of at least two storage sub-elements, that is, for two of the storage sub-elements, the first electrode plate structures are shared and the second electrode plate structures are independently arranged, and two storage sub-elements are formed by applying different voltages to the second electrode plate structures. Of course, in this arrangement, there are also at least two first electrode plate structures that are not shared, that is, the first electrode plate structures in a storage unit are not completely shared and there are spaced areas, and the separation of the storage sub-elements can also be achieved. Or, the arrangement can also be: the first electrode plate structures of each storage sub-element are shared and include at least two second electrode plate structures, so that in this arrangement, the independent division setting of the storage sub-elements is achieved through the second electrode plate structures. Among them, when storing in the shared first electrode plate structure, the first electrode plate structure includes accommodation areas corresponding to the number of second electrode plate structures. Of course, it should be noted that the discrete storage sub-elements can also play the role of the same storage sub-element through potential connection and electrical connection of the contact points. Among them, in Figure 15 In the example shown, the storage unit 300a includes a shared first electrode plate structure 305 and two second electrode plate structures 309. The first electrode plate structure 305 includes two accommodation areas (such as accommodation openings 305a) corresponding to the number of the first electrode plate structure 305 to obtain two storage sub-elements.

[0146] Continue to refer to Figure 15 As shown, in an example, the first electrode plate structure 305 further includes a wiring area 305d spaced from the accommodation area. The interconnection layer includes a plurality of interconnection contact posts 208c, and the interconnection contact posts 208c are arranged corresponding to the wiring area 305d to achieve electrical connection of the devices to be connected. The spaced arrangement can be considered as an opening made in two different first electrode plate structures. In this example, the accommodation area opening is surrounded by the material layer of the first electrode plate structure, and the corresponding opening of the wiring layer is a recessed opening made inward from the edge of the first electrode plate structure.

[0147] In this example, for the storage unit 300a, by effectively arranging each area, such as the accommodation area (accommodation opening 305a) of the first electrode plate structure 305, the area corresponding to the first contact area 305c, the wiring area 305d, etc., it is beneficial to achieve a reasonable layout of the storage unit, and while realizing the electrical connection of the capacitor electrode plates, further realize the arrangement of the interconnection contact posts in the interconnection layer to achieve the electrical connection of the image sensor device.

[0148] In a further example, the depths of the first electrode lead-out structure 208b and the second electrode lead-out structure 208a are the same. Further, the depths of the interconnect contact column 208c, the first electrode lead-out structure 208b, and the second electrode lead-out structure 208a are the same. The same depth can be understood as that the lowest depth in each structure (shown as the depth position close to the first interconnect wiring layer 202 in the figure) can be within a certain fluctuation range. This fluctuation range can be designed according to the actual process, which is beneficial to the preparation of the three structures based on the same process and the realization of the functions of their respective structures. Of course, the depths of the three can be exactly the same and stop at the same depth plane.

[0149] In one example, the interconnect layer includes a first wiring structure layer 202. The first electrode lead-out structure 208b, the second electrode lead-out structure 208a, and the interconnect contact column 208c all extend to the first wiring structure layer 202. Refer to Figure 14 as shown, and the electrical connections of the first electrode lead-out structure 208b, the second electrode lead-out structure 208a, and the interconnect contact column 208c are respectively realized through the first wiring structure layer 202. In this example, all three are connected to the first wiring structure layer 202 and are in contact with the corresponding first wiring blocks 202a, 202b, and 202c, so that the electrical lead-out of the capacitor plate structure of the storage element can be realized based on the process conditions of the interconnect contact column 208c.

[0150] Continue to refer to Figure 15 as shown. In one example, the storage unit has a symmetry axis in the first direction, as shown by the dotted line in the figure. The wiring area and the first contact area 305c are arranged in the first direction and are further symmetrically arranged with respect to the symmetry axis. When the storage unit includes at least two storage sub-elements, each storage sub-element is arranged in a second direction different from the first direction and is disposed on both sides of the symmetry axis. Among them, when there are two shared first plate structures, the corresponding first contact areas 305c are shared, that is, the electrical lead-out of the first plate structure is realized based on the same position. The figure includes a shared first plate structure 305 and two independent second plate structures 309. The second plate structures 309 are distributed on both sides of the symmetry axis and are symmetrically distributed in this example. Among them, the first direction and the second direction are different, and they can be the row direction and the column direction of the pixel array respectively.

[0151] Please refer to Figure 18 and Figure 19 as shown. Figure 18It is shown as a configuration method of a storage sub-element in a storage cell 300a. In this example, there are two first electrode plate structures 305 and four second electrode plate structures 309. The four second electrode plate structures 309 share two first electrode plate structures in pairs, thereby corresponding to four storage sub-elements. For the four storage sub-elements, two first electrode plate structures 305 can be connected to the same potential, and the two second electrode plate structures 309 corresponding to different first electrode plate structures 305 are connected to the same potential, thereby substantially constituting the working mode of two effective storage sub-elements, that is, each first electrode plate structure corresponds to a storage sub-element. Of course, there can also be other application methods, which are set according to actual needs.

[0152] Among them, Figure 19 The curve in Figure 15 compares the Figure 18 capacitance values and readout noises of the storage cells with the Figure 18 layout and the Figure 15 layout as the storage cell size changes. Among them, the abscissa is the change in the storage cell size. The solid line represents the change trend of the capacitance value of the storage element as the storage cell size changes, and the solid line represents the change trend of the readout noise in the pixel unit corresponding to the change in the storage cell size. On the left is the Figure 18 curve obtained from the storage cell layout shown, and on the right is the Figure 15 curve obtained from the storage cell layout shown. During the working process, the potentials applied to the first electrode plate structures in the two layout structures are the same.

[0153] Please refer toFigure 20 As shown, in one example, the second electrode plate structure 309 includes at least two layers of second electrode plate layers 302 and 308, and each second electrode plate layer 302, 308 includes an extraction portion corresponding to the accommodating area. The extraction portions of each second electrode plate layer 302, 308 are electrically connected through the second electrode extraction structure 208a.

[0154] In this example, the first electrode plate structure 305 further includes a first electrode plate layer 310. That is, the first electrode plate structure 309 includes first electrode plate layers corresponding to the number of second electrode plate layers of the second electrode plate structure 309, so that the capacitance value of the storage element can be increased based on the layout design of the present application in a limited space, and the area utilization rate can be improved.

[0155] In addition, please refer to Figure 27 As shown, in one example, the first electrode plate structure 305 has an inclined portion disposed on the periphery of the accommodating area. That is to say, the first electrode plate structure 305 is configured to have a side portion with an inclined structure. In this example, this side portion is formed when forming the accommodating opening 305a. The formation of the inclined portion is beneficial to improving the storage capacity of the storage element. In addition, it is beneficial to the realization of the accommodating opening. For example, in this example, it can be realized through the first interlayer dielectric material layer 303 and the first electrode plate material layer 307 on the bottom second electrode plate layer, so as to facilitate the etching process, and further facilitate the direct contact between the upper second electrode plate layer 308 and the bottom second electrode plate layer 302. Optionally, the acute angle of inclination with respect to the surface of the semiconductor substrate is greater than or equal to 30° and less than 90°, for example, it can be selected as 45°, 60°, 80°, etc.

[0156] Embodiment 2:

[0157] Please refer to Figures 21 - 26 As shown, this embodiment provides another method for manufacturing an image sensor and the corresponding structure. The same parts of this Embodiment 2 and Embodiment 1 can be referred to the description in Embodiment 1. The following mainly introduces the main different parts in the manufacturing method and the obtained structure from Embodiment 1.

[0158] In this Embodiment 2, during the process of manufacturing the first electrode plate structure 305 and the second electrode plate structure 309:

[0159] As Figure 21 shown, after etching the first electrode plate material layer 304 to obtain the first electrode plate layer 305, the first interlayer dielectric material layer 303 is further etched to obtain the first interlayer dielectric layer 303', and the surface of the bottom second electrode plate layer 302 is exposed by the first interlayer dielectric layer 303'.

[0160] As Figure 22As shown, a second interlayer dielectric material layer 306 is prepared on the structure formed with the first electrode plate layer 305 and the first interlayer dielectric layer 303', and the second interlayer dielectric material layer 306 is in contact with the exposed surface of the second electrode plate layer 302;

[0161] As Figure 23 shown, the second interlayer dielectric material layer 306 is etched to obtain the second interlayer dielectric layer 306', and the second interlayer dielectric layer 306' exposes the surface of the underlying second electrode plate layer 302;

[0162] As Figure 24 shown, an upper second electrode plate material layer 307 is deposited on the structure with the exposed surface of the second electrode plate layer 302;

[0163] As Figure 25 shown, the upper second electrode plate material layer 307 is etched to obtain the upper second electrode plate layer 308.

[0164] As Figure 26 shown, a second interconnection layer 200b is further prepared to obtain an image sensor.

[0165] In this embodiment, for the second electrode plate structure 309, the underlying second electrode plate layer 302 is in direct contact with the upper second electrode plate layer 308, and there is direct contact between two adjacent lead-out regions in the lead-out regions of each second electrode plate structure corresponding to the accommodating region, so that the device preparation can be simplified, which is beneficial to the connection of capacitance signals and the layout optimization.

[0166] Embodiment Three:

[0167] The present invention further provides an electronic device, including the image sensor described in any one of the solutions of Embodiment One and Embodiment Two above. The electronic device can be a security monitoring device, a vehicle-mounted electronic device, a mobile phone camera, a machine vision device, etc. Based on the image sensor of the present invention, high-quality image information can be acquired.

[0168] In summary, by arranging the storage element layer in the interconnection layer and corresponding the storage unit to the pixel unit, the present invention can improve the compactness of the device layout, effectively realize the arrangement of the storage element in the image sensor. Based on the design method of the accommodating region and by the way of realizing the lead-out of the additional electrode plate structure through the interconnection layer in the existing image sensor, the layout design of the storage element and the lead-out structure can be further optimized, the storage capacity of the storage element can be improved, and the image quality can be optimized. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0169] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. All equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An image sensor, characterized in that, The image sensor includes: a semiconductor substrate including a plurality of pixel units arranged in an array; an interconnect layer located on the semiconductor substrate; a storage element layer located on the semiconductor substrate, and the storage element layer includes a plurality of storage units arranged in an array, and the storage units correspond to the pixel units; wherein: the storage unit includes a first plate structure and a second plate structure, the first plate structure includes an accommodation area, and the second plate structure is electrically led out through the accommodation area and based on the interconnect layer.

2. The image sensor according to claim 1, wherein The first plate structure includes an accommodation opening and a plate main body portion surrounding the accommodation opening. Wherein, the accommodation opening defines the accommodation area, and the first plate structure is electrically led out based on the plate main body portion.

3. The image sensor according to claim 2, characterized in that, The plate main body portion includes a capacitor configuration portion and an electrical lead-out portion. The capacitor configuration portion is disposed opposite to the second plate structure, and the electrical lead-out portion extends from a side portion of the second plate structure and the first plate structure is electrically led out based on the electrical lead-out portion; and / or, the storage unit includes a first electrode lead-out structure, and there is a first contact area between the first electrode lead-out structure and the first plate structure, and the first plate structure is electrically led out based on the first contact area and through the plate main body portion.

4. The image sensor according to claim 3, wherein, When the plate main body portion includes the capacitor configuration portion and the electrical lead-out portion, the electrical lead-out portion extends from a side portion of the second plate structure towards the semiconductor substrate to form a position adjustment area.

5. The image sensor according to claim 1, characterized in that, The storage unit includes a second electrode lead-out structure, and there is a second contact area between the second electrode lead-out structure and the second plate structure. A positive projection of the second contact area on the semiconductor substrate surface is located within a positive projection of the accommodation area on the semiconductor substrate surface, so as to electrically lead out the second plate structure based on the second contact area.

6. The image sensor according to claim 5, wherein The second plate structure includes at least two second plate layers, and each of the second plate layers includes a lead-out area corresponding to the accommodation area, and the lead-out areas of each of the second plate layers are electrically connected through the second electrode lead-out structure.

7. The image sensor according to claim 6, wherein There is direct contact or an interlayer dielectric layer between two adjacent ones of the lead-out areas corresponding to the accommodation area; and / or, the first plate structure includes at least two first plate layers corresponding to at least two second plate layers.

8. The image sensor according to claim 1, characterized in that, The interconnect layer includes a transition layer located on the semiconductor substrate. The second plate structure includes a bottom second plate layer located on the surface of the transition layer. The first plate structure includes a bottom first plate layer located on the bottom second plate layer. The bottom first plate layer extends from the surface of the bottom second plate layer towards the transition layer to form a bottom contact portion, and a capacitor dielectric layer is formed between at least the bottom contact portion and the surface of the transition layer; and / or, the first plate structure has an inclined portion, and the inclined portion is arranged on the periphery of the accommodation area.

9. The image sensor according to claim 1, wherein The manner in which the storage unit is arranged corresponding to the pixel unit includes that the center of the storage unit is vertically corresponding to the center of the pixel unit using the storage unit; and / or, the pixel unit has a capacitive connection point, the storage unit has a pixel connection point, the pixel connection point includes electrical lead-out points of the first electrode plate structure and the second electrode plate structure, and the capacitive connection point is electrically connected to the corresponding pixel connection point through the interconnect layer.

10. The image sensor according to claim 1, wherein The storage unit includes at least two storage sub-elements, and the arrangement manner of the at least two storage sub-elements includes: Each of the storage sub-elements is independently arranged, or, there is sharing of the first electrode plate structures of at least two storage sub-elements, or, the first electrode plate structures of each storage sub-element are shared and correspondingly include at least two second electrode plate structures, and the shared first electrode plate structure includes accommodation areas corresponding to the number of second electrode plate structures.

11. The image sensor according to any one of claims 1 to 10, characterized in that, The first electrode plate structure further includes a wiring area spaced from the accommodation area, and the interconnect layer includes a plurality of interconnect contact posts, and the interconnect contact posts are arranged corresponding to the wiring area to achieve electrical connection of devices to be connected.

12. The image sensor according to claim 11, wherein, The interconnect layer includes a first wiring structure layer, and the first electrode lead-out structure, the second electrode lead-out structure and the interconnect contact posts all extend to the first wiring structure layer; and / or, the depths of the interconnect contact posts, the first electrode lead-out structure and the second electrode lead-out structure are all the same.

13. The image sensor according to claim 11, wherein The storage unit has a symmetry axis in the first direction, and the wiring area and the lead-out area of the first electrode plate structure are arranged in the first direction. Wherein, when the storage unit includes at least two storage sub-elements, each of the storage sub-elements is arranged in a second direction different from the first direction and is disposed on both sides of the symmetry axis.

14. An electronic device, characterized in that, The electronic device includes the image sensor according to any one of claims 1-13.

15. A method for manufacturing an image sensor according to any one of claims 1-13, characterized in that, The preparation method includes the following steps: Providing the semiconductor substrate including a plurality of pixel units arranged in an array; Preparing the interconnect layer and the storage element layer on the semiconductor substrate to obtain the image sensor, wherein the storage element layer is formed during the preparation process of the interconnect layer.

16. The method for manufacturing an image sensor according to claim 15, wherein, Preparing the interconnect layer and the storage element layer includes the following steps: Preparing a first interconnect layer on the semiconductor substrate; Preparing a first electrode plate structure and a second electrode plate structure having accommodation areas on the first interconnect layer; Preparing a second interconnect layer on the first interconnect layer formed with the first electrode plate structure and the second electrode plate structure; wherein: During the preparation of the second interconnect layer, the first electrode lead-out structure, the second electrode lead-out structure and the interconnect contact posts penetrating the second interconnect layer are formed.

17. The method for manufacturing an image sensor according to claim 16, characterized in that, During the process of preparing the first electrode plate structure and the second electrode plate structure having accommodation areas, the method includes: Forming an interlayer dielectric material layer between the first electrode plate structure and the second electrode plate structure; Etching the interlayer dielectric material layer to obtain a second electrode plate structure composed of at least two second electrode plate layers, and there is direct contact between adjacent two of the second electrode plate layers; Alternatively, based on the interlayer dielectric material layer, a second electrode plate structure composed of at least two second electrode plate layers is obtained, and there is isolation between two adjacent second electrode plate layers through the interlayer dielectric material layer.

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