Adaptive line spectrum enhancer based on neural network

Abstract

A method for reducing noise using a neural network-based adaptive line spectrum enhancer includes receiving an input signal including a narrowband signal and noise. The narrow signal and the noise are decorrelated via an artificial neural network. The artificial neural network generates an estimate of the narrowband signal. The noise in the input signal is reduced based on the estimated narrowband signal.

Description

Technical Field

[0001] Aspects of the present disclosure generally relate to adaptive noise cancellation using artificial neural networks. Background Art

[0002] Noise cancellation is a subject of increasing interest, given its wide application in communications and image signaling. Techniques for noise cancellation have been applied to hands-free telephony, echo cancellation, speech enhancement, medical imaging, and power delivery.

[0003] Adaptive noise cancellation systems can suppress noise and enhance audio signal quality. Some conventional methods use adaptive filters that automatically adjust parameters to suppress or remove noise from an input signal. The reference input can be derived from a single or multiple sensors at points where the signal is weak or undetectable in the noise field. The adaptive filter determines the input signal and reduces the noise level in the system output. However, using such adaptive filters can result in a significant increase in computational cost.

[0004] Adaptive line spectrum enhancers have also been used to provide noise cancellation and enhanced audio signal quality. An adaptive line spectrum enhancer (ALE) is an adaptive self-tuning filter that separates the periodic and random components in a signal. The ALE can detect low-level sine waves in the noise and can be applied to speech in a noisy environment. A finite impulse response (FIR) filter uses adaptive weights to form an FIR-based ALE for improved stability. However, the FIR-ALE can be directly affected by in-band radio frequency (RF) interference (e.g., in-band RF interference affected by non-linearity) that cannot be eliminated by the FIR-ALE. Thus, such in-band RF interference (such as in-band RF interference affected by non-linearity) can degrade performance. Summary of the Invention

[0005] The present disclosure is set forth in the independent claims. Some aspects of the present disclosure are described in the dependent claims.

[0006] In one aspect of the present disclosure, a processor-implemented method includes: receiving an input signal that includes a combined wideband signal and noise. The processor-implemented method further includes: decorrelating the input signal via an artificial neural network based on a delay. The processor-implemented method still further includes: generating an estimate of the wideband signal and a noise estimate based on the decorrelated input via the artificial neural network. The processor-implemented method also includes: reducing the noise in the input signal based at least in part on the noise estimate.

[0007] Another aspect of the present disclosure relates to an apparatus, comprising: components for receiving an input signal including a combined broadband signal and noise. The apparatus further comprises: components for decorrelating the input signal based on a delay via an artificial neural network. The apparatus still further comprises: components for generating an estimate of the broadband signal and a noise estimate based on the decorrelated input via the artificial neural network. The apparatus also comprises: components for reducing the noise in the input signal based at least in part on the noise estimate.

[0008] In another aspect of the present disclosure, a non-transitory computer-readable medium having non-transitory program code recorded thereon is disclosed. The program code is executed by a processor and comprises program code for receiving an input signal including a combined broadband signal and noise. The program code further comprises: program code for decorrelating the input signal based on a delay via an artificial neural network. The program code still further comprises: program code for generating an estimate of the broadband signal and a noise estimate based on the decorrelated input via the artificial neural network. The program code also comprises: program code for reducing the noise in the input signal based at least in part on the noise estimate.

[0009] Another aspect of the present disclosure relates to an apparatus having a memory and one or more processors coupled to the memory. The processor is configured to receive an input signal including a combined broadband signal and noise. The processor is further configured to decorrelate the input signal based on a delay via an artificial neural network. The processor is still further configured to generate an estimate of the broadband signal and a noise estimate based on the decorrelated input via the artificial neural network. The processor is also configured to reduce the noise in the input signal based at least in part on the noise estimate.

[0010] Additional features and advantages of the present disclosure will be described below. Those skilled in the art should understand that the present disclosure can be easily used as a basis for modifying or designing other structures for implementing the same purpose as the present disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the teachings of the present disclosure set forth in the appended claims. The novel features, which are considered to be characteristics of the present disclosure, will be better understood in terms of their organization and method of operation, together with further objects and advantages, when considered in conjunction with the following description taken in connection with the accompanying drawings. However, it should be clearly understood that each drawing is provided for the purpose of illustration and description only and is not intended as a definition of the limitation of the present disclosure. Description of the Drawings

[0011] The features, essences, and advantages of the present disclosure will become more apparent when the following specific embodiments are understood in conjunction with the accompanying drawings, in which like reference numerals are always correspondingly identified.

[0012] Figure 1An example implementation of a neural network using a system on a chip (SoC) including a general purpose processor in accordance with certain aspects of the present disclosure is illustrated.

[0013] Figure 2A , Figure 2B and Figure 2C is a diagram illustrating a neural network according to aspects of the present disclosure.

[0014] Figure 2D is a diagram illustrating an exemplary deep convolutional network (DCN) according to aspects of the present disclosure.

[0015] Figure 3 is a block diagram illustrating an exemplary deep convolutional network (DCN) according to aspects of the present disclosure.

[0016] Figure 4 is a block diagram illustrating an exemplary software architecture that can modularize artificial intelligence (AI) functionality.

[0017] Figure 5 is a block diagram illustrating an example neural network-based adaptive line spectrum enhancer in accordance with aspects of the present disclosure.

[0018] Figure 6 An expanded block diagram illustrating an example system for noise reduction using an artificial neural network in accordance with aspects of the present disclosure.

[0019] Figure 7 is a flow chart illustrating a method for noise reduction using an adaptive line spectrum enhancer based on an artificial neural network according to aspects of the present disclosure. DETAILED DESCRIPTION

[0020] The specific embodiments described below in conjunction with the accompanying drawings are intended as descriptions of various configurations and are not intended to represent the only configurations in which the described concepts can be practiced. In order to provide a comprehensive understanding of the various concepts, the specific embodiments include specific details. However, it is obvious to those skilled in the art that these concepts can be practiced without these specific details. In some instances, in order to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0021] Based on the teachings, those skilled in the art should recognize that the scope of the present disclosure is intended to cover any aspect of the present disclosure, whether implemented independently of any other aspect of the present disclosure or in combination with any other aspect. For example, a device can be implemented or a method can be practiced using any number of the aspects set forth. In addition, the scope of the present disclosure is intended to cover such devices or methods practiced using other structures, functionalities, or a combination of structures and functionalities that supplement or are different from the various aspects of the present disclosure set forth. It should be understood that any aspect of the present disclosure disclosed can be embodied by one or more elements of a claim.

[0022] The term "exemplary" is used to mean "serving as an example, instance, or illustration". Any aspect described as "exemplary" need not be construed as superior or better than other aspects.

[0023] Although specific aspects have been described, numerous variations and permutations of these aspects fall within the scope of the present disclosure. Although some benefits and advantages of the preferred aspects have been mentioned, the scope of the present disclosure is not intended to be limited to specific benefits, uses, or purposes. Instead, the aspects of the present disclosure are intended to be widely applicable to different technologies, system configurations, networks, and protocols, some of which are illustrated by way of example in the figures and the following description of the preferred aspects. The detailed description and the figures are merely illustrative of the present disclosure and not limiting, and the scope of the present disclosure is defined by the appended claims and their equivalents.

[0024] Adaptive line enhancers (ALEs) are widely used in communication, medical, and acoustic applications where narrowband signal components within broadband noise can be extracted. Broadband digital signal processing systems can be vulnerable to narrowband radio frequency (RF) interference. Analog front end (AFE) filter circuits can suppress out-of-band RF interference; however, broadband systems can be directly affected by in-band RF interference that cannot be eliminated by conventional filters (e.g., FIR-ALE). In-band RF interference degrades performance (e.g., lower audio quality, increased bit error rate, blurred images), and its bursty nature can cause immediate system failures.

[0025] Conventional techniques for adaptive noise cancellation employ a finite impulse response (FIR)-based adaptive line enhancer (ALE). The FIR-based ALE is a tracking system that detects and extracts narrowband interference from a broadband source by exploiting the time-domain correlation difference between the narrowband interference y(t) and the broadband source v(t). Digital estimates y'(n) and v'(n) of the individual narrowband and broadband signals can be generated from the ALE. However, narrowband signals are typically captured using an analog front-end (AFE) circuit. The AFE circuit can include circuits such as mixers, variable gain amplifiers, and analog-to-digital converters, and these AFE circuits introduce nonlinear distortion before adding broadband noise. Due to the linear nature of FIR, the FIR-based ALE cannot directly overcome the nonlinear impairments of the AFE. Thus, the signals distorted by the nonlinear distortion can degrade the estimation performance of the ALE.

[0026] To address these and other challenges, aspects of the present disclosure relate to a neural network-based ALE to improve and in some aspects significantly improve noise cancellation performance. Thus, aspects of the present invention can be beneficially applied to in-band RF interference cancellation for communication systems and medical diagnostics (such as electrocardiography), as well as echo cancellation and active noise control devices.

[0027] Figure 1 An example embodiment of an illustrative system-on-chip (SOC) 100 is shown, which may include a central processing unit (CPU) 102 or a multi-core CPU configured to perform noise reduction using a neural network-based ALE. Variables (e.g., neural signals and synaptic weights), system parameters associated with the computing device (e.g., a neural network with weights), latencies, frequency slot information, and task information may be stored in a storage block associated with the neural processing unit (NPU) 108, a storage block associated with the CPU 102, a storage block associated with the graphics processing unit (GPU) 104, a storage block associated with the digital signal processor (DSP) 106, storage block 118, or may be distributed across multiple blocks. Instructions executed at the CPU 102 may be loaded from a program memory associated with the CPU 102 or from storage block 118.

[0028] SoC 100 may also include additional processing blocks customized for specific functions, such as GPU 104, DSP 106, connection block 110 (which may include fifth-generation (5G) connection, fourth-generation long-term evolution (4G LTE) connection, Wi-Fi connection, USB connection, Bluetooth connection, etc.), and a multimedia processor 112 that can detect and recognize gestures, for example. In a specific implementation, NPU 108 is implemented in CPU 102, DSP 106, and / or GPU 104. SoC 100 may also include a sensor processor 114, an image signal processor (ISP) 116, and / or a navigation module 120 (which may include a global positioning system).

[0029] SoC 100 may be based on the ARM instruction set. In one aspect of the present disclosure, the instructions loaded into the general-purpose processor 102 may include code for receiving an input signal that includes a combined broadband signal and noise. The general-purpose processor 102 may also include code for decorrelating the input signal based on latency via an artificial neural network. The general-purpose processor 102 may also include code for generating an estimate of the broadband signal and an estimate of the noise based on the decorrelated input via an artificial neural network. The general-purpose processor 102 may also include code for reducing the noise in the input signal based at least in part on the noise estimate.

[0030] Deep learning architectures can perform object recognition tasks by learning to represent the input at successive higher levels of abstraction in each layer, thus constructing a useful feature representation of the input data. In this way, deep learning addresses the main bottleneck of traditional machine learning. Before the advent of deep learning, machine learning methods for object recognition problems may have relied heavily on features designed by humans and may have been combined with shallow classifiers. A shallow classifier can be a two-class linear classifier, for example, where the weighted sum of the feature vector components can be compared with a threshold to predict which class the input belongs to. Features designed by humans can be templates or kernels customized by engineers with domain expertise for a specific problem domain. In contrast, while deep learning architectures can learn to represent features similar to those that human engineers might design, they require training. Additionally, deep networks can learn to represent and recognize new types of features that humans may not have considered yet.

[0031] Deep learning architectures can learn hierarchical structures of features. For example, if presented with visual data, the first layer can learn to recognize relatively simple features in the input stream, such as edges. In another example, if presented with auditory data, the first layer can learn to recognize spectral power in specific frequencies. The second layer takes the output of the first layer as input and can learn to recognize combinations of features, such as simple shapes in visual data or combinations of sounds in auditory data. For example, higher layers can learn to represent complex shapes in visual data or words in auditory data. Even higher layers can learn to recognize common visual objects or spoken phrases.

[0032] Deep learning architectures can perform particularly well when applied to problems with a natural hierarchy. For example, the classification of motorized vehicles can benefit from first learning to recognize wheels, windshields, and other features. These features can be combined in different ways at higher levels to recognize cars, trucks, and airplanes.

[0033] Neural networks can be designed with various connection patterns. In a feedforward network, information flows from lower layers to higher layers, where each neuron in a given layer communicates with neurons in the higher layer. As described above, hierarchical representations can be built in successive layers of a feedforward network. Neural networks can also have recurrent or feedback (also known as top-down) connections. In recurrent connections, the output from a neuron in a given layer can be communicated to another neuron in the same layer. Recurrent architectures can help identify patterns that span more than one block of input data presented sequentially to the neural network. Connections from neurons in a given layer to neurons in lower layers are called feedback (or top-down) connections. Networks with many feedback connections can be helpful when the recognition of high-level concepts can assist in discerning specific low-level features of the input.

[0034] The connections between the layers of a neural network can be fully connected or locally connected. Figure 2A An example of a fully connected neural network 202 is illustrated. In the fully connected neural network 202, the neurons in the first layer can convey their outputs to each neuron in the second layer, such that each neuron in the second layer will receive inputs from every neuron in the first layer. Figure 2BAn example of a locally connected neural network 204 is illustrated. In a locally connected neural network 204, neurons in the first layer can be connected to a limited number of neurons in the second layer. More generally, the locally connected layer of the locally connected neural network 204 can be configured such that each neuron in the layer will have the same or a similar connection pattern, but the connection strengths can have different values (e.g., 210, 212, 214, and 216). The locally connected connection pattern may result in spatially distinct receptive fields in higher layers, because neurons in higher layers in a given region can receive input that is tuned through training to the attributes of a restricted portion of the network's total input.

[0035] An example of a locally connected neural network is a convolutional neural network. Figure 2C An example of a convolutional neural network 206 is illustrated. The convolutional neural network 206 can be configured such that the connection strengths associated with the input to each neuron in the second layer are shared (e.g., 208). Convolutional neural networks can be well-suited for problems where the spatial location of the input is meaningful.

[0036] One type of convolutional neural network is a deep convolutional network (DCN). Figure 2D A detailed example of a DCN 200 designed to recognize visual features from an image 226 input from an image capture device 230 (such as an in-vehicle camera) is illustrated. The DCN 200 of the current example can be trained to identify traffic signs and the numbers provided on traffic signs. Of course, the DCN 200 can be trained for other tasks, such as identifying lane markings or identifying traffic signals.

[0037] The DCN 200 can be trained through supervised learning. During training, an image (such as an image 226 of a speed limit sign) can be presented to the DCN 200, and then a forward pass can be computed to produce an output 222. The DCN 200 can include a feature extraction part and a classification part. When receiving the image 226, the convolutional layer 232 can apply a convolutional kernel (not shown) to the image 226 to generate a first set of feature maps 218. As an example, the convolutional kernel of the convolutional layer 232 can be a 5x5 kernel that generates 28x28 feature maps. In this example, since four different feature maps are generated in the first set of feature maps 218, four different convolutional kernels are applied to the image 226 at the convolutional layer 232. The convolutional kernel can also be referred to as a filter or a convolutional filter.

[0038] The first set of feature maps 218 can be subsampled by a max pooling layer (not shown) to generate a second set of feature maps 220. The max pooling layer reduces the size of the first set of feature maps 218. That is, the size of the second set of feature maps 220 (such as 14x14) is smaller than the size of the first set of feature maps 218 (such as 28x28). The reduced size provides similar information to subsequent layers while reducing memory consumption. The second set of feature maps 220 can be further convolved via one or more subsequent convolutional layers (not shown) to generate one or more sets of subsequent feature maps (not shown).

[0039] In Figure 2D the example, the second set of feature maps 220 is convolved to generate a first feature vector 224. Additionally, the first feature vector 224 is further convolved to generate a second feature vector 228. Each feature of the second feature vector 228 can include numbers corresponding to possible features of the image 226, such as "logo", "60", and "100". A softmax function (not shown) can convert the numbers in the second feature vector 228 into probabilities. Thus, the output 222 of the DCN 200 is the probability that the image 226 includes one or more features.

[0040] In this example, the probabilities of "logo" and "60" in the output 222 are higher than the probabilities of other numbers (such as "30", "40", "50", "70", "80", "90", and "100") in the output 222. Before training, the output 222 produced by the DCN 200 may be incorrect. Thus, the error between the output 222 and the target output can be calculated. The target output is the ground truth of the image 226 (e.g., "logo" and "60"). Then the weights of the DCN 200 can be adjusted such that the output 222 of the DCN 200 is closer to the target output.

[0041] To adjust the weights, a learning algorithm can calculate the gradient vector of the weights. The gradient can indicate the amount by which the error will increase or decrease if the weights are adjusted. At the top layer, the gradient can directly correspond to the value of the weight connecting the activated neuron in the penultimate layer and the neuron in the output layer. In the lower layers, the gradient can depend on the value of the weights and the error gradient calculated in the higher layers. The weights can then be adjusted to reduce the error. This way of adjusting the weights can be referred to as "backpropagation" because it involves a "backward pass" through the neural network.

[0042] In practice, the error gradient of the weights can be calculated over a small number of examples, such that the calculated gradient is close to the true error gradient. This approximation method can be referred to as stochastic gradient descent. Stochastic gradient descent can be repeated until the achievable error rate of the entire system stops decreasing or until the error rate reaches a target level. After learning, new images can be presented to the DCN, and the output 222 that can be considered as the inference or prediction of the DCN can be produced through the forward pass of the network.

[0043] A deep belief network (DBN) is a probabilistic model that includes multiple layers of hidden nodes. A DBN can be used to extract hierarchical representations of a training data set. A DBN can be obtained by stacking layers of restricted Boltzmann machines (RBMs). An RBM is a type of artificial neural network that can learn a probability distribution through a set of inputs. Since an RBM can learn a probability distribution without information about the class to which each input should be classified, an RBM is typically used for unsupervised learning. Using a hybrid paradigm of supervised and unsupervised, the bottom RBM of the DBN can be trained in an unsupervised manner and can be used as a feature extractor, while the top RBM can be trained in a supervised manner (on the joint distribution of the inputs from the previous layer and the target classes) and can be used as a classifier.

[0044] A deep convolutional network (DCN) is a network of convolutional networks configured with additional pooling and normalization layers. The DCN has achieved state-of-the-art performance on many tasks. The DCN can be trained using supervised learning, where both the input targets and the output targets are known for many paradigms and are used to modify the weights of the network by using gradient descent methods.

[0045] The DCN can be a feedforward network. Additionally, as described above, the connections from the neurons in the first layer of the DCN to a set of neurons in the next higher layer are shared across the neurons in the first layer. The feedforward and shared connections of the DCN can be used for fast processing. For example, the computational burden of the DCN may be much smaller than that of a similarly sized neural network that includes recurrent or feedback connections.

[0046] The processing of each layer of a convolutional network can be considered as a spatially invariant template or basis projection. If the input is first decomposed into multiple channels, such as the red, green, and blue channels of a color image, then the convolutional network trained on this input can be considered three-dimensional, where two spatial dimensions are along the axes of the image, and the third dimension captures color information. The output of the convolutional connection can be considered to form a feature map in subsequent layers, where each element in this feature map (e.g., 220) receives inputs from a certain range of neurons in the previous layer (e.g., feature map 218) and from each of the multiple channels. The values in the feature map can be further processed with a non-linearity such as rectification, max(0,x). Values from adjacent neurons can be further pooled, which corresponds to downsampling, and can provide additional local invariance and dimensionality reduction. Normalization corresponding to whitening can also be applied through lateral inhibition between neurons in the feature map.

[0047] The performance of deep learning architectures can increase as more labeled data points become available or as computing power increases. Modern deep neural networks are typically trained with computing resources that are thousands of times the computing resources available to a typical researcher only fifteen years ago. New architectures and training paradigms can further enhance the performance of deep learning. Rectified linear units can reduce a training problem called vanishing gradients. New training techniques can reduce overfitting and thus enable larger models to achieve better generalization. Encapsulation techniques can extract data within a given receptive field and further improve overall performance.

[0048] Figure 3 is a block diagram illustrating a deep convolutional network 350. Based on connections and weight sharing, the deep convolutional network 350 can include multiple different types of layers. As Figure 3 shown, the deep convolutional network 350 includes convolutional blocks 354A, 354B. Each of the convolutional blocks 354A, 354B can be configured with a convolutional layer (CONV) 356, a normalization layer (LNorm) 358, and a max pooling layer (MAX POOL) 360.

[0049] The convolutional layer 356 can include one or more convolutional filters that can be applied to the input data to generate a feature map. Although only two convolutional blocks 354A, 354B are shown, the present disclosure is not limited thereto, but instead, any number of convolutional blocks 354A, 354B can be included in the deep convolutional network 350 according to design preferences. The normalization layer 358 can normalize the output of the convolutional filter. For example, the normalization layer 358 can provide whitening or lateral inhibition. The max pooling layer 360 can provide spatially downsampled aggregation to achieve local invariance and dimensionality reduction.

[0050] For example, the parallel filter bank of the deep convolutional network can be loaded onto the CPU 102 or GPU 104 of the SoC 100 to achieve high performance and low power consumption. In an alternative embodiment, the parallel filter bank can be loaded onto the DSP 106 or ISP 116 of the SoC 100. Additionally, the deep convolutional network 350 can access other processing blocks that may be present on the SoC 100, such as the sensor processor 114 and the navigation module 120 dedicated to sensors and navigation, respectively.

[0051] The deep convolutional network 350 may also include one or more fully connected layers 362 (FC1 and FC2). The deep convolutional network 350 may also include a logistic regression (LR) layer 364. There are weights (not shown) to be updated between each layer 356, 358, 360, 362, 364 of the deep convolutional network 350. The output of each of these layers (e.g., 356, 358, 360, 362, 364) can be used as the input to the subsequent layer among these layers (e.g., 356, 358, 360, 362, 364) in the deep convolutional network 350 to learn a hierarchical feature representation from the input data 352 (e.g., image, audio, video, sensor data, and / or other input data) supplied at the first convolutional block 354A. The output of the deep convolutional network 350 is a classification score 366 for the input data 352. The classification score 366 can be a set of probabilities, where each probability is the probability that the input data includes features from a set of features.

[0052] Figure 4 is a block diagram illustrating an exemplary software architecture 400 that enables modularization of artificial intelligence (AI) functions. According to aspects of the present disclosure, by using this architecture, various processing blocks of a system-on-chip (SoC) 420 (e.g., CPU 422, DSP 424, GPU 426, and / or NPU 428) can be designed to support applications of adaptive rounding as disclosed for post-training quantization for AI applications 402.

[0053] The AI application 402 can be configured to call functions defined in the user space 404, which can, for example, provide detection and recognition of a scene indicating the current operating location of the device. For example, the AI application 402 can configure the microphone and camera differently depending on whether the identified scene is an office, a lecture hall, a restaurant, or an outdoor environment such as a lake. The AI application 402 can make a request for compiled program code associated with a library defined in the AI function application programming interface (API) 406. This request can ultimately depend on the output of a deep neural network configured to provide an inference response based on, for example, video and location data.

[0054] The runtime engine 408, which can be the compiled code of a runtime framework, can be further accessible by the AI application 402. For example, the AI application 402 can cause the runtime engine to request an inference to be triggered at specific time intervals or by events detected by the application's user interface. When causing the runtime engine to provide an inference response, the runtime engine can in turn send a signal to an operating system (such as the Linux kernel 412) in the operating system (OS) space running on the SoC 420. The operating system can then cause continuous quantization relaxation to be performed on the CPU 422, DSP 424, GPU 426, NPU 428, or some combination thereof. The CPU 422 can be directly accessed by the operating system, while the other processing blocks can be accessed through drivers (such as drivers 414, 416, or 418 for the DSP 424, GPU 426, or NPU 428 respectively). In an exemplary example, a deep neural network can be configured to run on a combination of processing blocks (such as the CPU 422, DSP 424, and GPU 426), or can run on the NPU 428.

[0055] The application 402 (e.g., an AI application) can be configured to call functions defined in the user space 404. For example, these functions can provide detection and recognition of a scene indicating the current operating location of the device. For example, the application 402 can configure the microphone and camera differently depending on whether the recognized scene is an office, lecture hall, restaurant, or an outdoor environment such as a lake. The application 402 can make a request for compiled program code associated with a library defined in the SceneDetect application programming interface (API) 406 to provide an estimate of the current scene. This request can ultimately depend on the output of a differential neural network configured to provide a scene estimate based on, for example, video and location data.

[0056] The runtime engine 408, which can be the compiled code of a runtime framework, can be further accessible by the application 402. For example, the application 402 can cause the runtime engine to request a scene estimate to be triggered at specific time intervals or by events detected by the application's user interface. When causing the runtime engine to estimate the scene, the runtime engine can in turn send a signal to the operating system 410 (such as the Linux kernel 412) running on the SoC 420. The operating system 410 can then cause computations to be performed on the CPU 422, DSP 424, GPU 426, NPU 428, or some combination thereof. The CPU 422 can be directly accessed by the operating system, while the other processing blocks can be accessed through drivers (such as drivers 414 - 418 for the DSP 424, GPU 426, or NPU 428 respectively). In an exemplary example, a differential neural network can be configured to run on a combination of processing blocks (such as the CPU 422 and GPU 426), or can run on the NPU 428.

[0057] As described, an adaptive line enhancer (ALE) is widely used in communication, medical, and acoustic applications where narrowband signal components within broadband noise can be extracted. A broadband digital signal processing system may be vulnerable to narrowband radio frequency (RF) interference. An analog front end (AFE) filter circuit can suppress out-of-band RF interference. However, a broadband system can be directly affected by in-band RF interference that cannot be eliminated by conventional filters (e.g., FIR-ALE). In-band RF interference degrades performance (e.g., lower audio quality, increased bit error rate, blurry images), and its bursty nature can cause an immediate system failure.

[0058] Conventional techniques for adaptive noise cancellation employ a finite impulse response (FIR)-based adaptive line enhancer (ALE). The FIR-based ALE is a tracking system that detects and extracts narrowband interference from a broadband source by exploiting the time-domain correlation difference between the narrowband interference y(t) and the broadband source v(t), where y(t) and v(t) are continuous-time signals and t is time. Digital estimates y'(n) and v'(n) of the respective narrowband and broadband signals can be generated from the ALE, where y′[n] and v′[n] are discrete-time signals and n is the sample index. However, narrowband signals are typically captured using an analog front end (AFE) circuit. The AFE circuit can include circuits such as mixers, variable gain amplifiers, and analog-to-digital converters, and these AFE circuits introduce non-linear distortion before adding broadband noise. Due to the linear nature of FIR, the FIR-based ALE cannot directly overcome the non-linear impairments of the AFE. Thus, the signals distorted non-linearly can degrade the estimation performance of the ALE. Accordingly, aspects of the present disclosure relate to a neural network-based adaptive line enhancer.

[0059] Figure 5 is a block diagram illustrating an example neural network-based adaptive line enhancer (NN-ALE) 500 according to aspects of the present disclosure. Refer to Figure 5 , the NN-ALE 500 includes a delay block 504 and a neural network 506. The NN-ALE 500 receives an input signal 502. The input signal 502 can include a narrowband interference signal Y (e.g., noise) and a broadband source V. The input signal 502 can be supplied to the delay block 504. The delay block 504 is configured to have a delay that is longer than the autocorrelation span of the broadband signal but shorter than the span of the narrowband interference signal Y. The output of the delay block 504 is supplied to the neural network 506.

[0060] The neural network 506 can be, for example, a recurrent neural network or a convolutional neural network (e.g., Figure 3The block 354A shown). The neural network 506 may include one or more convolutional layers. In some aspects, the neural network 506 may include one or more fully connected layers. The neural network 506 performs a decorrelation process based on the latency such that the output of the neural network 506 produces a narrowband interference estimate Y' (which may also be referred to as a "noise estimate"). The narrowband interference estimate Y' may be supplied as feedback to the summing node 508 such that the value of the narrowband interference estimate Y' may be inverted (e.g., -Y'). Thus, the narrowband interference estimate Y' is subtracted from the input signal 502 to produce a wideband estimate V'. Thus, by using the wideband estimate V', the noise in the input signal 502 may be suppressed or reduced. In some aspects, the neural network 506 may be trained based on a residual error, which may be expressed as the difference between the narrowband interference estimate Y' and the original input signal 502.

[0061] In some aspects, the neural network may not use an additional dedicated reference (or ground truth) as in supervised learning. The input signal 502 is the equivalent reference, and thus the residual error from the output of the summing node 508 is the error for backpropagation of the neural network within the NN-ALE 500. This also means that when the properties of the narrowband noise (e.g., frequency, amplitude, non-linearity) change (e.g., due to a change in system temperature, or an adjustment of the amplitude of the noise source), the neural network 506 may detect and track the changes from the narrowband interference signal (e.g., noise) Y + wideband source V. The neural network 506 also adjusts the neural network parameters to maintain noise suppression as long as the properties change within a certain boundary (e.g., not exceeding the ability of the backpropagation learning rate).

[0062] Figure 6 An expanded block diagram illustrating an example system 600 for noise reduction using an artificial neural network in accordance with aspects of the present disclosure. Refer to Figure 6 , the system 600 includes an analog front end (AFE) circuit 604, an analog-to-digital converter (ADC) 608, and a neural network-based adaptive line enhancer (NN-ALE) 500 (as Figure 5 shown). The wideband signal v(t) 610 may be affected by a noise signal associated with or generated within the input to the AFE circuit 610. For example, the AFE 610 may receive a noise signal 602a as an input, such as, for example, a sinusoidal narrowband interference source (e.g., fast frequency sinusoidal narrowband interference), a voice signal, or a pulse amplitude modulation (PAM) narrowband interference. Such a noise signal 602a may cause non-linear distortion (e.g., AFE non-linearity 602b). The AFE non-linearity 602b may be generated (e.g.) via a transmitter (e.g., power amplifier) of the RF input signal, via the signal propagation channel, or via a receiver (e.g., variable gain amplifier).

[0063] The AFE circuit 604 may not be able to eliminate non - linear distortion. Thus, a narrow - band signal due to AFE non - linear distortion is combined with a wide - band signal v(t) that may be received as an input at the ADC 608 via a summing node 606. Thus, the ADC 608 may receive the wide - band signal (V) and the narrow - band interference signal (Y), resulting in a combined wide - band signal and narrow - band interference signal (e.g., V + Y). The ADC 608 may sample the combined wide - band signal and narrow - band interference signal (e.g., V + Y) and may provide the samples to the NN - ALE 500. The NN - ALE 500 may process the combined wide - band signal and narrow - band interference signal (e.g., V + Y) via a convolutional layer to decorrelate the wide - band signal v(t) from the narrow - band interference signal y(t), where t is continuous time. In so doing, the NN - ALE 500 may generate a narrow - band estimate y'(n) 612 and a wide - band estimate v'(n) 614, where n is the sample index. Subsequently, the narrow - band estimate y'(n) 612 and the wide - band estimate v'(n) 614 may be used to reduce the narrow - band interference y(t) (e.g., noise). Different from conventional FIR - based ALE, the narrow - band estimate y'(n) 612 and the wide - band estimate v'(n) 614 may also be used to reduce the AFE non - linear distortion 602b. The non - linear distortion may be generated (e.g.) via a transmitter (e.g., power amplifier) of the input signal, via a signal propagation channel, or via a receiver (e.g., variable - gain amplifier).

[0064] Accordingly, aspects of the present disclosure may be beneficially applied to fields such as communication systems and medical diagnostics. For example, in some aspects, the NN - ALE 500 may be incorporated in, for example, a headset product with active noise cancellation, a device with electromagnetic interference cancellation, a surveillance device, or a medical imaging device.

[0065] Figure 7 is a flowchart illustrating a processor - implemented method 700 for noise reduction using an artificial - neural - network - based adaptive line - spectral enhancer according to aspects of the present disclosure. As Figure 7 shown, at block 702, the method 700 receives an input signal including a combined wide - band signal and noise. As described, for example, with reference to Figure 5 , the NN - ALE 500 receives the input signal 502. The input signal 502 may include a narrow - band interference signal Y (e.g., noise) and a wide - band source V. In some aspects, the input signal may include, for example, a sinusoidal narrow - band interference source (e.g., fast - frequency sinusoidal narrow - band interference), a voice signal, or a pulse - amplitude - modulation (PAM) narrow - band interference. Additionally, in some aspects, the noise may include non - linear distortion.

[0066] At block 704, the method 700 decorrelates the input signal based on delay via an artificial neural network. For example, as referenced in Figure 5As described, the neural network 506 performs a decorrelation process based on latency.

[0067] At block 706, method 700 generates an estimate of the wideband signal and an estimate of the noise based on the decorrelated input via an artificial neural network. As Figure 5 and Figure 6 shown, NN-ALE can generate a narrowband interference estimate Y' and a wideband estimate V'. In Figure 5 and Figure 6 the example of, the narrowband interference estimate Y' can include a "noise estimate".

[0068] At block 708, method 700 reduces the noise in the input signal based at least in part on the estimated narrowband signal. For example, as referenced Figure 5 and Figure 6 described, the narrowband interference estimate Y' can be supplied as feedback to a summing node 508 such that the value of the narrowband interference estimate Y' can be inverted (e.g., -Y'). Accordingly, the narrowband interference estimate Y' can be subtracted from the input signal 502 to produce the wideband estimate V'. Thus, by using the wideband estimate V', the noise in the input signal 502 can be suppressed or reduced.

[0069] Specific implementation examples are provided in the following numbered clauses:

[0070] 1. A processor-implemented method, comprising:

[0071] Receiving an input signal comprising a combined wideband signal and noise;

[0072] Decorrelating the input signal via an artificial neural network based on latency;

[0073] Generating an estimate of the wideband signal and an estimate of the noise based on the decorrelated input via the artificial neural network; and

[0074] Reducing the noise in the input signal based at least in part on the noise estimate.

[0075] 2. The processor-implemented method according to clause 1, wherein the artificial neural network is trained based on the wideband estimate.

[0076] 3. The processor-implemented method according to clause 1 or 2, wherein the narrowband interference comprises one of fast frequency sinusoidal narrowband interference, sinusoidal narrowband interference source signal, voice signal, or pulse amplitude modulation (PAM) narrowband interference.

[0077] 4. The processor-implemented method according to any one of clauses 1 to 3, wherein the noise comprises one or more of the narrowband interference or non-linear distortion.

[0078] 5. The processor-implemented method according to any one of clauses 1 to 4 further includes: calculating a difference between a noise estimate and the combined input signal.

[0079] 6. The processor-implemented method according to any one of clauses 1 to 5, wherein the input signal is received via an analog front-end circuit.

[0080] 7. The processor-implemented method according to any one of clauses 1 to 6, wherein the artificial neural network is incorporated in a communication device, an active noise cancellation device, a medical diagnostic device, or an echo cancellation device.

[0081] 8. An apparatus for a processor-implemented method, comprising:

[0082] a memory; and

[0083] at least one processor coupled to the memory, the at least one processor

[0084] being configured to:

[0085] receive an input signal including a combined broadband signal and noise;

[0086] decorrelate the input signal via an artificial neural network based on a delay;

[0087] generate an estimate of the broadband signal and a noise estimate via the artificial neural network based on the decorrelated input; and

[0088] reduce the noise in the input signal at least in part based on the noise estimate.

[0089] 9. The apparatus according to clause 8, wherein the artificial neural network is trained based on the broadband estimate.

[0090] 10. The apparatus according to clause 8 or 9, wherein the narrowband interference includes one of fast frequency sinusoidal narrowband interference, sinusoidal narrowband interference source signal, voice signal, or pulse amplitude modulation (PAM) narrowband interference.

[0091] 11. The apparatus according to any one of clauses 8 to 10, wherein the noise includes one or more of the narrowband interference or nonlinear distortion.

[0092] 12. The apparatus according to any one of clauses 8 to 11, wherein the at least one processor is further configured to calculate a difference between the noise estimate and the combined input signal.

[0093] 13. The apparatus according to any one of clauses 8 to 12, wherein the input signal is received via an analog front-end circuit.

[0094] 14. The apparatus according to any one of clauses 8 to 13, wherein the artificial neural network is incorporated in a communication device, an active noise cancellation device, a medical diagnostic device, or an echo cancellation device.

[0095] 15. A non-transitory computer-readable medium having program code recorded thereon, the program code being executed by a processor and comprising:

[0096] Program code for receiving an input signal including a combined broadband signal and noise;

[0097] Program code for decorrelating the input signal based on a delay via an artificial neural network;

[0098] Program code for generating an estimate of the broadband signal and a noise estimate based on the decorrelated input via the artificial neural network; and

[0099] Program code for reducing the noise in the input signal based at least in part on the noise estimate.

[0100] 16. The non-transitory computer-readable medium according to clause 15, wherein the artificial neural network is trained based on the broadband estimate.

[0101] 17. The non-transitory computer-readable medium according to clause 15 or 16, wherein the narrowband interference includes one of fast-frequency sinusoidal narrowband interference, a sinusoidal narrowband interference source signal, a voice signal, or pulse amplitude modulation (PAM) narrowband interference.

[0102] 18. The non-transitory computer-readable medium according to any one of clauses 15 to 17, wherein the noise includes one or more of the narrowband interference or non-linear distortion.

[0103] 19. The non-transitory computer-readable medium according to any one of clauses 15 to 18, further comprising: program code for calculating a difference between the noise estimate and the combined input signal.

[0104] 20. The non-transitory computer-readable medium according to any one of clauses 15 to 19, wherein the input signal is received via an analog front-end circuit.

[0105] 21. The non-transitory computer-readable medium according to any one of clauses 15 to 20, wherein the artificial neural network is incorporated in a communication device, an active noise cancellation device, a medical diagnostic device, or an echo cancellation device.

[0106] 22. An apparatus comprising:

[0107] A component for receiving an input signal including a combined broadband signal and noise;

[0108] A component for decorrelating the input signal based on delay via an artificial neural network;

[0109] A component for generating an estimate of the broadband signal and a noise estimate based on the decorrelated input via the artificial neural network; and

[0110] A component for reducing the noise in the input signal based at least in part on the noise estimate.

[0111] 23. The apparatus according to clause 22, wherein the artificial neural network is trained based on the broadband estimate.

[0112] 24. The apparatus according to clause 22 or 23, wherein the narrowband interference includes one of fast frequency sinusoidal narrowband interference, sinusoidal narrowband interference source signal, voice signal, or pulse amplitude modulation (PAM) narrowband interference.

[0113] 25. The apparatus according to any one of clauses 22 to 24, wherein the noise includes one or more of the narrowband interference or non - linear distortion.

[0114] 26. The apparatus according to any one of clauses 22 to 25, further comprising: a component for calculating the difference between the noise estimate and the combined input signal.

[0115] 27. The apparatus according to any one of clauses 22 to 26, wherein the input signal is received via an analog front - end circuit.

[0116] 28. The apparatus according to any one of clauses 22 to 27, wherein the artificial neural network is incorporated in a communication device, an active noise cancellation device, a medical diagnostic device, or an echo cancellation device.

[0117] In one aspect, the receiving component, the decorrelating component, the generating component, the reducing device, and / or the calculating device can be the CPU 102 configured to perform the recited functions, the program memory associated with the CPU 102, the dedicated memory block 118, the fully - connected layer 362, and / or the NPU 428. In another configuration, the foregoing components can be any module or any device configured to perform the functions recited by the foregoing components.

[0118] The various operations of the above-described method can be performed by any suitable component capable of performing the corresponding functions. These components can include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs), or processors. Generally, in cases where operations are illustrated in the figures, these operations can have corresponding paired components plus functional components with similar numbers.

[0119] As used, the term "determine" encompasses a wide variety of actions. For example, "determine" can include calculating, computing, processing, deducing, investigating, looking up (e.g., looking up in a table, database, or another data structure), ascertaining, and so on. Additionally, "determine" can include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), etc. Further, "determine" can include parsing, selecting, choosing, establishing, etc.

[0120] As used, the phrase referring to "at least one of" a list of items means any combination of these items, including a single member. As an example, "at least one of a, b, or c" is intended to cover: a, b, c, a - b, a - c, b - c, and a - b - c.

[0121] The various illustrative logical blocks, modules, and circuits described in connection with the present disclosure can be implemented or performed with a general purpose processor, digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array signal (FPGA), or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the described functions. The general purpose processor can be a microprocessor, but in the alternative, the processor can be any commercially available processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0122] The steps or algorithms of the methods described in connection with the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of both. The software modules may reside in any form of storage medium known in the art. Some examples of storage media that may be used include random access memory (RAM), read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, CD-ROMs, and the like. The software modules may include a single instruction, or many instructions, and may be distributed over several different code segments, among different programs, and across multiple storage media. The storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In an alternative, the storage medium may be integral with the processor.

[0123] The methods disclosed herein include one or more steps or acts for implementing the described methods. The steps and / or acts of the methods may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of the steps or acts is specified, the order and / or use of specific steps and / or acts may be modified without departing from the scope of the claims.

[0124] The described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may include a processing system in a device. The processing system may be implemented using a bus architecture. Depending on the particular application and overall design constraints of the processing system, the bus may include any number of interconnecting buses and bridges. The bus may link together various circuits, including a processor, a machine-readable medium, and a bus interface. The bus interface may be used to connect a network adapter, etc. to the processing system via the bus. The network adapter may be used to implement signal processing functions. For some aspects, a user interface (e.g., keypad, display, mouse, joystick, etc.) may also be connected to the bus. The bus may also link various other circuits, such as a timing source, peripherals, voltage regulators, power management circuits, etc., which are well known in the art and will not be described further.

[0125] The processor may be responsible for managing the bus and general processing, including executing software stored on a machine-readable medium. The processor may be implemented using one or more general-purpose processors and / or dedicated processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuitry capable of executing software. Software should be broadly interpreted to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. By way of example, the machine-readable medium may include random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, magnetic disks, optical disks, hard disk drives, or any other suitable storage medium, or any combination thereof. The machine-readable medium may be embodied in a computer program product. The computer program product may include packaging material.

[0126] In a hardware implementation, the machine-readable medium may be part of a processing system separate from the processor. However, as will be readily understood by those skilled in the art, the machine-readable medium or any portion thereof may be external to the processing system. By way of example, the machine-readable medium may include transmission lines, carriers modulated by data, and / or computer products separate from the device, all of which may be accessed by the processor via a bus interface. Alternatively or in addition, the machine-readable medium or any portion thereof may be integrated into the processor, such as in the case of having a cache and / or a general register file. Although the various components discussed may be described as having a particular location, such as local components, they may also be configured in various ways, such as some components being configured as part of a distributed computing system.

[0127] The processing system may be configured as a general-purpose processing system having one or more microprocessors providing processor functionality and an external memory providing at least a portion of the machine-readable medium, all of these components linked together via an external bus architecture with other supporting circuitry. Alternatively, the processing system may include one or more neuromorphic processors for implementing the described neuron models and nervous system models. As yet another alternative, the processing system may be implemented using an application-specific integrated circuit (ASIC) having a processor, a bus interface, a user interface, supporting circuitry, and at least a portion of the machine-readable medium integrated on a single chip, or using one or more field-programmable gate arrays (FPGA), programmable logic devices (PLD), controllers, state machines, gated logic, discrete hardware components, or any other suitable circuitry, or any combination of circuits capable of performing the various functions described throughout this disclosure. Those skilled in the art will recognize how best to implement the described functionality of the processing system depending on the particular application and the overall design constraints imposed on the system as a whole.

[0128] A machine-readable medium may include a plurality of software modules. These software modules include instructions that, when executed by a processor, cause a processing system to perform various functions. The software modules may include a sending module and a receiving module. Each software module may reside in a single storage device or be distributed across multiple storage devices. By way of example, when a triggering event occurs, the software modules may be loaded from a hard disk drive into RAM. During the execution of the software modules, the processor may load some of the instructions into a cache to improve access speed. Then one or more cache lines may be loaded into the general register file for the processor to execute. When the functionality of a software module is referred to hereinafter, it will be understood that such functionality is implemented by the processor when executing instructions from that software module. In addition, it should be understood that aspects of the present disclosure result in improvements to the functionality of a processor, computer, machine, or other system implementing such aspects.

[0129] If implemented in software, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. The storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Additionally, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared (IR), radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of the medium. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and optical disc, where disks typically reproduce data magnetically, while discs reproduce data optically with lasers. Thus, in some aspects, computer-readable media may include non-transitory computer-readable media (e.g., tangible media). Additionally, for other aspects, computer-readable media may include transitory computer-readable media (e.g., signals). Combinations of the above should also be included within the scope of computer-readable media.

[0130] Accordingly, certain aspects may include a computer program product for performing the operations given herein. For example, such a computer program product may include a computer-readable medium having instructions stored (and / or encoded) thereon, which instructions can be executed by one or more processors to perform the described operations. For some aspects, the computer program product may include packaging material.

[0131] In addition, it should be understood that modules and / or other suitable components for performing the described methods and techniques may be downloaded and / or otherwise obtained by a user terminal and / or a base station, where applicable. For example, such devices can be coupled to a server to facilitate the transfer of components for performing the described methods. Alternatively, the various methods described can be provided via a storage component (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or a floppy disk) such that, once the storage component is coupled to or provided to the device, the user terminal and / or the base station can obtain the various methods. Moreover, any other suitable technique for providing the described methods and techniques to the device can be utilized.

[0132] It should be understood that the claims are not limited to the exact configurations and components illustrated above. Various modifications, variations, and alterations to the arrangements, operations, and details of the methods and apparatuses described above may be made without departing from the scope of the claims.

Claims

1. A processor-implemented method, comprising: Receiving an input signal comprising a combined broadband signal and noise; Decorrelating the input signal via an artificial neural network based on a delay; Generating an estimate of the broadband signal and a noise estimate based on the decorrelated input via the artificial neural network; and Reducing the noise in the input signal based at least in part on the noise estimate.

2. The processor-implemented method according to claim 1, wherein the artificial neural network is trained based on the broadband estimate.

3. The processor-implemented method according to claim 1, wherein the narrowband interference comprises one of fast frequency sinusoidal narrowband interference, a sinusoidal narrowband interference source signal, a voice signal, or pulse amplitude modulation (PAM) narrowband interference.

4. The processor-implemented method according to claim 1, wherein the noise comprises one or more of the narrowband interference or non-linear distortion.

5. The processor-implemented method according to claim 1, further comprising: Calculating a difference between the noise estimate and the combined input signal.

6. The processor-implemented method according to claim 1, wherein the input signal is received via an analog front-end circuit.

7. The processor-implemented method according to claim 1, wherein the artificial neural network is incorporated in a communication device, an active noise cancellation device, a medical diagnostic device, or an echo cancellation device.

8. An apparatus for a processor-implemented method, comprising: A memory; And At least one processor coupled to the memory, the at least one processor being configured to: Receive an input signal comprising a combined broadband signal and noise; Decorrelate the input signal via an artificial neural network based on a delay; Generate an estimate of the broadband signal and a noise estimate based on the decorrelated input via the artificial neural network; and Reduce the noise in the input signal based at least in part on the noise estimate.

9. The apparatus according to claim 8, wherein the artificial neural network is trained based on the broadband estimate.

10. The apparatus according to claim 8, wherein the narrowband interference comprises one of fast frequency sinusoidal narrowband interference, a sinusoidal narrowband interference source signal, a voice signal, or pulse amplitude modulation (PAM) narrowband interference.

11. The apparatus according to claim 8, wherein the noise comprises one or more of the narrowband interference or non-linear distortion.

12. The apparatus according to claim 8, wherein the at least one processor is further configured to calculate a difference between the noise estimate and the combined input signal.

13. The apparatus according to claim 8, wherein the input signal is received via an analog front-end circuit.

14. The apparatus according to claim 8, wherein the artificial neural network is incorporated in a communication device, an active noise cancellation device, a medical diagnostic device, or an echo cancellation device.

15. A non-transitory computer-readable medium having program code recorded thereon, the program code being executed by a processor and comprising: Program code for receiving an input signal comprising a combined broadband signal and noise; Program code for decorrelating the input signal based on delay via an artificial neural network; Program code for generating an estimate of the broadband signal and a noise estimate based on the decorrelated input via the artificial neural network; and Program code for reducing the noise in the input signal based at least in part on the noise estimate.

16. The non-transitory computer-readable medium according to claim 15, wherein the artificial neural network is trained based on the broadband estimate.

17. The non-transitory computer-readable medium according to claim 15, wherein the narrowband interference includes one of fast-frequency sinusoidal narrowband interference, sinusoidal narrowband interference source signal, voice signal, or pulse amplitude modulation (PAM) narrowband interference.

18. The non-transitory computer-readable medium according to claim 15, wherein the noise includes one or more of the narrowband interference or non-linear distortion.

19. The non-transitory computer-readable medium according to claim 15, further comprising: Program code for calculating the difference between the noise estimate and the combined input signal.

20. The non-transitory computer-readable medium according to claim 15, wherein the input signal is received via an analog front-end circuit.

21. The non-transitory computer-readable medium according to claim 15, wherein the artificial neural network is incorporated in a communication device, an active noise cancellation device, a medical diagnostic device, or an echo cancellation device.

22. An apparatus, comprising: means for receiving an input signal including a combined broadband signal and noise; means for decorrelating the input signal based on delay via an artificial neural network; means for generating an estimate of the broadband signal and a noise estimate based on the decorrelated input via the artificial neural network; and means for reducing the noise in the input signal based at least in part on the noise estimate.

23. The apparatus according to claim 22, wherein the artificial neural network is trained based on the broadband estimate.

24. The apparatus according to claim 22, wherein the narrowband interference includes one of fast-frequency sinusoidal narrowband interference, sinusoidal narrowband interference source signal, voice signal, or pulse amplitude modulation (PAM) narrowband interference.

25. The apparatus according to claim 22, wherein the noise includes one or more of the narrowband interference or non-linear distortion.

26. The apparatus according to claim 22, further comprising: means for calculating the difference between the noise estimate and the combined input signal.

27. The apparatus according to claim 22, wherein the input signal is received via an analog front-end circuit.

28. The apparatus according to claim 22, wherein the artificial neural network is incorporated in a communication device, an active noise cancellation device, a medical diagnostic device, or an echo cancellation device.

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