Quantum chip design process DRC detection method and device, equipment and storage medium

Abstract

The invention discloses a quantum chip design process DRC detection method, device and equipment and a storage medium, and relates to the technical field of quantum computing, and the method comprises the steps: building a distributed learning framework, and carrying out the initialization of a design rule check model on the distributed learning framework, and obtaining a to-be-trained DRC detection model; obtaining model updating parameters provided by each chip designer, and carrying out aggregation processing on the model updating parameters to obtain global model parameters; the model updating parameters are data obtained by training a to-be-trained DRC detection model on a distributed learning framework locally by each chip design party by using local chip design data; and sending the global model parameter to each chip design party, so that each chip design party detects the quantum chip design process by using a target DRC detection model obtained by updating the local DRC detection model based on the global model parameter to obtain a DRC detection result. Therefore, the design rule checking efficiency of the layout can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of quantum computing, and particularly to a DRC detection method, device, equipment and storage medium in the process of quantum chip design. Background Art

[0002] EDA (Electronic Design Automation) technology is a new technology dedicated to electronic systems formed by scientifically and effectively integrating databases, computational mathematics, graph theory, graphics, topological logic, optimization theory, etc. with the help of computers and using the expression of hardware description languages. It is the latest achievement of computer technology, signal processing technology, and signal analysis technology. The emergence of EDA technology not only better guarantees the simulation, debugging, and error correction at all levels of electronic engineering design, provides strong technical support for its development, but also greatly reduces the work intensity of relevant practitioners. In recent years, EDA online platforms have become indispensable tools in the field of electronic design. In the development of quantum EDA online layout design tools, Design Rule Check (DRC) is an important link in layout verification and is crucial for ensuring the manufacturability and reliability of quantum chip design. Traditional DRC methods have problems such as insufficient data privacy protection and low inspection efficiency.

[0003] It can be seen that how to improve the efficiency of design rule checking for the layout is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of the embodiments of the present invention is to provide a DRC detection method, device, equipment and storage medium in the process of quantum chip design, which can improve the efficiency of design rule checking for the layout. The specific solutions are as follows:

[0005] In the first aspect, the present invention discloses a DRC detection method in the process of quantum chip design, which is applied to a central server and includes:

[0006] Build a distributed learning framework and initialize a design rule checking model on the distributed learning framework to obtain a to-be-trained DRC detection model;

[0007] Obtain the model update parameters provided by each chip design party, and perform aggregation processing on the model update parameters to obtain global model parameters; the model update parameters are data obtained by each chip design party using local chip design data to train the to-be-trained DRC detection model on the distributed learning framework respectively;

[0008] Send the global model parameters to each chip designer so that each chip designer can update the local DRC detection model based on the global model parameters to obtain the target DRC detection model, and use the target DRC detection model to detect the quantum chip design process to obtain the DRC detection result.

[0009] Optionally, build a distributed learning framework and initialize the design rule checking model on the distributed learning framework to obtain the DRC detection model to be trained, including:

[0010] Select a target learning model from several machine learning models based on the preset quantum chip design requirements, and determine the target learning model as the design rule checking model;

[0011] Build a distributed learning framework locally or at the target coordination node; the distributed learning framework has the ability to process encrypted data;

[0012] On the distributed learning framework, initialize the model parameters of the design rule checking model based on the model initialization method to obtain the DRC detection model to be trained.

[0013] Optionally, the process of training the DRC detection model to be trained on the distributed learning framework by the chip designer to obtain the model update parameters includes:

[0014] Each chip designer encrypts the local quantum chip design data based on the preset public key encryption technology to generate the target chip design data;

[0015] Each chip designer uses the target chip design data and the preset optimization algorithm to update the model parameters of the DRC detection model to be trained on the distributed learning framework locally to obtain the updated DRC detection model;

[0016] Determine whether the updated DRC detection model meets the preset model training end condition; the preset model training end condition is that the loss function value corresponding to the updated DRC detection model converges to the preset threshold;

[0017] If the updated DRC detection model meets the preset model training end condition, obtain the current update parameters corresponding to the updated DRC detection model;

[0018] Use the preset public key encryption technology to encrypt the current update parameters to obtain the model update parameters;

[0019] Correspondingly, obtain the model update parameters provided by each chip designer, and aggregate the model update parameters to obtain the global model parameters, including:

[0020] Obtain the model update parameters provided by each chip designer, and decrypt the model update parameters using the preset public key encryption technology to obtain the decrypted parameters;

[0021] Use the preset weighted average algorithm to aggregate the decrypted parameters to obtain the global model parameters.

[0022] Optionally, the chip designer updates the model parameters of the DRC detection model to be trained on the distributed learning framework locally using the target chip design data and the preset optimization algorithm, including:

[0023] The chip designer locally identifies and extracts the features that violate the predetermined rules of chip design in the target chip design data to obtain the target features;

[0024] The chip designer inputs the target features into the DRC detection model to be trained on the distributed learning framework to train the DRC detection model to be trained, and at the same time updates the model parameters of the DRC detection model to be trained using the preset optimization algorithm to obtain the updated DRC detection model.

[0025] Optionally, the process by which the chip designer updates the local DRC detection model based on the global model parameters to obtain the target DRC detection model and uses the target DRC detection model to detect the quantum chip design process to obtain the DRC detection result includes:

[0026] The chip designer obtains the global model parameters and updates the updated DRC detection model using the global model parameters to obtain the target DRC detection model;

[0027] Use the target DRC detection model to detect the quantum chip layout design to obtain the DRC detection result; the quantum chip layout design is the data obtained by encrypting the changed local quantum chip design data using the preset public key encryption technology.

[0028] Optionally, after using the target DRC detection model to detect the quantum chip layout design to obtain the DRC detection result, it further includes:

[0029] When there is an abnormal design situation in the DRC detection result, decrypt the quantum chip layout design to obtain the chip design abnormal position and abnormal type;

[0030] Display the chip design abnormal position and abnormal type in the preset front-end DRC function error reporting column, and block the function of the quantum chip layout design, so that the chip designer can correct the quantum chip layout design based on the chip design abnormal position and abnormal type.

[0031] Optionally, after the chip designer corrects the quantum chip layout design based on the abnormal position and type of the chip design, it further includes:

[0032] Each chip designer respectively obtains the optimized design data obtained after correcting the quantum chip layout design, and updates the local quantum chip design data based on the optimized design data to obtain new local quantum chip design data;

[0033] Jump to the step where each chip designer encrypts the local quantum chip design data based on the preset public key encryption technology to generate the target chip design data until new global model parameters are obtained.

[0034] In a second aspect, the present invention discloses a DRC detection device for the quantum chip design process, which is applied to a central server and includes:

[0035] A model initialization module, configured to build a distributed learning framework and initialize a design rule check model on the distributed learning framework to obtain a to-be-trained DRC detection model;

[0036] A model training module, configured to obtain the model update parameters provided by each chip designer and perform an aggregation process on the model update parameters to obtain global model parameters; the model update parameters are data obtained by each chip designer using the local chip design data to train the to-be-trained DRC detection model on the distributed learning framework respectively;

[0037] A model application module, configured to send the global model parameters to each chip designer, so that each chip designer updates the local DRC detection model based on the global model parameters to obtain a target DRC detection model, and uses the target DRC detection model to detect the quantum chip design process to obtain a DRC detection result.

[0038] In a third aspect, the present invention discloses an electronic device, including:

[0039] A memory, configured to store a computer program;

[0040] A processor, configured to execute the computer program to implement the foregoing DRC detection method for the quantum chip design process.

[0041] In a fourth aspect, the present invention discloses a computer-readable storage medium, configured to store a computer program, and when the computer program is executed by a processor, the foregoing DRC detection method for the quantum chip design process is implemented.

[0042] In the present invention, a distributed learning framework is established, and a design rule check model is initialized on the distributed learning framework to obtain a to-be-trained DRC detection model; model update parameters provided by each chip designer are obtained, and the model update parameters are aggregated to obtain global model parameters; the model update parameters are data obtained by each chip designer training the to-be-trained DRC detection model on the distributed learning framework respectively by using local chip design data; the global model parameters are sent to each chip designer, so that each chip designer updates the local DRC detection model based on the global model parameters to obtain a target DRC detection model, and the quantum chip design process is detected by using the target DRC detection model to obtain a DRC detection result.

[0043] As can be seen from the above technical solutions, the present invention constructs a distributed framework, enabling each chip designer to utilize this distributed framework to simultaneously perform collaborative training and model optimization, that is, to use the federated learning framework to achieve parallel computing and accelerate the training process, and to promote collaborative cooperation among different chip designers by using the distributed framework, expanding the scale and diversity of design data, and improving the accuracy of DRC inspection. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings without creative efforts based on these drawings.

[0045] Figure 1 It is a flowchart of a DRC detection method for a quantum chip design process disclosed by the present invention;

[0046] Figure 2 It is a schematic diagram of a specific quantum chip design data disclosed by the present invention;

[0047] Figure 3 It is a schematic diagram of a specific DRC detection result for a quantum chip design process disclosed by the present invention;

[0048] Figure 4 It is a schematic diagram of the structure of a DRC detection device for a quantum chip design process disclosed by the present invention;

[0049] Figure 5 It is a structural diagram of an electronic device disclosed by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0050] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0051] The terms "including" and "having" in the specification of the present invention and any variations related to "including" and "having" are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may include steps or units not listed.

[0052] In order to enable those skilled in the art of this technology to better understand the solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0053] Traditional DRC methods have problems such as insufficient data privacy protection and low inspection efficiency. Especially in a design environment where multiple chip design parties collaborate, how to achieve efficient DRC inspection without leaking the original design data has become an urgent problem to be solved. Therefore, the present invention will specifically introduce a DRC detection method for the quantum chip design process, which can perform efficient DRC inspection while protecting the privacy of design data.

[0054] See Figure 1 As shown, an embodiment of the present application discloses a DRC detection method for the quantum chip design process, which is applied to a central server and includes:

[0055] Step S11: Build a distributed learning framework and initialize the design rule check model on the distributed learning framework to obtain a to-be-trained DRC detection model.

[0056] In this embodiment, a distributed learning framework is built, and the design rule checking model is initialized on the distributed learning framework to obtain a to-be-trained DRC detection model, including: selecting a target learning model from several machine learning models based on the preset quantum chip design requirements, and determining the target learning model as the design rule checking model; building a distributed learning framework locally or at the target coordination node; the distributed learning framework has the ability to process encrypted data; based on the model initialization method, the model parameters of the design rule checking model are initialized on the distributed learning framework to obtain a to-be-trained DRC detection model. That is, first, according to the characteristics and requirements of quantum chip design, a suitable machine learning model (such as a neural network) is selected as the basic model for DRC detection (i.e., the above-mentioned design rule checking model), and then a distributed learning framework is built locally or at a preset coordination node. Here, the distributed learning framework supports multiple chip design parties to participate in model training simultaneously and can process encrypted data. Then, the model is initialized in the built distributed learning framework. Among them, the initialization steps include but are not limited to setting the parameters, structure, etc. of the model. For example, first, a parameterized function is selected , where are the parameters of the model (including but not limited to the weights and biases of the neural network), and x is the input data (in quantum chip design, this can be selected as the feature representation of the chip in the layout file). The initialization of the model usually involves randomly selecting or setting the initial values to obtain a to-be-trained DRC detection model.

[0057] Step S12: Obtain the model update parameters provided by each chip design party, and aggregate the model update parameters to obtain global model parameters; the model update parameters are the data obtained by each chip design party using the local chip design data to train the to-be-trained DRC detection model on the distributed learning framework locally.

[0058] In this embodiment, the process of obtaining the model update parameters by training the to-be-trained DRC detection model on the distributed learning framework by the chip design party includes: each chip design party encrypts the local quantum chip design data based on the preset public key encryption technology to generate target chip design data; each chip design party uses the target chip design data and the preset optimization algorithm. In the actual operation process, first, as Figure 2As shown, each chip designer first prepares their own quantum chip design data, including chip layout files (such as GDS (Geometry Data System) type files), design rule files, etc. In an online layout design tool developed by combining Vue + JavaScript + ElementUI, the rules for DRC detection to be performed are set or files are imported to achieve the preparation of the basic data for federated learning. Then, public key encryption technologies are used, including but not limited to RSA (Rivest-Shamir-Adleman, an asymmetric encryption algorithm based on number theory), ECC (Elliptic Curve Cryptography), etc., to encrypt the design data. During the encryption process, each chip designer in the online layout design tool uses their local private key to encrypt the data and sends the encrypted data and the corresponding public key to the central server or coordination node. In this way, only the chip designer with the corresponding private key can decrypt their own data, thus ensuring the security of the data during transmission.

[0059] Further, the model parameters of the DRC detection model to be trained on the distributed learning framework are updated locally to obtain the updated DRC detection model; it is determined whether the updated DRC detection model meets the preset model training end condition; the preset model training end condition is that the loss function value corresponding to the updated DRC detection model converges to a preset threshold; if the updated DRC detection model meets the preset model training end condition, the current updated parameters corresponding to the updated DRC detection model are obtained; the preset public key encryption technology is used to encrypt the current updated parameters to obtain the model update parameters. After each chip designer generates the encrypted data, the encrypted design data is used locally to train the DRC detection model. That is, in federated learning, each chip designer i trains the model on their local dataset Di. Assume that chip designer i uses the loss function to evaluate the performance of the model on their local data, and this loss function is a function of the model parameters and the local data Di. The goal of chip designer i is to find the that can minimize . Then, during the local training process, chip designer i will use an optimization algorithm (such as gradient descent) to update their local model parameters θi. The update rule can be expressed as: . Where is the learning rate, and is the gradient of the loss function Li with respect to . After training is completed, each chip designer will send the updated model parameters Before sending it to the central server, chip designer i encrypts it using the public key pki to obtain the encrypted parameters . Then, chip designer i sends to the central server. These parameter updates contain the learning results during the local training of the model. It should be noted here that this learning result refers to the model update parameters.

[0060] Then, obtain the model update parameters provided by each chip designer and perform an aggregation process on the model update parameters to obtain the global model parameters, including: obtaining the model update parameters provided by each chip designer and decrypting the model update parameters using the preset public key encryption technology to obtain the decrypted parameters; using the preset weighted average algorithm to aggregate the decrypted parameters to obtain the global model parameters. That is, after the central server or the coordination node receives the parameter updates from all chip designers, it performs decryption and aggregation operations. Through weighted average or other aggregation algorithms, the parameter updates of each chip designer are merged into a global model parameter update.

[0061] Among them, the chip design party uses the target chip design data and a preset optimization algorithm to update the model parameters of the to-be-trained DRC detection model on the distributed learning framework locally to obtain the updated DRC detection model, including: the chip design party locally identifies and extracts the features in the target chip design data that violate the predetermined rules of the chip design to obtain the target features; the chip design party inputs the target features into the to-be-trained DRC detection model on the distributed learning framework to train the to-be-trained DRC detection model, and at the same time uses the preset optimization algorithm to update the model parameters of the to-be-trained DRC detection model to obtain the updated DRC detection model. That is, during the training process, the model will learn and optimize according to the rule violation situations in the design data (such as too small wire spacing, shape mismatch, etc.). Specifically, it learns the data with rule violation situations in the design data to obtain the target features including the rule specification situations, and then uses the target features to train the to-be-trained DRC detection model. During the optimization process, the corresponding preset optimization algorithm is selected to update the model parameters of the to-be-trained DRC detection model to obtain the updated DRC detection model. Among them, the preset optimization algorithm includes but is not limited to the gradient descent algorithm. It should be noted here that different optimization algorithms can be selected for model training at different stages according to the actual situation. For example, the Adam (Adaptive Moment Estimation) algorithm can be used to train the to-be-trained DRC detection model at the initial stage of model training so that the model parameters of the to-be-trained DRC detection model can converge quickly, and the Stochastic Gradient Descent (SGD) can be used to refine the model parameters at the later stage of model training. And, according to the actual situation, Laplace noise (a random variable) can be added when the model parameters are updated by gradient, so as to help the updated DRC detection model have a better generalization effect.

[0062] Step S13: Send the global model parameters to each chip design party so that each chip design party can update the local DRC detection model based on the global model parameters to obtain the target DRC detection model, and use the target DRC detection model to detect the quantum chip design process to obtain the DRC detection result.

[0063] In this embodiment, the process by which the chip designer updates the local DRC detection model based on the global model parameters to obtain the target DRC detection model and uses the target DRC detection model to detect the quantum chip design process to obtain the DRC detection result includes: The chip designer obtains the global model parameters and uses the global model parameters to update the updated DRC detection model to obtain the target DRC detection model; uses the target DRC detection model to detect the quantum chip layout design to obtain the DRC detection result; The quantum chip layout design is the data obtained by encrypting the changed local quantum chip design data using the preset public key encryption technology. Specifically, each chip designer uses the updated DRC detection model to perform encrypted detection on the new or modified quantum chip design. During the detection process, the design data remains encrypted, and only the necessary calculation results (such as rule violation situations) are decrypted and transmitted. In this way, the data security of each chip designer can be guaranteed.

[0064] In this embodiment, after using the target DRC detection model to detect the quantum chip layout design to obtain the DRC detection result, it further includes: When there is an abnormal design situation in the DRC detection result, decrypt the quantum chip layout design to obtain the chip design abnormal position and abnormal type; display the chip design abnormal position and abnormal type in the preset front-end DRC function error reporting column, and perform function locking on the quantum chip layout design, so that the chip designer can correct the quantum chip layout design based on the chip design abnormal position and abnormal type. That is, as Figure 3 shown, the DRC detection result is fed back to each chip designer. If there is a rule violation in the design, specific violation position and type information are provided. After the front-end obtains the component position information in the provided chip layout and searches for it, if found, it is prompted in the DRC function error reporting column. If no correction is made, this layout is not allowed to perform functions such as simulation, so that the chip designer can make modifications and optimizations.

[0065] In this embodiment, after the chip designer corrects the quantum chip layout design based on the abnormal position and type of the chip design, the following steps are further included: each chip designer respectively obtains the optimized design data obtained after correcting the quantum chip layout design, and updates the local quantum chip design data based on the optimized design data to obtain new local quantum chip design data; jump to the step where each chip designer encrypts the local quantum chip design data based on the preset public key encryption technology to generate the target chip design data until new global model parameters are obtained. In the actual operation process, each chip designer optimizes and modifies the quantum chip design according to the DRC detection result to solve the rule violation problem. After the modification, the detection is performed again. After passing, the error prompt in the DRC error column disappears, and the layout can be simulated. Then, the optimized design data is re-added to the training process for a new round of model training and parameter update. In this way, through multiple iterative trainings, the accuracy and efficiency of the DRC detection can be continuously improved. In addition, the present invention regularly evaluates and validates the DRC detection model to ensure its effectiveness and reliability in actual applications. An independent test data set can be used to evaluate the performance of the model during the evaluation process.

[0066] In this embodiment, a distributed learning framework is built, and the design rule checking model is initialized on the distributed learning framework to obtain the DRC detection model to be trained; the model update parameters provided by each chip designer are obtained, and the model update parameters are aggregated to obtain the global model parameters; the model update parameters are data obtained by each chip designer training the DRC detection model to be trained on the distributed learning framework respectively using the local chip design data; the global model parameters are sent to each chip designer so that each chip designer updates the local DRC detection model based on the global model parameters to obtain the target DRC detection model, and uses the target DRC detection model to detect the quantum chip design process to obtain the DRC detection result. That is, through the distributed learning and data encryption technology, efficient DRC checking is achieved while protecting the privacy of the design data, the operation process is simplified, and the efficiency of the design rule checking of the layout is improved.

[0067] As can be seen from the above technical solution, the present invention constructs a distributed framework, enabling each chip design party to utilize this distributed framework to simultaneously conduct collaborative training and model optimization, that is, to achieve parallel computing and accelerate the training process using the federated learning framework, and promoting collaborative cooperation among different chip design parties by utilizing the distributed framework, expanding the scale and diversity of design data, and improving the accuracy of DRC inspection. In this way, the DRC detection method for the quantum chip design process based on federated learning can achieve efficient DRC inspection while protecting the privacy of design data, improving the accuracy and efficiency of quantum chip design. This not only reduces the workload of designers but also improves the reliability and maintainability of the design.

[0068] Reference Figure 4 , the embodiment of the present application also correspondingly discloses a DRC detection device for the quantum chip design process, which is applied to a central server and includes:

[0069] A model initialization module 11, configured to build a distributed learning framework and initialize a design rule check model on the distributed learning framework to obtain a to-be-trained DRC detection model;

[0070] A model training module 12, configured to obtain the model update parameters provided by each chip design party and perform aggregation processing on the model update parameters to obtain global model parameters; the model update parameters are data obtained by each chip design party using local chip design data to separately train the to-be-trained DRC detection model on the distributed learning framework;

[0071] A model application module 13, configured to send the global model parameters to each chip design party, so that each chip design party updates the local DRC detection model based on the global model parameters to obtain a target DRC detection model, and uses the target DRC detection model to detect the quantum chip design process to obtain a DRC detection result.

[0072] It can be seen that in this embodiment, by constructing a distributed framework, each chip design party can utilize this distributed framework to simultaneously conduct collaborative training and model optimization, that is, to achieve parallel computing and accelerate the training process using the federated learning framework, and promoting collaborative cooperation among different chip design parties by utilizing the distributed framework, expanding the scale and diversity of design data, and improving the accuracy of DRC inspection. Compared with common simulation software, the DRC detection method for the quantum chip design process based on federated learning can achieve efficient DRC inspection while protecting the privacy of design data, improving the accuracy and efficiency of quantum chip design. This not only reduces the workload of designers but also improves the reliability and maintainability of the design.

[0073] Furthermore, the embodiment of the present application also discloses an electronic deviceFigure 5 It is a structural diagram of an electronic device shown according to an exemplary embodiment. The content in the figure should not be regarded as any limitation on the scope of use of this application. The electronic device may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the DRC detection method for the quantum chip design process disclosed in any of the foregoing embodiments. Additionally, the electronic device in this embodiment may specifically be an electronic computer.

[0074] In this embodiment, the power supply 23 is used to provide operating voltages for each hardware device on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows is any communication protocol applicable to the technical solution of this application, and no specific limitation is imposed on it here; the input / output interface 25 is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application requirements, and no specific limitation is made here.

[0075] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, a random access memory, a magnetic disk, or an optical disc, etc. The resources stored thereon may include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0076] Among them, the operating system 221 is used to manage and control each hardware device on the electronic device and the computer program 222, and it can be Windows Server, Netware, Unix, Linux, etc. The computer program 222, in addition to including a computer program capable of completing the DRC detection method for the quantum chip design process executed by the electronic device disclosed in any of the foregoing embodiments, may further include a computer program capable of completing other specific tasks.

[0077] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the DRC detection method for the quantum chip design process disclosed above. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be elaborated here.

[0078] Furthermore, this application also discloses a computer program product, including a computer program / instructions; wherein, when the computer program / instructions are executed by a processor, they implement the alarm aggregation method disclosed above. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be elaborated here.

[0079] In the present specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method section.

[0080] Those skilled in the art can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of the examples have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0081] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be directly implemented by hardware, software modules executed by a processor, or a combination of the two. The software modules can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.

[0082] Finally, it should also be noted that in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0083] The above has introduced the technical solution provided by this application in detail. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application; at the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. A DRC detection method for a quantum chip design process, characterized in that: Applied to the central server, including: Building a distributed learning framework, and initializing a design rule checking model on the distributed learning framework to obtain a DRC detection model to be trained; Obtaining model update parameters provided by each chip designer, and aggregating the model update parameters to obtain global model parameters; the model update parameters are data obtained by each chip designer using local chip design data to locally train the DRC detection model to be trained on the distributed learning framework; The global model parameters are sent to each of the chip designers, so that each of the chip designers updates the local DRC detection model based on the global model parameters to obtain a target DRC detection model, and uses the target DRC detection model to detect the quantum chip design process to obtain a DRC detection result.

2. The DRC detection method for quantum chip design process according to claim 1, characterized in that: The step of building a distributed learning framework and initializing a design rule checking model on the distributed learning framework to obtain a DRC detection model to be trained includes: Selecting a target learning model from a number of machine learning models based on preset quantum chip design requirements, and determining the target learning model as a design rule checking model; Building a distributed learning framework locally or at a target coordination node; the distributed learning framework is capable of processing encrypted data; Based on the model initialization method, the model parameters of the design rule checking model are initialized and set on the distributed learning framework to obtain the DRC detection model to be trained.

3. The DRC detection method for quantum chip design process according to claim 1 or 2, characterized in that: The process of training the DRC detection model to be trained on the distributed learning framework by the chip design party to obtain the model update parameters includes: Each of the chip designers encrypts the local quantum chip design data based on a preset public key encryption technology to generate target chip design data; Each of the chip designers uses the target chip design data and a preset optimization algorithm to locally update the model parameters of the to-be-trained DRC detection model on the distributed learning framework to obtain an updated DRC detection model; Determine whether the updated DRC detection model meets a preset model training end condition; the preset model training end condition is that the loss function value corresponding to the updated DRC detection model converges to a preset threshold; If the updated DRC detection model meets the preset model training end condition, then obtaining the current update parameters corresponding to the updated DRC detection model; Using the preset public key encryption technology to encrypt the current update parameter to obtain the model update parameter; Accordingly, the acquiring of the model update parameters provided by each chip designer and aggregating the model update parameters to obtain the global model parameters includes: Obtaining model update parameters provided by each chip designer, and decrypting the model update parameters using the preset public key encryption technology to obtain decrypted parameters; The decrypted parameters are aggregated using a preset weighted average algorithm to obtain global model parameters.

4. The DRC detection method for quantum chip design process according to claim 3, characterized in that: The chip designer uses the target chip design data and a preset optimization algorithm to locally update the model parameters of the to-be-trained DRC detection model on the distributed learning framework to obtain an updated DRC detection model, including: The chip designer locally identifies and extracts features in the target chip design data that violate predetermined chip design rules to obtain target features; The chip designer inputs the target features into the DRC detection model to be trained on the distributed learning framework to train the DRC detection model to be trained, and simultaneously uses a preset optimization algorithm to update the model parameters of the DRC detection model to be trained to obtain an updated DRC detection model.

5. The DRC detection method for quantum chip design process according to claim 3, characterized in that: The chip designer updates the local DRC detection model based on the global model parameters to obtain a target DRC detection model, and uses the target DRC detection model to detect the quantum chip design process to obtain a DRC detection result, including: The chip designer obtains the global model parameters, and uses the global model parameters to update the updated DRC detection model to obtain a target DRC detection model; The target DRC detection model is used to detect the quantum chip layout design to obtain a DRC detection result; the quantum chip layout design is data obtained by encrypting the changed local quantum chip design data using the preset public key encryption technology.

6. The DRC detection method for quantum chip design process according to claim 5, characterized in that: After the target DRC detection model is used to detect the quantum chip layout design to obtain the DRC detection result, the method further includes: When there is an abnormal design in the DRC test result, the quantum chip layout design is decrypted to obtain the abnormal position and abnormal type of the chip design; The abnormal position of the chip design and the abnormal type are displayed in the preset front-end DRC function error column, and the function of the quantum chip layout design is blocked so that the chip designer can correct the quantum chip layout design based on the abnormal position of the chip design and the abnormal type.

7. The DRC detection method for quantum chip design process according to claim 6, characterized in that: After the chip designer corrects the quantum chip layout design based on the chip design abnormality position and the abnormality type, the method further includes: Each chip designer obtains optimized design data obtained after error correction of the quantum chip layout design, and updates the local quantum chip design data based on the optimized design data to obtain new local quantum chip design data; Jump to the step in which each chip design party encrypts the local quantum chip design data based on a preset public key encryption technology and then generates target chip design data until new global model parameters are obtained.

8. A DRC detection device for a quantum chip design process, characterized in that: Applied to the central server, including: A model initialization module, used for building a distributed learning framework and initializing a design rule checking model on the distributed learning framework to obtain a DRC detection model to be trained; A model training module is used to obtain model update parameters provided by each chip designer, and aggregate the model update parameters to obtain global model parameters; the model update parameters are data obtained by each chip designer using local chip design data to train the DRC detection model to be trained on the distributed learning framework locally; The model application module is used to send the global model parameters to each of the chip designers, so that each of the chip designers updates the local DRC detection model based on the global model parameters to obtain a target DRC detection model, and uses the target DRC detection model to detect the quantum chip design process to obtain a DRC detection result.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the DRC detection method for the quantum chip design process as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the DRC detection method for the quantum chip design process as claimed in any one of claims 1 to 7 are implemented.

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