Wave trap comprising three switched capacitor arrays

Abstract

The invention provides a wave trap comprising three switched capacitor arrays, and relates to the field of microelectronics and solid-state electronics. The circuit is applied to the fields of microelectronics and solid-state electronics, in particular to low-noise and low-offset circuit systems in the fields. According to the switched capacitor wave trap, a large resistor and a large capacitor are not needed to adjust the wave trapping frequency, only corresponding clock signals need to be added, filtering can be achieved at the specified frequency, and static power consumption does not exist. The device has the advantages of small area, low power consumption, simple structure, high PVT resistance and the like. Simulation results show that the low-frequency gain of the wave trap is 404.497 mdB, the high-frequency notch gain of the wave trap is-91.102 dB, harmful high-frequency components at specific frequencies in signals can be well filtered out, and useful low-frequency signal components are reserved.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics and solid state electronics, and particularly to a novel notch filter including three switched capacitor arrays. Background Art

[0002] In recent years, with the rapid development of the integrated circuit field, while pursuing high speed, low power consumption and miniaturization, the circuit also puts forward higher requirements for indicators such as noise and offset. Filters are usually used to filter out harmful signal components in certain specific frequency bands. As a basic module in CMOS signal processing circuits, filters play a crucial role in filtering noise and interference, extracting specific frequency components, and signal analysis and processing. In a low-noise and low-offset circuit system, a chopper modulation circuit and a low-pass filter can eliminate the low-frequency 1 / f noise and offset of the circuit. The chopper modulation circuit separates the useful signal from the low-frequency 1 / f noise and offset in the frequency domain through modulation and demodulation, so that the useful signal remains in the low frequency, while the low-frequency 1 / f noise and offset are modulated to the chopping frequency. Finally, a low-pass filter with a bandwidth lower than the chopping frequency can be used to filter out the low-frequency 1 / f noise and offset. Using a common RC passive filter requires using large resistors and large capacitors to ensure an appropriate bandwidth, but this will consume a large amount of chip area. If an active RC filter is used, a third-order or even fourth-order filter is required to achieve an ideal filtering effect, and the circuit is extremely complex. Moreover, the bandwidths of the former and the latter are easily affected by PVT fluctuations, and neither of them is the best choice for a chopper system. Therefore, the present invention designs a notch filter including three switched capacitor arrays adapted to a chopper system.

[0003] Currently, relevant literatures have proposed the theoretical basis and design ideas of switched capacitor notch filters:

[0004] Literature 1: K. Afifah, M. Arijal, N. Retdian and T. Shima, "Second-Order N-path Notch Filter for Hum Noise Suppression," 2018 International Symposium on Electronics and Smart Devices (ISESD), Bandung, Indonesia, 2018, pp. 1-4, doi: 10.1109 / ISESD.2018.8605468. Literature 1 provides Figure 1 the basic structure of the shown traditional N-path switched capacitor notch filter and calculates the relationship between the notch depth H N and the number of paths N as The larger the value of the number of paths N, the deeper the notch depth. When the frequency of the input signal is equal to the clock frequency, each capacitor only samples a specific part of the input signal for storage. Since the signal transmission from input to output is reduced, the circuit will have a notch characteristic. The drawback of this structure is that the value of the resistor R must be large enough (1 TΩ) to ensure sufficient notch depth. Document 2: Sun Angbo. Research and Design of High-Precision Hall Sensors [D]. Xidian University, 2020. DOI: 10.27389 / d.cnki.gxadu.2020.000654. Document 2 designed Figure 2 the switched-capacitor notch filter shown. This notch filter includes a fully differential amplifier and two switched-capacitor arrays. The notch frequency can be adjusted and controlled by the clock to remove the harmful components in the signal. According to the conclusion in Document 1, the notch depth of this notch filter can be increased by continuously increasing the number of switched-capacitor arrays. Summary of the Invention

[0005] In view of the characteristic that the chopper circuit modulates low-frequency 1 / f noise and offset to the chopping frequency in a low-noise and low-offset system, the present invention designs a notch filter including three switched-capacitor arrays, which can cooperate with the chopper circuit to eliminate low-frequency 1 / f noise and offset.

[0006] The technical solution of the present invention is: a notch filter including three switched-capacitor arrays, characterized in that: the notch filter includes: three groups of switched-capacitor arrays with fully differential input and output, input ports V INP , V INN , differential output ports V OP , V ON ; each group of switched-capacitor arrays includes two input ports and two output ports, and the two input ports of each group of switched-capacitor arrays are correspondingly connected to the input ports V INP , V INN , and the two output ports of each group of switched-capacitor arrays are correspondingly connected to the differential output ports V OP , V ON .

[0007] Furthermore, the three groups of switched-capacitor arrays with fully differential input and output have exactly the same structure. Each switched-capacitor array includes two switched networks with the same structure. Each switched network includes an input port, an output port, and a common-mode voltage input port V CM ; the input port of one switched network is connected to the input port V INP , the output port is connected to the output port V OP , and the input port of the other switched network is connected to the input port V INN , and the output port is connected to the output port V ON .

[0008] Further, each of the switch networks includes: eight switches S1 - S8 respectively, and two capacitors C1 and C2 respectively. The input port is divided into two paths. One path is successively connected in series with switch S1, capacitor C1, switch S2 and then connected to the common - mode voltage input port V CM , and the other path is successively connected in series with switch S7, capacitor C2, switch S8 and then connected to the common - mode voltage input port V CM . The common node of switch S1 and capacitor C1 and the common node of switch S7 and capacitor C2 are successively connected in series with switch S3 and switch S5. The common node of switch S3 and switch S5 serves as the output port; the common node of capacitor C1 and switch S2 and the common node of capacitor C2 and switch S8 are successively connected in series with switch S4 and switch S6. The common node of switch S4 and switch S6 also serves as the common - mode voltage input port V CM .

[0009] Further, the switches S1 - S8 have exactly the same structure and are CMOS complementary switches; the capacitors C1 and C2 are exactly the same.

[0010] A control method for a switched - capacitor notch filter with adjustable notch frequency. In this method, the numbers of the switches in the first switch network of the first switched - capacitor array are successively: S1, S2, S3, S4, S5, S6, S7, S8, and the capacitors are successively numbered as: C1, C2; the numbers of the switches at the corresponding positions of the second switch network relative to the switches S1, S2, S3, S4, S5, S6, S7, S8 in the first switch network are successively: S9, S10, S11, S12, S13, S14, S15, S16; the numbers of the capacitors at the corresponding positions of the second switch network relative to the capacitors C1, C2 in the first switch network are successively: C3, C4;

[0011] The numbers of the switches at the corresponding positions of the second switched - capacitor array relative to the switches S1, S2... S15, S16 in the first switched - capacitor array are successively: S17, S18... S31, S32; the numbers of the capacitors at the corresponding positions of the second switched - capacitor array relative to the capacitors C1, C2, C3, C4 in the first switched - capacitor array are successively: C5, C6, C7, C8;

[0012] The numbers of the switches at the corresponding positions of the third switched - capacitor array relative to the switches S1, S2... S15, S16 in the first switched - capacitor array are successively: S33, S34... S47, S48; the numbers of the capacitors at the corresponding positions of the second switched - capacitor array relative to the capacitors C1, C2, C3, C4 in the first switched - capacitor array are successively: C9, C10, C11, C12;

[0013] The switches controlled by timing CLK1: S2, S3, S5, S8, S10, S11, S13, S16; the switches controlled by timing CLK2: S18, S19, S21, S24, S26, S27, S32; the switches controlled by timing CLK3: S34, S35, S37, S40, S42, S43, S45, S48; the switches controlled by timing CLK4: S17, S20, S30, S31, S38, S39, S41, S44; the switches controlled by timing CLK5: S6, S7, S9, S12, S33, S36, S46, S47; the switches controlled by timing CLK6: S1, S4, S14, S15, S22, S23, S25, S28;

[0014] The specific control method is as follows:

[0015] Step 1: The first switched-capacitor array is in the sampling state when CLK5 and CLK6 are at high level, and at this time CLK1 is at low level; when CLK5 is at high level, capacitor C2 is connected across V INP and V CM to sample V INP , capacitor C3 is connected across V INN and V CM to sample V INN , and the two ends of capacitor C1 and capacitor C4 are open; when CLK6 is at high level, capacitor C1 is connected across V INP and V CM to sample V INP , capacitor C4 is connected across V INN and V CM to sample V INN , and the two ends of capacitor C2 and capacitor C3 are open; when the clock signal CLK1 is at high level and CLK2 and CLK3 are at low level, the first switched-capacitor array is in the output state, and at this time capacitor C1 and C2 are connected across V INP and V CM , capacitor C3 and C4 are connected across V INN and V CM , and the low-frequency DC signal V A is output;

[0016] Step 2: The second switched-capacitor array is in the sampling state when CLK6 and CLK4 are at high level, and at this time CLK2 is at low level; when CLK6 is at high level, capacitor C6 is connected across V INP and V CM to sample V INP , capacitor C7 is connected across V INN and V CM to sample V INNSampling is performed with the two ends of capacitor C5 and capacitor C8 open-circuited; when CLK4 is at a high level, capacitor C5 is connected across V INP and V CM to sample V INP ; capacitor C8 is connected across V INN and V CM to sample V INN ; the two ends of capacitor C6 and capacitor C7 are open-circuited; when the clock signal CLK2 is at a high level and CLK1 and CLK3 are at low levels, the second switched-capacitor array is in the output state. At this time, capacitor C5 and C6 are connected across V INP and V CM ; capacitor C7 and C8 are connected across V INN and V CM ; and a low-frequency DC signal V A is output;

[0017] Step 3: The third switched-capacitor array is in the sampling state when CLK4 and CLK5 are at high levels, and at this time CLK3 is at a low level; when CLK4 is at a high level, capacitor C10 is connected across V INP and V CM to sample V INP ; capacitor C11 is connected across V INN and V CM to sample V INN ; the two ends of capacitor C9 and capacitor C12 are open-circuited; when CLK5 is at a high level, capacitor C9 is connected across V INP and V CM to sample V INP ; capacitor C12 is connected across V INN and V CM to sample V INN ; the two ends of capacitor C10 and capacitor C11 are open-circuited; when the clock signal CLK3 is at a high level and CLK1 and CLK2 are at low levels, the third switched-capacitor array is in the output state. At this time, capacitor C9 and C10 are connected across V INP and V CM ; capacitor C11 and C12 are connected across V INN and V CM ; and a low-frequency DC signal V A is output;

[0018] Step 4: Return to Step 1.

[0019] The beneficial effects of the present invention are as follows: Compared with the RC passive filter, this circuit does not require large capacitors and large resistors to control the frequency characteristics of the circuit, saving chip area. Compared with the RC active filter, this circuit is a passive circuit, does not generate static power consumption, and has a relatively simple structure. Finally, the notch frequency of this notch filter can be accurately controlled by the clock and notch at the specified frequency, and the notch frequency is not easily affected by PVT fluctuations. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 FIG. is the basic structure and clock timing diagram of a traditional N-path switched-capacitor notch filter.

[0021] Figure 2 FIG. is the notch filter structure and clock timing diagram including two switched-capacitor arrays.

[0022] Figure 3 FIG. is the overall structure diagram of the switched-capacitor notch filter proposed by the present invention.

[0023] Figure 4 FIG. is the specific circuit diagram of the switched-capacitor notch filter proposed by the present invention.

[0024] Figure 5 FIG. is the timing diagram of the input signal and the clock proposed by the present invention.

[0025] Figure 6 FIG. is the baseband characteristic simulation diagram of the switched-capacitor notch filter proposed by the present invention.

[0026] Figure 7 FIG. is the notch characteristic simulation diagram of the switched-capacitor notch filter proposed by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] As shown in Figure 3 , three groups of switched-capacitor arrays are connected to differential input V INP , V INN and differential output V OP , V ON . As shown in Figure 4 , the first switched-capacitor array includes 4 capacitors C1 - C4 and 16 switches S1 - S16; the second switched-capacitor array includes 4 capacitors C5 - C8 and 16 switches S17 - S32; the third switched-capacitor array includes 4 capacitors C9 - C12 and 16 switches S33 - S48. Among them, V CM is the DC common-mode signal. The timing relationship between the input signal and the clock signal is as shown in Figure 5 . The input square-wave signal is V A ± V B , where V A is the useful low-frequency DC signal, and V B is the harmful high-frequency AC signal, and its frequency is fB CLK1, CLK2, and CLK3 are clock signals with a duty cycle of 1 / 3, used to control the output of the notch filter. CLK4, CLK5, and CLK6 are clock signals with a duty cycle of 1 / 12, used to control the sampling of the notch filter. CLK1 - CLK6 have the same period. There are 12 capacitors C1 - C12 and 48 switches S1 - S48; the first switched-capacitor array includes capacitors C1 - C4 and switches S1 - S16. The two ends of capacitor C1 are respectively connected to V INP and V CM through switches S1 (controlled by CLK6) and S2 (controlled by CLK1), and connected to V OP and V CM through switches S3 (controlled by CLK1) and S4 (controlled by CLK6); the two ends of capacitor C2 are respectively connected to V OP and V CM through switches S5 (controlled by CLK1) and S6 (controlled by CLK5), and connected to V INP and V CM through switches S7 (controlled by CLK5) and S8 (controlled by CLK1); the two ends of capacitor C3 are respectively connected to V INN and V CM through switches S9 (controlled by CLK5) and S10 (controlled by CLK1), and connected to V ON and V CM through switches S11 (controlled by CLK1) and S12 (controlled by CLK5); the two ends of capacitor C4 are respectively connected to V ON and V CM through switches S13 (controlled by CLK1) and S14 (controlled by CLK6), and connected to V INN and V CM through switches S15 (controlled by CLK6) and S16 (controlled by CLK1). The second switched-capacitor array includes capacitors C5 - C8 and switches S17 - S32. The two ends of capacitor C5 are respectively connected to V INP and V CM through switches S17 (controlled by CLK4) and S18 (controlled by CLK2), and connected to V OP and V CM through switches S19 (controlled by CLK2) and S20 (controlled by CLK4); the two ends of capacitor C6 are respectively connected to V OP and V CM through switches S21 (controlled by CLK2) and S22 (controlled by CLK6), and connected to V INP and V CM through switches S23 (controlled by CLK6) and S24 (controlled by CLK2); the two ends of capacitor C7 are respectively connected to V INN and VCM are connected. Through switches S27 (controlled by CLK2) and S28 (controlled by CLK6), they are connected to V ON and V CM are connected; both ends of capacitor C4 are respectively connected to V through switches S29 (controlled by CLK2) and S30 (controlled by CLK4) ON and V CM are connected, and through switches S31 (controlled by CLK4) and S32 (controlled by CLK2), they are connected to V INN and V CM are connected. The third switched-capacitor array includes capacitors C9 - C12 and switches S33 - S48. Both ends of capacitor C9 are respectively connected to V through switches S33 (controlled by CLK5) and S34 (controlled by CLK3) INP and V CM are connected, and through switches S35 (controlled by CLK3) and S36 (controlled by CLK5), they are connected to V OP and V CM are connected; both ends of capacitor C10 are respectively connected to V through switches S37 (controlled by CLK3) and S38 (controlled by CLK4) OP and V CM are connected, and through switches S39 (controlled by CLK4) and S40 (controlled by CLK3), they are connected to V INP and V CM are connected; both ends of capacitor C11 are respectively connected to V through switches S41 (controlled by CLK4) and S42 (controlled by CLK3) INN and V CM are connected, and through switches S43 (controlled by CLK3) and S44 (controlled by CLK4), they are connected to V ON and V CM are connected; both ends of capacitor C12 are respectively connected to V through switches S45 (controlled by CLK3) and S46 (controlled by CLK5) ON and V CM are connected, and through switches S47 (controlled by CLK5) and S48 (controlled by CLK3), they are connected to V INN and V CM are connected;

[0028] Capacitances of the capacitors C1 - C12 are exactly the same, and switches S1 - S48 are CMOS complementary switches with exactly the same size.

[0029] Taking the first switched-capacitor array as an example, the operating principle of this switched-capacitor notch filter is described. When CLK1 is at a high level, CLK2 and CLK3 are at low levels, and CLK5 and CLK6 are also at low levels. Capacitors C1 and C2 are connected in parallel across V OP and V CM , and capacitors C3 and C4 are connected in parallel across V ON and VCM Between them, at this time V OP and V ON Can be respectively expressed as

[0030]

[0031] In formula (1) and formula (2), V C1 , V C2 , V C3 , V C4 Respectively represent the voltages across the two ends of capacitors C1, C2, C3, and C4.

[0032] When CLK5 is at a high level, CLK1 and CLK6 are at low levels. Capacitor C2 is connected across V INP and V CM Between them, capacitor C3 is connected across V INN and V CM Between them, the two ends of capacitors C1 and C4 are open. At this time, the inputs V INP_CLK5 and V INP_CLK5 Have the following relationship

[0033] V INP_CLK5 -V INN_CLK5 =V A -V B (3)

[0034] The voltages across the two ends of capacitors C2 and C3 can be expressed as

[0035] V C2 =V INP_CLK5 -V CM (4)

[0036] V C3 =V INN_CLK5 -V CM (5)

[0037] When CLK6 is at a high level, CLK1 and CLK5 are at low levels. Capacitor C1 is connected across V INP and V CM Between them, capacitor C4 is connected across V INN and V CM Between them, the two ends of capacitors C2 and C3 are open. At this time, the inputs V INP_CLK6 and V INP_CLK6 Have the following relationship

[0038] V INP_CLK6 -V INN_CLK6 =V A +V B (6)

[0039] The voltages across the two ends of capacitors C1 and C4 can be expressed as

[0040] V C1 = V INP_CLK6 - V CM (7)

[0041] V C4 = V INP_CLK6 - V CM (8)

[0042] Substituting formulas (3) - (8) into formulas (1) and (2) gives

[0043]

[0044] Similarly, when CLK2 is high, CLK1 and CLK3 are low, and when CLK3 is high, CLK1 and CLK2 are low, the output of the switched - capacitor notch filter can be expressed by formula (11). Formula (11) shows that the useful low - frequency DC signal V A can pass through the notch filter, while the harmful high - frequency AC signal V B is filtered out, that is, the notch frequency is f B .

[0045] As Figure 6 shown, in the baseband characteristic simulation diagram of the switched - capacitor notch filter, the gain of the low - frequency signal is 404.497 mdB. This result shows that the gain of the low - frequency signal is approximately equal to 1 and can pass through the notch filter.

[0046] As Figure 7 shown, in the notch characteristic simulation diagram of the switched - capacitor notch filter, the gains at frequencies of 1 MHz, 2 MHz, 3 MHz, and 4 MHz are - 91.102 dB, - 90.489 dB, - 87.18 dB, and - 81.785 dB respectively. This result shows that the notch filter can suppress high - frequency signals at 1 MHz and multiples of 1 MHz.

Claims

1. A notch filter comprising three switched capacitor arrays, characterized in that: The notch filter includes: three sets of fully differential input and output switch capacitor arrays, the input port V INP ,V INN , differential output port V OP , V ON Each switch capacitor array comprises two input ports and two output ports, and the two input ports of each switch capacitor array are connected to the input port V INP ,V INN , the two output ports of each switch capacitor array are connected to the differential output port V OP , V ON .

2. A notch filter comprising three switched capacitor arrays as claimed in claim 1, characterized in that: The three groups of fully differential input and output switch capacitor arrays have the same structure. Each switch capacitor array includes two switch networks with the same structure. Each switch network includes an input port, an output port, and a common mode voltage input port V CM ; One of the switch network input ports is connected to the input port V INP , the output port is connected to the output port V OP , the input port of another switch network is connected to the input port V INN , the output port is connected to the output port V ON .

3. A notch filter comprising three switched capacitor arrays as claimed in claim 2, characterized in that: Each switch network includes: 8 switches S1-S8, two capacitors C1 and C2, and the input port is divided into two paths, one of which is connected in series with switch S1, capacitor C1, switch S2 and then connected to the common mode voltage input port V CM The other path is connected in series with switch S7, capacitor C2, switch S8 and then connected to the common mode voltage input port V CM , the common node of the switch S1 and the capacitor C1 and the common node of the switch S7 and the capacitor C2 are connected in series with the switch S3 and the switch S5 in sequence, and the common node of the switch S3 and the switch S5 is used as the output port; the common node of the capacitor C1 and the switch S2 and the common node of the capacitor C2 and the switch S8 are connected in series with the switch S4 and the switch S6 in sequence, and the common node of the switch S4 and the switch S6 is also used as the common mode voltage input port V CM .

4. A notch filter comprising three switched capacitor arrays as claimed in claim 3, characterized in that: The switches S1 - S8 have the same structure and are CMOS complementary switches; the capacitors C1 and C2 are the same.

5. A control method for a switched capacitor trap with adjustable trap frequency as claimed in claim 3, wherein the switches in the first switch network in the first switch capacitor array are numbered in sequence: S1, S2, S3, S4, S5, S6, S7, S8, and the capacitors are numbered in sequence: C1, C2; the positions of the second switch network corresponding to the switches S1, S2, S3, S4, S5, S6, S7, S8 in the first switch network are numbered in sequence: S9, S10, S11, S12, S13, S14, S15, S16; the positions of the second switch network corresponding to the capacitors C1, C2 in the first switch network are numbered in sequence: C3, C4; The positions of the second switch capacitor array corresponding to the switches S1, S2, ..., S15, S16 in the first switch capacitor array are numbered as S17, S18, ..., S31, S32 in sequence; the positions of the second switch capacitor array corresponding to the capacitors C1, C2, C3, C4 in the first switch capacitor array are numbered as C5, C6, C7, C8 in sequence; The positions of the third switch capacitor array corresponding to the switches S1, S2, ..., S15, S16 in the first switch capacitor array are numbered as follows: S33, S34, ..., S47, S48; the positions of the second switch capacitor array corresponding to the capacitors C1, C2, C3, C4 in the first switch capacitor array are numbered as follows: C9, C10, C11, C12; The timing CLK1 controls switches: S2, S3, S5, S8, S10, S11, S13, S16; the timing CLK2 controls switches: S18, S19, S21, S24, S26, S27, S32; the timing CLK3 controls switches: S34, S35, S37, S40, S42, S43, S45, S48; the timing CLK4 controls switches: S17, S20, S30, S31, S38, S39, S41, S44; the timing CLK5 controls switches: S6, S7, S9, S12, S33, S36, S46, S47; the timing CLK6 controls switches: S1, S4, S14, S15, S22, S23, S25, S28; The specific control methods are: Step 1: The first switched capacitor array is in a sampling state when CLK5 and CLK6 are high, and CLK1 is low; when CLK5 is high, capacitor C2 is connected across V INP and V CM Between V INP For sampling, capacitor C3 is connected across V INN and V CM Between V INN Sampling is performed, and the two ends of capacitor C1 and capacitor C4 are open; when CLK6 is high, capacitor C1 is connected across V INP and V CM Between V INP For sampling, capacitor C4 is connected across V INN and V CM Between V INN Sampling is performed, and both ends of capacitor C2 and capacitor C3 are open; when the clock signal CLK1 is high level, CLK2 and CLK3 are low level, the first switch capacitor array is in the output state, at this time, capacitors C1 and C2 are connected across V INP and V CM Capacitors C3 and C4 are connected across V INN and V CM Output low frequency DC signal V A ; Step 2: The second switched capacitor array is in the sampling state when CLK6 and CLK4 are high, and CLK2 is low; when CLK6 is high, capacitor C6 is connected across V INP and V CM Between V INP For sampling, capacitor C7 is connected across V INN and V CM Between V INN Sampling is performed, and both ends of capacitor C5 and capacitor C8 are open; when CLK4 is high, capacitor C5 is connected across V INP and V CM Between V INP For sampling, capacitor C8 is connected across V INN and V CM Between V INN Sampling is performed, and both ends of capacitor C6 and capacitor C7 are open; when the clock signal CLK2 is high and CLK1 and CLK3 are low, the second switch capacitor array is in the output state, and capacitors C5 and C6 are connected across V INP and V CM Capacitors C7 and C8 are connected across V INN and V CM Output low frequency DC signal V A ; Step 3: The third switched capacitor array is in a sampling state when CLK4 and CLK5 are high, and CLK3 is low; when CLK4 is high, capacitor C10 is connected across V INP and V CM Between V INP For sampling, capacitor C11 is connected across V INN and V CM Between V INN Sampling is performed, and the two ends of capacitor C9 and capacitor C12 are open; when CLK5 is high, capacitor C9 is connected across V INP and V CM Between V INP For sampling, capacitor C12 is connected across V INN and V CM Between V INN Sampling is performed, and both ends of capacitor C10 and capacitor C11 are open; when the clock signal CLK3 is high and CLK1 and CLK2 are low, the third switch capacitor array is in the output state, and capacitors C9 and C10 are connected across V INP and V CM Capacitors C11 and C12 are connected across V INN and V CM Output low frequency DC signal V A ; Step 4: Return to step 1.

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