Power-on reset circuit

Abstract

The invention discloses a power-on reset circuit, and relates to the technical field of integrated circuits, in order to eliminate static power consumption of the power-on reset circuit and reduce power consumption of the power-on reset circuit, the power-on reset circuit comprises a discharge delay circuit, a current mirror circuit and a buffer circuit; the discharge delay circuit comprises a capacitor and an NMOS (N-channel Metal Oxide Semiconductor) tube M4, and the NMOS tube M4 is used for discharging the capacitor; the current mirror image circuit comprises an NMOS tube M2, an NMOS tube M3 and a PMOS tube M9. The grid electrode of the NMOS tube M2 and the grid electrode of the PMOS tube M9 are respectively connected with the output end of the buffer circuit; the grid electrode of the NMOS tube M3 is respectively connected with the source electrode of the PMOS tube M9, the drain electrode of the NMOS tube M2 and the grid electrode of the NMOS tube M4; the current mirror image circuit is used for turning off the NMOS tube M2 after the reset signal is ended, and pulling up the drain electrode voltage of the NMOS tube M3 to the power supply voltage through the PMOS tube M9, so that the NMOS tube M3 enters a deep linear region, and a direct current path from the power supply to the ground in the current mirror image circuit is cut off; and the buffer circuit is used for outputting a reset signal according to the voltage change of the capacitor in the discharge delay circuit.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular, to a power-on reset circuit. Background Art

[0002] For digital integrated circuits and mixed-signal integrated circuits, a power-on reset circuit is an essential and important component. The power-on reset circuit is responsible for resetting the system to a certain determined state at the initial stage when the chip starts to be powered, so as to ensure the reliable startup of the chip. Since the power-on reset circuit has been in a working state since power-on, even after the reset ends, there is still a direct current path from the power supply to the ground in the traditional power-on reset circuit, resulting in the inability to eliminate the static power consumption.

[0003] In view of this, how to eliminate the static power consumption of the power-on reset circuit and reduce the power consumption of the power-on reset circuit has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0004] In view of the above technical status quo, the present invention provides a power-on reset circuit to eliminate the static power consumption of the power-on reset circuit.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A power-on reset circuit, comprising: a discharge delay circuit, a current mirror circuit, and a buffer circuit;

[0007] The discharge delay circuit includes: a capacitor and an NMOS transistor M4, and the NMOS transistor M4 is used to discharge the capacitor;

[0008] The current mirror circuit includes: an NMOS transistor M2, an NMOS transistor M3, and a PMOS transistor M9; wherein, the gate of the NMOS transistor M2 and the gate of the PMOS transistor M9 are respectively connected to the output end of the buffer circuit, and the gate of the NMOS transistor M3 is respectively connected to the source of the PMOS transistor M9, the drain of the NMOS transistor M2, and the gate of the NMOS transistor M4;

[0009] The current mirror circuit is used to turn off the NMOS transistor M2 after the reset signal ends, pull up the drain voltage of the NMOS transistor M3 to the power supply voltage through the PMOS transistor M9, so that the NMOS transistor M3 enters the deep linear region, and cut off the direct current path from the power supply to the ground in the current mirror circuit;

[0010] The buffer circuit includes two-stage inverters, and the two-stage inverters are used to output a reset signal according to the voltage change of the capacitor in the discharge delay circuit.

[0011] In an alternative embodiment of the present application, the NMOS transistor M3 and the NMOS transistor M4 are used to form a current mirror to delay the discharge time of the capacitor until the inverting threshold of the two-stage inverter in the buffer circuit is reached before power-on is completed.

[0012] In an alternative embodiment of the present application, in the current mirror, the current ratio flowing through the NMOS transistor M3 and the NMOS transistor M4 is N:1, where N is an integer greater than 1.

[0013] In an alternative embodiment of the present application, after the reset signal ends, the gate voltage of the NMOS transistor M4 is pulled up to the power supply voltage through the PMOS transistor M9, so that the NMOS transistor M4 enters the deep linear region and the capacitor is quickly discharged to zero potential.

[0014] In an alternative embodiment of the present application, the current mirror circuit further includes: a PMOS transistor M1 with an inverse ratio structure;

[0015] The gate of the PMOS transistor M1 is grounded, the drain is connected to the power supply, and the source is respectively connected to the source of the PMOS transistor M9, the drain of the NMOS transistor M2, and the gate of the NMOS transistor M4.

[0016] In an alternative embodiment of the present application, the two-stage inverter includes a first inverter and a second inverter;

[0017] The first inverter includes an NMOS transistor M5 and a PMOS transistor M6, and the second inverter includes an NMOS transistor M7 and a PMOS transistor M8;

[0018] Wherein, the gate of the NMOS transistor M5 is respectively connected to the gate of the PMOS transistor M6 and the output end of the discharge delay circuit; the source of the NMOS transistor M5 is grounded, the drain of the PMOS transistor M6 is connected to the power supply; the drain of the NMOS transistor M5 is connected to the source of the PMOS transistor M6;

[0019] The gate of the NMOS transistor M7 is respectively connected to the gate of the PMOS transistor M8 and the drain of the NMOS transistor M5; the source of the NMOS transistor M7 is grounded, the drain of the PMOS transistor M8 is connected to the power supply; the drain of the NMOS transistor M7 is connected to the source of the PMOS transistor M8 and serves as the output end of the buffer circuit to output a reset signal.

[0020] In an alternative embodiment of the present application, one end of the capacitor is respectively connected to the drain of the NMOS transistor M4 and the input end of the buffer circuit, and the other end of the capacitor is connected to the power supply;

[0021] The source of the NMOS transistor M4 is grounded.

[0022] Compared with the prior art, the power-on reset circuit provided by the present invention introduces an automatic switching mechanism controlled by the NMOS transistor M2 and the PMOS transistor M9 in the current mirror circuit. After the reset is completed, M9 is turned on and M2 is turned off. The drain voltage of the NMOS transistor M3 is pulled up to the power supply voltage through the PMOS transistor M9, so that the NMOS transistor M3 enters the deep linear region, cutting off the direct current path from the power supply to the ground in the current mirror circuit, thereby reducing the static power consumption to zero and reducing the power consumption of the power-on reset circuit. Description of the Drawings

[0023] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0024] Figure 1 is the structure of the power-on reset circuit provided by the embodiment of the present application Figure 1 ;

[0025] Figure 2 is the structure of the power-on reset circuit provided by the embodiment of the present application Figure 2 ;

[0026] Figure 3 is the voltage waveform diagram during the power-on process provided by the embodiment of the present application. Detailed Embodiments

[0027] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0028] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0029] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined. The meaning of "several" is one or more unless otherwise specifically defined.

[0030] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0031] In the description of the present invention, it should be noted that unless otherwise clearly specified and defined, the terms "mounted", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0032] For digital integrated circuits and mixed-signal integrated circuits, the power-on reset circuit is an essential and important component. The power-on reset circuit is responsible for resetting the system to a certain determined state in the initial stage when the chip starts to be powered, so as to ensure the reliable startup of the chip. Since the power-on reset circuit has been in a working state since power-on, even after the reset is completed, the traditional power-on reset circuit still has a direct current path from power to ground, resulting in the inability to eliminate the static power consumption.

[0033] In view of this, how to eliminate the static power consumption of the power-on reset circuit and reduce the power consumption of the power-on reset circuit has become a technical problem that needs to be solved urgently by those skilled in the art.

[0034] To solve the above technical problems, the present application provides a power-on reset circuit.

[0035] Please refer to Figure 1 , Figure 1 which is the structure of the power-on reset circuit provided by the embodiment of the present application. Figure 1 .

[0036] As Figure 1 shown, the power-on reset circuit includes: a discharge delay circuit, a current mirror circuit, and a buffer circuit.

[0037] The discharge delay circuit includes: a capacitor and an NMOS transistor M4, and the NMOS transistor M4 is used to discharge the capacitor.

[0038] The current mirror circuit includes: NMOS transistor M2, NMOS transistor M3, and PMOS transistor M9. Among them, the gates of the NMOS transistor M2 and the PMOS transistor M9 are respectively connected to the output terminal of the buffer circuit, and the gate of the NMOS transistor M3 is respectively connected to the source of the PMOS transistor M9, the drain of the NMOS transistor M2, and the gate of the NMOS transistor M4.

[0039] The current mirror circuit is configured to turn off the NMOS transistor M2 after the reset signal ends, pull up the drain voltage of the NMOS transistor M3 to the power supply voltage through the PMOS transistor M9, so that the NMOS transistor M3 enters the deep linear region, and cut off the DC conduction path from the power supply to the ground in the current mirror circuit.

[0040] The buffer circuit includes two-stage inverters, and the two-stage inverters are configured to output a reset signal according to the voltage change of the capacitor in the discharge delay circuit.

[0041] To facilitate understanding of the power-on reset circuit provided in this application, the power-on reset circuit will be introduced in detail below in combination with the circuit structures of the discharge delay circuit, the current mirror circuit, and the buffer circuit.

[0042] Please refer to Figure 2 , Figure 2 which is the structure of the power-on reset circuit provided in the embodiment of this application Figure 2 .

[0043] As Figure 2 shown, the current mirror circuit includes: M1 (i.e., PMOS transistor M1), NMOS transistor M2 (i.e., NMOS transistor M2), M3 (i.e., NMOS transistor M3), and M9 (i.e., PMOS transistor M9).

[0044] In the embodiment of this application, M1 is specifically a reverse ratio transistor structure (the channel width is much smaller than the channel length), and in the actual application process, it can be regarded as a resistor with a relatively large resistance value.

[0045] The gate of M1 is grounded, the drain is connected to the power supply Vdd, and the source is respectively connected to the source of M9, the drain of M2, and the gate of M3.

[0046] The gate of M2 is respectively connected to the gate of M9 and the output terminal of the buffer circuit; the source of M2 is connected to the drain of M3, and the drain of M2 is respectively connected to the source of M1, the source of M9, and the gate of M3.

[0047] The drain of M9 is connected to the power supply Vdd, the source of M9 is respectively connected to the source of M1, the drain of M2, and the gate of M3, and the gate of M9 is respectively connected to the gate of M2 and the output terminal of the buffer circuit.

[0048] The source of M3 is grounded, the drain of M3 is connected to the source of M2, and the gate of M3 is connected to the source of M1, the drain of M2, the source of M9, and the input terminal of the discharge delay circuit as the output terminal of the current mirror circuit.

[0049] The discharge delay circuit includes: a capacitor C1 and M4 (i.e., NMOS transistor M4).

[0050] Wherein, the first terminal of C1 is connected to the power supply Vdd, and the second terminal is respectively connected to the drain of M4 and the input terminal of the buffer circuit.

[0051] The source of M4 is grounded, and the gate of M4 is connected to the input terminal of the current mirror circuit as the input terminal of the discharge delay circuit.

[0052] The buffer circuit includes: M5 (i.e., NMOS transistor M5), M6 (i.e., PMOS transistor M6), M7 (i.e., NMOS transistor M7), M8 (i.e., PMOS transistor M8).

[0053] Wherein, M5 and M6 form a first inverter; the gates of M5 and M6 are connected and used as the input terminal of the buffer circuit to be connected to the output terminal of the discharge delay circuit; the source of M5 is grounded, and the source of M6 is connected to the power supply Vdd; the drains of M5 and M6 are connected and used as the output terminal of the first inverter to be connected to the gates of M7 and M8.

[0054] M7 and M8 form a second inverter; the gates of M7 and M8 are connected; the source of M7 is grounded, and the source of M8 is connected to the power supply Vdd; the drains of M7 and M8 are connected and used as the output terminal of the buffer circuit to be connected to the gates of M9 and M2 in the current mirror circuit.

[0055] Furthermore, to facilitate understanding of the working principle of the above power-on reset circuit, the following will introduce it in detail in combination with the reset process of the power-on reset circuit.

[0056] To facilitate understanding of the power-on process of the power-on reset circuit, the following will take the nodes at the drain of M2, the source of M9, the source of M1, and the gate of M3 as node X; the node at the second terminal of the capacitor C1 and the drain of M4 as node Y, and the output terminal of the buffer circuit as node Z.

[0057] Furthermore, please refer to Figure 3 , Figure 3 which is the voltage waveform diagram of the power-on process provided by the embodiment of the present application.

[0058] As shown in Figure 3As shown, at time T0, the voltages of nodes X, Y, and Z are all 0. After that, the power supply Vdd starts to power on. Affected by capacitor C1, at this time, node Y is in a high impedance state, and the voltage across capacitor C1 cannot change suddenly. The voltage of node Y will gradually rise following the power supply voltage VDD, causing the voltage of node Z at the output of the buffer circuit to also rise with the power supply voltage VDD. Before the power supply voltage VDD rises to the threshold voltages of M1, M2, and M3, M1, M2, M3, and M9 are all in the off state. At this time, node X remains at zero potential.

[0059] At time T1, the power supply voltage is higher than the threshold voltages of M1, M2, and M3, M1, M2, and M3 turn on, and the voltage of node X rises to the gate-source voltage V1 when M3 operates in the saturation region. At the same time, M4 conducts, discharging capacitor C1.

[0060] In the actual application process, in order to ensure effective reset, capacitor C1 is usually designed as a large capacitor, thereby extending the reset time. However, this will occupy a large layout area, resulting in an increase in chip cost.

[0061] In an alternative embodiment of the present application, in order to save chip manufacturing cost, M3 and M4 in the embodiments of the present application are designed as an electron mirror current structure, so that the current ratio flowing through M3 and M4 is N:1 (where N is an integer greater than 1).

[0062] In the actual application process, the electron mirror current structure can be constructed by increasing the aspect ratio of M3, thereby reducing the current flowing through M4 by N times during the discharge process, and then extending the reset time. As Figure 3 shown, Figure 3 is the voltage waveform diagram after adopting the electron mirror current structure.

[0063] Before the power-on is completed, the voltage of node Y rises with the voltage of power supply VDD, but the rising rate decreases.

[0064] At time T2, the power supply completes power-on. After that, the voltage of node Y is determined by the discharge current of M4. Since the discharge current is small, the voltage of node Y will slowly decrease at a constant rate until it reaches the inversion threshold of the first inverter in the buffer circuit. The duration of this process is the duration of the reset signal.

[0065] At time T3, the voltage of node Y reaches the inversion threshold of the first inverter in the buffer circuit, causing the voltage of node Z to flip from the power supply voltage VDD (i.e., logic 1) to zero potential (i.e., logic 0).

[0066] At time T4, the voltage of node Z is zero, M9 is turned on, M2 is turned off, and the drain voltage of M3 (i.e., the voltage of node X) is quickly pulled up to the power supply voltage through M9. The operating state of M3 changes from the saturation region to the deep linear region, cutting off the DC conduction path from the power supply to ground in the current mirror circuit.

[0067] At time T5, the voltage of node X is the power supply voltage, the operating state of M4 changes from the saturation region to the deep linear region, capacitor C1 discharges quickly, and the voltage of node Y is quickly pulled down to zero by M4.

[0068] In summary, for the power-on reset circuit provided in this application, by introducing an automatic switch mechanism controlled by the NMOS transistor M2 and the PMOS transistor M9 in the current mirror circuit, after the reset is completed, M9 is turned on and M2 is turned off. The drain voltage of the NMOS transistor M3 is pulled up to the power supply voltage through the PMOS transistor M9, so that the NMOS transistor M3 enters the deep linear region, cutting off the DC conduction path from the power supply to ground in the current mirror circuit, thereby reducing the static power consumption to zero and reducing the power consumption of the power-on reset circuit.

[0069] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. A power-on reset circuit, characterized in that: include: Discharge delay circuit, current mirror circuit and buffer circuit; The discharge delay circuit comprises: a capacitor and an NMOS tube M4, wherein the NMOS tube M4 is used to discharge the capacitor; The current mirror circuit comprises: an NMOS tube M2, an NMOS tube M3 and a PMOS tube M9; wherein the gate of the NMOS tube M2 and the gate of the PMOS tube M9 are respectively connected to the output end of the buffer circuit, and the gate of the NMOS tube M3 is respectively connected to the source of the PMOS tube M9, the drain of the NMOS tube M2 and the gate of the NMOS tube M4; The current mirror circuit is used to turn off the NMOS tube M2 after the reset signal ends, and pull up the drain voltage of the NMOS tube M3 to the power supply voltage through the PMOS tube M9, so that the NMOS tube M3 enters the deep linear region, and cuts off the DC path from the power supply to the ground in the current mirror circuit; The buffer circuit includes a two-stage inverter, and the two-stage inverter is used to output a reset signal according to the voltage change of the capacitor in the discharge delay circuit.

2. The power-on reset circuit according to claim 1, characterized in that: The NMOS transistor M3 and the NMOS transistor M4 are used to form a current mirror to delay the discharge time of the capacitor before power-on is completed until the inversion threshold of the two-stage inverter in the buffer circuit is reached.

3. The power-on reset circuit according to claim 2, characterized in that: In the current mirror, the ratio of the current flowing through the NMOS transistor M3 to the current flowing through the NMOS transistor M4 is N:1, where N is an integer greater than 1.

4. The power-on reset circuit according to claim 2 or 3, characterized in that: After the reset signal ends, the gate voltage of the NMOS tube M4 is pulled up to the power supply voltage through the PMOS tube M9, so that the NMOS tube M4 enters the deep linear region, and the capacitor is quickly discharged to zero potential.

5. The power-on reset circuit according to claim 1, characterized in that: The current mirror circuit further includes: a PMOS tube M1 with an inverse ratio tube structure; The gate of the PMOS tube M1 is grounded, the drain is connected to a power source, and the source is respectively connected to the source of the PMOS tube M9 , the drain of the NMOS tube M2 , and the gate of the NMOS tube M4 .

6. The power-on reset circuit according to claim 1, characterized in that: The two-stage inverter comprises a first inverter and a second inverter; The first inverter includes an NMOS tube M5 and a PMOS tube M6, and the second inverter includes an NMOS tube M7 and a PMOS tube M8; The gate of the NMOS tube M5 is connected to the gate of the PMOS tube M6 and the output end of the discharge delay circuit respectively; the source of the NMOS tube M5 is grounded, and the drain of the PMOS tube M6 is connected to the power supply; the drain of the NMOS tube M5 is connected to the source of the PMOS tube M6; The gate of the NMOS tube M7 is connected to the gate of the PMOS tube M8 and the drain of the NMOS tube M5 respectively; the source of the NMOS tube M7 is grounded, and the drain of the PMOS tube M8 is connected to a power supply; the drain of the NMOS tube M7 is connected to the source of the PMOS tube M8, and serves as the output end of the buffer circuit to output a reset signal.

7. The power-on reset circuit according to claim 1, characterized in that: One end of the capacitor is connected to the drain of the NMOS tube M4 and the input end of the buffer circuit respectively, and the other end of the capacitor is connected to a power supply; the source of the NMOS tube M4 is grounded.

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