Vector coprocessor and vector calculation method

Abstract

The invention discloses a vector coprocessor and a vector calculation method, and relates to the technical field of processors. The vector coprocessor comprises an arbitration module, a distributor module, a function module and a data path; the arbitration module is used for receiving the calculation tasks from the main processor, screening vector tasks from the calculation tasks and filtering non-vector tasks in the calculation tasks; the dispatcher module is used for determining the parallelism degree and the task queue of the vector tasks and dispatching the vector tasks according to the parallelism degree and the task queue; the function module is used for decomposing the vector task into a plurality of subtasks and determining a data path corresponding to each subtask; distributing the subtasks to the data paths, and reducing the calculation results corresponding to the data paths to generate target results corresponding to the vector tasks; and the data path is used for calculating the subtasks and sending a calculation result to the functional module. Data redundancy storage is avoided, and the working efficiency of the processor in vector calculation is improved.

Description

Technical Field

[0001] This application relates to the technical field of processors, and particularly to a vector co-processor and a vector calculation method. Background Art

[0002] In current technologies, general-purpose processors have significant limitations when dealing with vector calculation tasks. In a multi-core CPU architecture, if each core integrates a vector calculation unit, it will lead to a substantial increase in chip area and power consumption. For example, a 16-core system needs to repeat the integration of 16 sets of vector modules, resulting in serious redundancy of hardware resources.

[0003] The architecture design of general-purpose processors is oriented towards generality and is difficult to be deeply optimized for vector calculations (such as matrix operations, convolutions, large-scale data reduction), resulting in low computing efficiency. Especially in data-intensive scenarios such as AI training and scientific simulations, it is difficult to meet the requirements of high throughput and low latency. Summary of the Invention

[0004] This application provides a vector co-processor and a vector calculation method to solve the problems of hardware redundancy and low energy efficiency in traditional solutions.

[0005] In a first aspect, this application provides a vector co-processor, including an arbitration module, a dispatcher module, a functional module, and a data path; The arbitration module is configured to receive a calculation task from a main processor, screen out vector tasks from the calculation task, and filter non-vector tasks in the calculation task; The dispatcher module is configured to determine the parallelism degree and task queue of the vector task, and dispatch the vector task according to the parallelism degree and task queue; The functional module is configured to decompose the vector task into multiple subtasks, and determine the data path corresponding to each subtask; allocate the subtasks to the data path, and reduce the calculation results corresponding to each data path to generate the target result corresponding to the vector task; The data path is configured to calculate the subtask and send the calculation result to the functional module.

[0006] In a second aspect, this application provides a vector calculation method, which is applied to the vector co-processor in the first aspect, including: When receiving a vector task sent by the main processor, determining the parallelism degree and task queue of the vector task through the dispatcher module corresponding to the co-processor; Sending the vector task to the functional module corresponding to the co-processor according to the task queue, so that the functional module decomposes the vector task into multiple subtasks according to a preset decomposition rule; Determining the target path corresponding to the subtask according to the parallelism degree and the real-time load of each data path; And send the subtasks to the corresponding target paths so that the target paths calculate the calculation results corresponding to the subtasks; Reduce the calculation results into the target result corresponding to the vector task; Send the target result to the main processor.

[0007] In this application, by decoupling the vector calculation task from the main processor core, designing an independent coprocessor module, and combining the dynamic scheduling, task decomposition, and reduction aggregation mechanisms, the resource utilization and calculation efficiency are significantly optimized. This architecture not only supports wide-bit-width or multi-channel parallel computing, but also realizes the dynamic mounting of multiple coprocessors and data consistency management through the collaborative design of the crossbar switch and the first-level cache, thus effectively solving the problems of hardware redundancy, low energy efficiency, and insufficient scalability existing in the traditional solutions, and providing an efficient and flexible solution for data-intensive applications.

[0008] The further effects of the above non-conventional preferred methods will be described in conjunction with the specific embodiments below. Brief Description of the Drawings

[0009] In order to more clearly illustrate the embodiments of the present application or the existing technical solutions, the following will briefly introduce the drawings required for the description of the embodiments or the existing technical solutions. Obviously, the drawings in the following description are only some embodiments recorded in the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0010] Figure 1 Structural schematic diagram of a vector coprocessor provided by an embodiment of the present application; Figure 2 Structural schematic diagram of an arbitration module in a vector coprocessor provided by an embodiment of the present application; Figure 3 Structural schematic diagram of a distributor module in a vector coprocessor provided by an embodiment of the present application; Figure 4 Structural schematic diagram of a functional module in a vector coprocessor provided by an embodiment of the present application; Figure 5 Structural schematic diagram of a data path in a vector coprocessor provided by an embodiment of the present application; Figure 6 Structural schematic diagram of a calculation unit in a data path of a vector coprocessor provided by an embodiment of the present application; Figure 7 Flow schematic diagram of a vector calculation method provided by an embodiment of the present application. Detailed Description of the Embodiments

[0011] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without creative efforts belong to the scope of protection of this application.

[0012] In the current technology, general-purpose processors have significant limitations when processing vector computing tasks. In a multi-core CPU architecture, if each core integrates a vector computing unit, it will lead to a significant increase in chip area and power consumption. For example, a 16-core system needs to repeat the integration of 16 sets of vector modules, resulting in serious redundancy of hardware resources.

[0013] The architecture design of general-purpose processors is oriented towards generality and is difficult to deeply optimize for vector computing (such as matrix operations, convolutions, large-scale data reduction), resulting in low computing efficiency. Especially in data-intensive scenarios such as AI training and scientific simulations, it is difficult to meet the requirements of high throughput and low latency.

[0014] In view of this, this application provides a vector coprocessor. See Figure 1 As shown, it is a specific embodiment of the vector coprocessor provided by this application. In this embodiment, the vector coprocessor includes: an arbitration module 101, a dispatcher module 102, a functional module 103, and a data path 104.

[0015] The arbitration module is used to receive computing tasks from the main processor, filter out vector tasks from the computing tasks, and filter out non-vector tasks in the computing tasks.

[0016] The dispatcher module is used to determine the parallelism and task queue of vector tasks, and dispatch vector tasks according to the parallelism and task queue.

[0017] The functional module is used to decompose vector tasks into multiple subtasks, determine the data paths corresponding to each subtask; allocate the subtasks to the data paths, and reduce the calculation results corresponding to each data path to generate the target result corresponding to the vector task.

[0018] The data path is used to calculate subtasks and send the calculation results to the functional module.

[0019] The vector coprocessor can be connected to the level-1 cache of the main processor through a crossbar switch. The main processor can preferably be a processor with the RISC-V architecture because RISC-V is an open-source processor, and its modular instruction set allows developers to directly optimize the hardware interaction process through custom extensions (such as adding coprocessor-specific instructions). For example, by extending vector memory access instructions or coprocessor control instructions, the main processor can distribute tasks to the coprocessor with lower latency while reducing data movement overhead.

[0020] As Figure 2 shown, it is a schematic structural diagram of the arbitration module in this embodiment. The arbitration module includes: a parsing unit 1011 and a feedback unit 1012. The parsing unit is used to parse the computing task to identify whether the computing task is a vector task; the feedback unit is used to send the vector task to the dispatcher module when the computing task is a vector task; when the computing task is a non-vector task, generate a rejection signal and return the computing task to the main processor.

[0021] As the entry of the coprocessor, the arbitration module is responsible for receiving the computing tasks sent by the main processor and classifying and filtering them. The built-in parsing unit of the module dynamically identifies the task type by deeply parsing the instruction stream sent by the main processor. For example, it determines whether the task is a vector calculation based on the instruction opcode, data format, and memory access mode. If scalar operations or control instructions are detected, it is determined as a non-vector task.

[0022] The feedback unit then performs dynamic task allocation according to the parsing result. For the identified vector tasks, the feedback unit pushes them to the dispatcher module through a dedicated channel. If the computing task is determined to be of non-vector type, the feedback unit generates a rejection signal and returns the task to the main processor through the crossbar switch, ensuring that the main core can promptly recycle the task and reallocate it to other execution units.

[0023] As Figure 3 shown, it is a schematic structural diagram of the dispatcher module in this embodiment. The dispatcher module includes: a queue management unit 1021 and a parallelism decision unit 1022. The queue management unit is used to receive the vector tasks sent by the arbitration module and generate a task queue for the vector tasks according to the preset priority rules; the parallelism decision unit is used to parse the task characteristics corresponding to the vector tasks to determine the parallelism corresponding to the vector tasks according to the task characteristics.

[0024] The dispatcher module achieves efficient task allocation and resource optimization through a multi-level collaboration mechanism. The queue management unit receives vector tasks from the arbitration module and sorts the tasks according to preset priority rules (such as task urgency, data dependencies, or instruction types). For example, in an AI inference scenario, real-time inference requests may be marked as high priority and enter the queue ahead of offline training tasks; for consecutive tasks with data dependencies (such as multi-stage matrix factorization), the queue management unit will ensure the execution order through a label association mechanism to avoid calculation errors caused by out-of-order processing. The scheduling policy of the queue (such as FIFO, round-robin, or preemptive) can be dynamically configured according to the application scenario to adapt to different requirements from low-latency real-time computing to high-throughput batch processing.

[0025] The parallelism decision unit dynamically determines the optimal parallelism by analyzing the characteristic parameters of vector tasks (such as data scale, instruction complexity, memory access pattern). For example, when processing a 2048-dimensional vector multiply-add operation, if the bit width of each data path is 128 bits, the parallelism decision unit can determine to apply 16 data paths for the operation. In addition, the parallelism decision unit can also monitor the load status of data paths in real time and then make dynamic trade-offs in combination with task characteristics. For example, maximize parallelism in compute-intensive tasks to increase throughput, and moderately reduce parallelism in memory-intensive tasks to reduce cache occupancy.

[0026] As Figure 4 shown, it is a schematic structural diagram of the functional module in the embodiment. The functional module includes: a reduction unit 1031 and a register control unit 1032. The reduction unit is used to decompose vector tasks into subtasks and allocate the subtasks in parallel to each data path; perform a reduction operation on the calculation results corresponding to each data path to generate a target result; the register control unit is used to temporarily store each calculation result corresponding to the model of each data path; send the target result to the main processor through the first-level cache corresponding to the main processor.

[0027] The role of the functional module is the decomposition of vector tasks and the integration of calculation results. The reduction unit receives vector tasks from the dispatcher module and splits the vector tasks into sub-tasks with appropriate granularity according to the bit width and parallelism capabilities of the data paths. For example, when processing a large-scale matrix multiplication, the reduction unit may partition by rows or columns, allocate each sub-block to different data paths, and mark the dependencies between sub-tasks to maintain calculation correctness.

[0028] After the subtask completes the calculation in the data path, the reduction unit aggregates the scattered intermediate results through a hardware-level reduction tree (such as an addition tree, a maximum tree) or a software-configurable mode (such as accumulation, multiplication, fused multiply-add). For example, during the gradient descent process of AI training, the reduction unit can accumulate the local gradients output by multiple data paths into a global gradient. This process achieves low latency through a multi-stage pipeline design and also supports dynamic switching of the reduction mode to adapt to different algorithm requirements.

[0029] The register control unit is responsible for data transfer and consistency. The calculation result of each data path is temporarily stored in the distributed register bank of this unit when it is completed, and its design can adopt a double-buffer mechanism. When one set of registers receives new results, the other set writes the ready data in batches to the first-level cache of the main processor, thus hiding the data transfer latency.

[0030] The register control unit also ensures the timing consistency of the results of multiple data paths through a tag matching mechanism. For example, in the reduction operation, the aggregation operation of the reduction unit is triggered only when the results of all relevant subtasks are ready, avoiding errors caused by missing some data.

[0031] As Figure 5 shown, it is a schematic structural diagram of the data path in this embodiment. The data path includes: a data controller unit 1041, a buffer unit 1042, a calculation unit 1043, and a write-back unit 1044. The data controller unit is used to receive the calculation request of the functional module and feedback the data ready signal; the buffer unit is used to sequentially buffer the subtasks and temporarily store the intermediate data of multi-cycle calculations; the calculation unit is used to calculate the subtasks to generate calculation results; the write-back unit is used to send the calculation results to the register control unit.

[0032] As the execution unit of actual calculations, the data path realizes the efficient execution of tasks and data flow management through pipelining design. The data controller unit is responsible for receiving the calculation requests from the functional module and coordinating the data transfer rhythm through a two-way handshake protocol.

[0033] The front-end input buffer of the buffer unit arranges the subtask data in sequence to solve the misalignment problem caused by differences in task distribution timing or data arrival speed. For example, in convolution operations, it ensures that the sliding window data is sent to the calculation unit block by block according to the calculation cycle. The back-end has a multi-cycle temporary storage area for saving the intermediate results of long-latency calculations. For example, in iterative reduction tasks, partial sum values are cyclically written into the buffer until the final result is generated.

[0034] The calculation unit is composed of a vector multiplication sub-unit and a vector arithmetic logic sub-unit, and the two work together to cover the diverse requirements of vector calculations. As Figure 6As shown in the figure, it is a schematic structural diagram of the computing unit in this embodiment. The computing unit includes: a vector multiplication subunit 4301 and a vector arithmetic logic subunit 4302. The vector multiplication subunit is used to perform vector multiplication operations; the vector arithmetic logic subunit is used to perform vector addition, subtraction, displacement, and logical operations.

[0035] The vector multiplication subunit is designed specifically for high-density multiplication operations. It supports large-scale parallel vector multiplication operations through hardware-level pipeline optimization. For example, in matrix multiplication or convolution calculations, it can simultaneously process vector multiplication operations of multiple data blocks, significantly improving the computing throughput. Its architecture is customized for the characteristics of multiplication repeatability and data locality. For example, Booth encoding or Wallace tree structure is used to accelerate the generation and accumulation of partial products, thus achieving low-latency and energy-efficient operations in AI training or scientific simulations.

[0036] The vector arithmetic logic subunit focuses on vector addition, subtraction, displacement, and logical operations, providing flexible arithmetic and data manipulation capabilities. In the vector addition and subtraction scenarios, the vector arithmetic logic subunit supports parallel processing of multi-precision data and reduces the critical path delay through carry chain optimization; the displacement function can be used to quickly adjust data alignment or implement scaling operations, such as batch adjusting the pixel value range in image processing; the logical operation module serves tasks such as data mask generation and conditional filtering. For example, in sparse matrix calculations, it dynamically filters out invalid elements.

[0037] The co-design of the vector multiplication subunit and the vector arithmetic logic subunit allows for pipelined execution of complex instructions. For example, first, the vector arithmetic logic subunit completes the displacement alignment of vector data, then the vector multiplication subunit performs the multiplication operation, and finally, the vector arithmetic logic subunit realizes the accumulation and reduction. Such hardware-level cooperation significantly reduces the data transfer overhead, especially showing significant advantages in real-time signal processing or neural network inference.

[0038] The write-back unit is responsible for transferring the calculation result to the register control unit. The write-back unit can adopt a transmission protocol with a verification mechanism to ensure the integrity of data during high-speed transmission. For example, in floating-point operations of scientific computing, the write-back unit will verify the exponent and mantissa parts separately to detect and correct bit flip errors caused by circuit noise. At the same time, the write-back unit can also support result compression and format conversion functions. For example, it splices scattered 128-bit intermediate results into a 512-bit vector and then writes them into the register in batches, reducing the bus transaction overhead.

[0039] It can be seen from the above technical solutions that the beneficial effects of this embodiment are: A vector coprocessor includes: an arbitration module, a dispatcher module, a functional module, and a data path; the arbitration module is configured to receive a computing task from a main processor, screen out vector tasks from the computing task, and filter out non-vector tasks in the computing task; the dispatcher module is configured to determine the parallelism and task queue of the vector task, and dispatch the vector task according to the parallelism and task queue; the functional module is configured to decompose the vector task into multiple subtasks, and determine the data path corresponding to each subtask; allocate the subtasks to the data path, and reduce the calculation results corresponding to each data path to generate a target result corresponding to the vector task; the data path is configured to calculate the subtasks and send the calculation results to the functional module. This avoids redundant data storage and improves the working efficiency of the processor in vector calculation.

[0040] As Figure 7 shown, it is a specific embodiment of a vector calculation method of the present application. The method in this embodiment is applied to Figures 1-6 the vector coprocessor.

[0041] Step 701, when receiving a vector task sent by the main processor, determine the parallelism and task queue of the vector task through the dispatcher module corresponding to the coprocessor.

[0042] Generate a task queue for the vector task according to a preset priority rule; analyze the task characteristics corresponding to the vector task to determine the parallelism corresponding to the vector task according to the task characteristics.

[0043] The dispatcher module sorts and caches the tasks according to a preset dynamic priority rule (such as task deadline, data dependency chain, or instruction type). For example, in a real-time video processing scenario, a high-frame-rate rendering task may be marked as an urgent priority and enter the head of the queue first, while for an offline data analysis task, a bandwidth-aware strategy is adopted to batch load only when the cache is idle.

[0044] In the task receiving stage, the tasks are classified and feature-extracted based on metadata analysis (such as instruction type tags, data scale descriptors). For example, in an AI training scenario, a gradient update task is identified as having high parallelism requirements because it involves large-scale matrix multiplication and addition operations. And a parameter synchronization task is classified as a low priority because it depends on global communication.

[0045] Parallelism determination can be divided into static and dynamic mechanisms. The static mechanism generates initial parallelism suggestions based on preset hardware parameters. For example, a 2048-bit vector is split into 16 sub-tasks according to a 128-bit width. The dynamic mechanism flexibly adjusts the parallelism by monitoring the computing progress of each data path in real time (such as instruction throughput and cache miss rate). If it is detected that some sub-tasks are delayed due to data dependencies or resource contention, the system automatically shrinks the parallelism and reallocates redundant tasks to idle resources to avoid a decline in overall efficiency.

[0046] Step 702: Send vector tasks to the corresponding functional modules of the coprocessor according to the task queue, so that the functional modules decompose the vector tasks into multiple sub-tasks according to the preset decomposition rules.

[0047] Parse the data structure of the vector task to determine the corresponding data chunking method according to the data structure; determine the data granularity corresponding to the sub-tasks according to the parallelism and the bit-width limit of the data path; decompose the vector task into multiple sub-tasks according to the data chunking method and the data granularity.

[0048] When the vector tasks in the task queue are sent to the functional modules, multi-dimensional analysis of the data organization form of the tasks is required. For example, for two-dimensional matrix operations (such as convolution or matrix multiplication), according to the memory layout (row-major or column-major) and data locality characteristics, select row-chunking, column-chunking, or checkerboard-chunking strategies.

[0049] If the task involves high-dimensional tensors (such as the attention weight matrix in an AI model), then use slicing or hierarchical chunking methods to ensure that the data blocks of each sub-task are continuously distributed in memory and strictly aligned to the cache line boundary to minimize the performance loss caused by cross-row access. For irregular data structures (such as sparse matrices or graph data), the system dynamically chunks through tuple index partitioning or non-zero element clustering techniques. For example, the non-zero elements of a sparse matrix are split into balanced sub-blocks according to the density distribution to reduce the idle waiting of computing resources.

[0050] After determining the data chunking method, it is also necessary to dynamically adjust the scale of the sub-tasks in combination with the parallelism and the bit-width limit of the data path. For example, if the coprocessor supports 8 data paths and the bit-width of each data path is 128 bits, then a 1024-bit vector task will be split into 8 sub-tasks, and each sub-task processes 128-bit data.

[0051] For floating-point operation scenarios, the data granularity also needs to consider computational precision alignment. If the task requires FP32 precision (32 bits per element), then each sub-task contains 4 elements (128 / 32); if it is INT8 quantization calculation, then 16 elements (128 / 8) can be processed in parallel to maximize hardware utilization.

[0052] Integrate the chunking method with the data granularity to generate a set of executable subtasks. Taking real-time object detection in image processing as an example, after the input image frame (e.g., 1080p resolution) is parsed into a two-dimensional pixel matrix, it is chunked into 16×16 pixel blocks (matching 4 FP32 pixels under the 128-bit data path width), and split into 256 subtasks according to the parallelism (e.g., 16 data paths) (each data path processes 16 blocks). Each subtask carries metadata tags (such as block coordinates, reduction mode), and ensures the timing constraints through the dependency check module.

[0053] Step 703: Determine the target path corresponding to the subtask according to the parallelism and the real-time load of each data path.

[0054] When the subtask is sent from the functional module to the data path, the system needs to analyze the decomposition scale of the current subtask and the upper limit of the hardware resources. For example, if the initial parallelism is set to 16 subtasks, when it is detected that some data paths are unavailable due to high load or hardware errors, the system will dynamically reduce the parallelism to 12 and reallocate the redundant tasks to the low-load data paths.

[0055] This process needs to combine with the real-time load monitoring network to continuously collect the key indicators of each data path (such as instruction throughput, cache hit rate, power consumption threshold, error counter) to form a global view of the resource status. For example, in the AI inference scenario, if a certain Lane has its temperature increased due to frequent execution of multiply-accumulate operations, the system will mark this data path as a throttling state and preferentially allocate new tasks to the path with better cooling conditions.

[0056] Step 704: Send the subtask to the corresponding target path so that the target path calculates the calculation results corresponding to each subtask.

[0057] Parse the instruction type corresponding to the subtask; call the corresponding computing unit based on the instruction type; use the computing unit to process the subtask to determine the calculation result.

[0058] It is necessary to decode the operation code carried by the subtask to dynamically identify the instruction type (such as vector multiplication, addition, displacement or logical operation). For example, if the subtask instruction is "VMUL-128-FP32", the system determines that it needs to call the vector multiplication subunit to perform single-precision floating-point multiplication. If the instruction is "VALU-AND-INT8", then it is necessary to call the vector arithmetic logic subunit to complete the bitwise AND operation of 8-bit integers.

[0059] During the parsing process, the operand format (such as data bit width, memory address alignment information) can also be extracted to configure parameters for the computing unit (such as the Booth encoding mode of the multiplier, the carry chain structure of the ALU) to ensure the precise matching of the hardware resources and the task requirements.

[0060] Step 705: Reduce each calculation result to the target result corresponding to the vector task.

[0061] In the calculation process of the vector coprocessor, result reduction can integrate the calculation results of subtasks scattered in each data path into the final target result of the vector task through a multi-level aggregation and consistency control mechanism. When all subtasks complete the calculation in the target path, the reduction unit first confirms the integrity of the data. For example, in a matrix multiplication task, the reduction operation is triggered only when the results of all row-column multiply-add subtasks are ready.

[0062] For accumulative tasks (such as parameter update in gradient descent), the reduction unit gradually merges the subtask results through a pipelined adder hierarchy (such as a 4-stage pipelined adder tree), and can complete parallel accumulation of outputs from dozens of data paths in a single cycle.

[0063] For extreme value screening tasks (such as maximum pooling in image filtering), the extreme values are gradually passed through a comparator tree to finally output the global maximum or minimum. The reduction mode (such as accumulation, multiplication, logical merging) is dynamically configured by task instructions. For example, in AI inference, the exponential sum reduction of the Softmax layer needs to first accumulate the local sums of all subtasks and then normalize the probability distribution through a division tree.

[0064] Step 706: Send the target result to the main processor.

[0065] When the target result is integrated in the reduction unit, the register control unit writes the target result to the first-level cache in batches according to the cache line alignment principle.

[0066] To ensure data consistency, the system can adopt a lightweight cache coherence protocol. When multiple coprocessors share the first-level cache, the protocol manages data ownership through status tags. For example, in a heterogeneous computing platform, if the GPU coprocessor and the vector coprocessor access the same cache line simultaneously, the protocol will automatically coordinate the access order to avoid data contention. In addition, the access permission of the first-level cache is dynamically allocated through a hardware lock mechanism (such as atomic operation instructions) to ensure that the data read by the main processor is always the latest version.

[0067] From the above technical solutions, the beneficial effects of this embodiment are as follows: When receiving a vector task sent by the main processor, determine the parallelism degree and task queue of the vector task through the corresponding dispatcher module of the coprocessor; send the vector task to the corresponding functional module of the coprocessor according to the task queue, so that the functional module decomposes the vector task into multiple subtasks according to the preset decomposition rules; determine the target path corresponding to the subtask according to the parallelism degree and the real-time load of each data path; and send the subtask to the corresponding target path, so that the target path calculates the calculation results corresponding to each subtask; reduce each calculation result into the target result corresponding to the vector task; and send the target result to the main processor. Through the collaborative mechanism of dynamic task scheduling, elastic resource allocation and efficient result reduction, the execution efficiency and system adaptability of vector calculation are significantly improved.

[0068] Those skilled in the art should understand that the embodiments of the present application can be provided as a method or a computer program product. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or a combination of software and hardware.

[0069] The embodiments in the present application are all described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiments.

[0070] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, so that a process, method, commodity or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, commodity or device. Without further limitation, the element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, commodity or device including the element.

[0071] The above are only the embodiments of the present application and are not used to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

Claims

1. A vector coprocessor, characterized in that, It includes an arbitration module, a dispatcher module, a functional module, and a data path; The arbitration module is used to receive computing tasks from a main processor, filter out vector tasks from the computing tasks, and filter non-vector tasks in the computing tasks; The dispatcher module is used to determine the parallelism and task queue of the vector tasks, and dispatch the vector tasks according to the parallelism and the task queue; The functional module is used to decompose the vector tasks into multiple subtasks, and determine the data paths corresponding to the subtasks; Allocate the subtasks to the data paths, and reduce the calculation results corresponding to the data paths to generate the target result corresponding to the vector task; The data path is used to calculate the subtasks and send the calculation results to the functional module.

2. The vector coprocessor according to claim 1, wherein The arbitration module includes: A parsing unit and a feedback unit; The parsing unit is used to parse the computing tasks to identify whether the computing tasks are vector tasks; The feedback unit is used to send the vector tasks to the dispatcher module when the computing tasks are the vector tasks; when the computing tasks are the non-vector tasks, generate a rejection signal and return the computing tasks to the main processor.

3. The vector co-processor according to claim 1, wherein The dispatcher module includes: A queue management unit and a parallelism decision unit; The queue management unit is used to receive the vector tasks sent by the arbitration module and generate a task queue for the vector tasks according to preset priority rules; The parallelism decision unit is used to parse the task characteristics corresponding to the vector tasks to determine the parallelism corresponding to the vector tasks according to the task characteristics.

4. The vector coprocessor according to claim 1, wherein The functional module includes: A reduction unit and a register control unit; The reduction unit is used to decompose the vector tasks into the subtasks, and parallelly allocate the subtasks to the data paths; perform a reduction operation on the calculation results corresponding to the data paths to generate the target result; The register control unit is used to temporarily store the calculation results corresponding to the data path models; send the target result to the main processor through the first-level cache corresponding to the main processor.

5. The vector coprocessor according to claim 4, wherein The data path includes: A data controller unit, a buffer unit, a calculation unit, and a write-back unit; The data controller unit is used to receive the calculation request of the functional module and feedback a data ready signal; The buffer unit is used to sequentially buffer the subtasks and temporarily store intermediate data for multi-cycle calculations; The calculation unit is used to calculate the subtasks to generate the calculation results; The write-back unit is used to send the calculation results to the register control unit.

6. The vector coprocessor according to claim 5, wherein The calculation unit includes: A vector multiplication sub-unit and a vector arithmetic logic sub-unit; The vector multiplication sub-unit is used to perform vector multiplication operations; The vector arithmetic logic sub-unit is used to perform vector addition, subtraction, displacement, and logical operations.

7. A vector calculation method, characterized in that, The method is applied to the vector coprocessor according to any one of claims 1-6, and includes: When receiving a vector task sent by the main processor, determine the parallelism degree and task queue of the vector task through the dispatcher module corresponding to the coprocessor; Send the vector task to the function module corresponding to the coprocessor according to the task queue, so that the function module decomposes the vector task into multiple subtasks according to a preset decomposition rule; Determine the target path corresponding to the subtask according to the parallelism degree and the real-time load of each data path; And send the subtask to the corresponding target path, so that the target path calculates the calculation results corresponding to each subtask; Reduce each calculation result into the target result corresponding to the vector task; Send the target result to the main processor.

8. The method according to claim 7, characterized in that The determining the parallelism degree and task queue of the vector task through the dispatcher module corresponding to the coprocessor includes: Generate a task queue for the vector task according to a preset priority rule; Analyze the task characteristics corresponding to the vector task to determine the parallelism degree corresponding to the vector task according to the task characteristics.

9. The method according to claim 7, characterized in that The function module decomposing the vector task into multiple subtasks according to a preset decomposition rule includes: Analyze the data structure of the vector task to determine the data chunking method corresponding to the vector task according to the data structure; Determine the data granularity corresponding to the subtask according to the parallelism degree and the bit-width limit of the data path; Decompose the vector task into multiple subtasks according to the data chunking method and the data granularity.

10. The method according to claim 7, wherein The target path calculating the calculation results corresponding to each subtask includes: Analyze the instruction type corresponding to the subtask; Call the corresponding calculation unit based on the instruction type; Use the calculation unit to process the subtask to determine the calculation result.

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